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IEEE Journal of Solid-State Circuits, Volume 41
Volume 41, Number 1, January 2006
- Jan Van der Spiegel, Ram K. Krishnamurthy, Sreedhar Natarajan, Chih-Kong Ken Yang:
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. 3-6 - Marc-Alexandre Dubois, Jean-François Carpentier, Pierre Vincent, Christophe Billard, Guy Parat, Claude Müller, Pascal Ancey, Patrick Conti:
Monolithic above-IC resonator technology for integrated architectures in mobile and wireless communication. 7-16 - Behzad Razavi:
A 60-GHz CMOS receiver front-end. 17-22 - Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda:
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. 23-34 - Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, Shoji Otaka:
A 950-MHz rectifier circuit for sensor network tags with 10-m distance. 35-41 - Glenn E. R. Cowan, Robert C. Melville, Yannis P. Tsividis:
A VLSI analog computer/digital computer accelerator. 42-53 - Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. 54-62 - Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. 63-70 - Donghyun Kim, Kyusik Chung, Chang-Hyo Yu, Chun-Ho Kim, Inho Lee, Jaewan Bae, Young-Jun Kim, Jae-Hyeon Park, Sungbeen Kim, Yong-Ha Park, Nak Hee Seong, Jin-Aeon Lee, Jaehong Park, Stephen Oh, Seh-Woong Jeong, Lee-Sup Kim:
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. 71-84 - Andrea Lodi, Andrea Cappelli, Massimo Bocchi, Claudio Mucci, Massimilano Innocenti, Claudia De Bartolomeis, Luca Ciccarelli, Roberto Giansante, Antonio Deledda, Fabio Campi, Mario Toma, Roberto Guerrieri:
XiSystem: a XiRisc-based SoC with reconfigurable IO module. 85-96 - Andrew Cofler, Francois Druilhe, Denis Dutoit
, Michel Harrand:
A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM. 97-106 - Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. 107-112 - Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake:
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. 113-121 - Hyung-Rok Oh, Beak-Hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hye-Jin Kim, Ki-Sung Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim:
Enhanced write performance of a 64-mb phase-change random access memory. 122-126 - Kyu-Hyoun Kim
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. 127-134 - Takashi Ohsawa
Design of a 128-mb SOI DRAM using the floating body cell (FBC). 135-145 - Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. 146-151 - Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. 152-160 - Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Takumi Abe, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka, Teruhiko Kamei, Hiroaki Nasu, Chi-Ming Wang, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Tohru Maruyama, Susumu Yoshikawa, Masaaki Higashitani, Tuan D. Pham, Yupin Fong, Toshiharu Watanabe:
A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology. 161-169 - Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy:
PVT-aware leakage reduction for on-die caches with improved read stability. 170-178 - Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. 179-196 - Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz:
The implementation of a 2-core, multi-threaded itanium family processor. 197-209 - Jason M. Hart, Kyung T. Lee, Dennis Chen, Lik Cheng, Chipai Chou, Anand Dixit, Dale Greenley, Gregory Gruber, Kenneth Ho, Jesse Hsu, Naveen G. Malur, John Wu:
Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor. 210-217 - Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella:
A 90-nm variable frequency clock system for a power-managed itanium architecture processor. 218-228 - Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger:
Power and temperature control on a 90-nm Itanium family processor. 229-237 - Benton H. Calhoun, Anantha P. Chandrakasan:
Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering. 238-245 - Eric S. Fetzer, David M. Dahle, Casey Little, Kevin Safford:
The Parity protected, multithreaded register files on the 90-nm itanium microprocessor. 246-255 - Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar:
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. 256-264 - Li-min Lee, Daniel Weinlader, Chih-Kong Ken Yang:
A sub-10-ps multiphase sampling system using redundancy. 265-273 - Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jinhan Kim, Kicheol Bae, Jiheon Yu, Hoi-Jun Yoo, Joungho Kim:
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery. 274-286 - Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. 287-296 - Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed J. M. van Tuijl, Bram Nauta
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. 297-306
Volume 41, Number 2, February 2006
- Aida Varzaghani, Chih-Kong Ken Yang:
A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration. 310-319 - Jurgen Deveugele, Michiel S. J. Steyaert
A 10-bit 250-MS/s binary-weighted current-steering DAC. 320-329 - Nikolaus Klemmer, Emad Hegazi
A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets. 330-338 - Jesús Arias Álvarez, Peter Kiss, Vladimir I. Prodanov, Vito Boccuzzi, Mihai Banu, David Bisbal, Jacinto San Pablo, Luis Quintanilla, Juan Barbolla:
A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers. 339-351 - Haluk Külah
Noise analysis and characterization of a sigma-delta capacitive microaccelerometer. 352-361 - Jim Kulyk, James W. Haslett:
A monolithic CMOS 2368±30 MHz transformer based Q-enhanced series-C coupled resonator bandpass filter. 362-374 - Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida:
Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz. 375-383 - Pete Sivonen, Jussi Tervaluoto, Niko Mikkola, Aarno Pärssinen
A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-μm CMOS. 384-394 - Imtinan Elahi, Khurram Muhammad, Poras T. Balsara:
I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process. 395-404 - Curtis Leifso, John Nisbet:
A monolithic 6 GHz quadrature frequency doubler with adjustable phase offset. 405-412 - Elad Alon, Jaeha Kim, Sudhakar Pamarti
Replica compensated linear regulators for supply-regulated phase-locked loops. 413-424 - Jae-Youl Lee, Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, Hoi-Jun Yoo:
A regulated charge pump with small ripple voltage and fast start-up. 425-432 - Krishnakumar Sundaresan, Phillip E. Allen, Farrokh Ayazi:
Process and temperature compensation in a 7-MHz CMOS clock oscillator. 433-442 - Ethan Crain, Michael H. Perrott:
A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation. 443-451 - Hideki Kamitsuna, Yasuro Yamane, Masami Tokumitsu, Hirohiko Sugahara, Masahiro Muraguchi:
Low-power InP-HEMT switch ICs integrating miniaturized 2×2 switches for 10-Gb/s systems. 452-460 - Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling. 461-473 - Weize Xu, Eby G. Friedman:
On-chip test circuit for measuring substrate and line-to-line coupling noise. 474-482 - Guichang Zhong, Fan Xu, Alan N. Willson Jr.:
A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring. 483-495 - Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen:
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique. 496-506 - Sami Karvonen, Thomas A. D. Riley, Sami Kurtti, Juha Kostamovaara:
A quadrature charge-domain sampler with embedded FIR and IIR filtering functions. 507-515
Volume 41, Number 3, March 2006
- Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio:
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver. 530-539 - Giuseppe Gramegna, Philip G. Mattos, Marco Losi, Sabyasachi Das, Massimo Franciotta, Nino G. Bellantone, Michele Vaiana, Valentina Mandará, Mario Paparo:
A 56-mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm2 radio. 540-551 - Massimo Brandolini, Paolo Rossi, Davide Sanzogni, Francesco Svelto:
A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers. 552-559 - Jonathan P. Comeau, John D. Cressler:
A 28-GHz SiGe up-conversion mixer using a series-connected triplet for higher dynamic range and improved IF port return loss. 560-565 - Jri Lee:
A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology. 566-573 - Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. 574-587 - Sotir Ouzounov, Engel Roza
Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer. 588-596 - Mike Yun He, John Poulton:
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver. 597-606 - James F. Buckwalter, Ali Hajimiri
Analysis and equalization of data-dependent jitter. 607-620 - James F. Buckwalter, Ali Hajimiri
Cancellation of crosstalk-induced jitter. 621-632 - Seok-Woo Choi, Hyun-Bae Lee, Hong-June Park:
A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation. 633-641 - Yoshiaki Konno, Koji Tomioka, Yusuke Aiba, Katsuhiko Yamazoe, Bang-Sup Song:
A CMOS 1×-16× speed DVD write channel IC. 642-650 - Helmy Eltoukhy, Khaled N. Salama
A 0.18-μm CMOS bioluminescence detection lab-on-chip. 651-662 - Abhishek Bandyopadhyay, Jungwon Lee, Ryan W. Robucci, Paul E. Hasler:
MATIA: a programmable 80 WμW/frame CMOS block matrix transform imager architecture. 663-672 - Mladen Panovic, Andreas Demosthenous:
A low-power analog motion estimation processor for digital video coding. 673-683 - Mohammad M. Mansour, Naresh R. Shanbhag:
A 640-Mb/s 2048-bit programmable LDPC decoder chip. 684-698 - Matthew B. Leslie, R. Jacob Baker:
Noise-shaping sense amplifier for MRAM cross-point arrays. 699-704 - Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. 705-711 - Kostas Pagiamtzis
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. 712-727 - Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki:
A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme. 728-742
Volume 41, Number 4, April 2006
- Keng L. Wong, Tawfik Rahal-Arabi, Matthew Ma, Greg Taylor:
Enhancing microprocessor immunity to power supply noise with clock-data compensation. 749-758 - Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong:
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. 759-771 - Anup P. Jose, George Patounakis, Kenneth L. Shepard:
Pulsed current-mode signaling for nearly speed-of-light intrachip communication. 772-780 - David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. 781-792 - Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
A self-tuning DVS processor using delay-error detection and correction. 792-804 - Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara:
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. 805-814 - Yasuhisa Takeyama, Hiroyuki Otake, Osamu Hirabayashi, Keiichi Kushida, Nobuaki Otsuka:
A low leakage SRAM macro with replica cell biasing scheme. 815-822 - Kyomin Sohn, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo:
An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology. 823-830 - Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. 831-838 - Fa Foster Dai, Weining Ni, Yin Shi, Richard C. Jaeger:
A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC. 839-850 - Nana Akahane, Shigetoshi Sugawa, Satoru Adachi, Kazuya Mori, Toshiyuki Ishiuchi, Koichi Mizobuchi:
A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor. 851-858 - Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi
Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). 859-867 - Andrew Chang, David K. Su, Richard K. Hester, Bruce A. Wooley:
A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems. 868-875 - Sunyoung Kim, Jae-Youl Lee, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo:
An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip. 876-882 - Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito:
A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. 883-890 - Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda:
A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding. 891-898 - Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Namhoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS. 899-908 - Jonathan Sewter, Anthony Chan Carusone
A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s. 909-917 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit. 918-934
- Aida Varzaghani, Chih-Kong Ken Yang:
A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. 935-944 - Tae Wook Kim, Bonkee Kim:
A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications. 945-953 - Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. 954-965 - Scott E. Meninger, Michael H. Perrott:
A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise. 966-980 - Antonio Liscidini
A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. 981-989 - Jan H. Rutger Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta:
Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-μm CMOS. 990-999
Volume 41, Number 5, May 2006
- Jri Lee:
High-speed circuit designs for transmitters in broadband data links. 1004-1015 - Ruiyuan Zhang, George S. La Rue:
Fast acquisition clock and data recovery circuit with low jitter. 1016-1024 - Day-Uei Li, Chia-Ming Tsai:
10-Gb/s modulator drivers with local feedback networks. 1025-1030 - Ari Yakov Valero-López, Sung Tae Moon, Edgar Sánchez-Sinencio:
Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer. 1031-1041 - Jinho Jeong, Youngwoo Kwon:
A fully integrated V-band PLL MMIC using 0.15-μm GaAs pHEMT technology. 1042-1050 - Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu:
A 0.7-2-GHz self-calibrated multiphase delay-locked loop. 1051-1061 - Michiel De Wilde, Wim Meeus, Pieter Rombouts, Jan Van Campenhout
A simple on-chip repetitive sampling setup for the quantification of substrate noise. 1062-1072 - Jongchan Kang, Daekyu Yu, Youngoo Yang, Bumman Kim:
Highly linear 0.18-μm CMOS power amplifier with deep n-Well structure. 1073-1080 - Ju-Ho Sohn, Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ramchan Woo, Hoi-Jun Yoo:
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. 1081-1091 - Yasuhiko Sasaki, Naoki Kato, Hiroaki Nakaya:
Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications. 1092-1099 - Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. 1100-1107 - Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh:
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. 1108-1119 - Daniel L. Kaczman, Manish Shah, Nihal J. Godambe, Mohammed Alam, Homero N. Guimarães, Lu M. Han, Mohammed Rachedine, David L. Cashen, William E. Getka, Charles Dozier, Wayne P. Shepherd, Karl Couglar:
A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver. 1122-1132 - Alex W. Hietala:
A quad-band 8PSK/GMSK polar transceiver. 1133-1141 - Fatih Kocer
A new transponder architecture with on-chip ADC for long-range telemetry applications. 1142-1148 - Bertan Bakkaloglu
A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process. 1149-1159 - Chih-Ming Hung
A digitally controlled oscillator system for SAW-less transmitters in cellular handsets. 1160-1170 - Vladimir Aparin, Gary J. Ballantyne, Charles J. Persico, Alberto Cicalini:
An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends. 1171-1182 - Tak Shun Dickson Cheung, John R. Long:
Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits. 1183-1200 - Francis M. Rotella, Cristian Cismaru, Yevgeniy Gene Tkachenko, Yuhua Cheng, Peter J. Zampardi:
Characterization, design, modeling, and model validation of silicon-wafer M: N balun components under matched and unmatched conditions. 1201-1209 - Junxiong Deng, Prasad S. Gudem, Lawrence E. Larson, Donald F. Kimball, Peter M. Asbeck:
A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications. 1210-1221 - Andrea Mazzanti, Luca Larcher
Analysis of reliability and power efficiency in cascode class-E PAs. 1222-1229
Volume 41, Number 6, June 2006
- Alan W. L. Ng, Gerry C. T. Leung, Ka-Chun Kwok, Lincoln Lai Kan Leung, Howard C. Luong
A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process. 1236-1244 - Tai-Cheng Lee, Keng-Jan Hsiao:
The design and analysis of a DLL-based frequency synthesizer for UWB application. 1245-1252 - Tai-Cheng Lee, Yen-Chuan Huang:
The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application. 1253-1261 - You-Jen Wang, Shao-Ku Kao, Shen-Iuan Liu:
All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles. 1262-1274 - Pao-Lung Chen, Ching-Che Chung
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. 1275-1285 - Jussi-Pekka Jansson
A CMOS time-to-digital converter with better than 10 ps single-shot precision. 1286-1296 - Changhua Cao, Kenneth K. O:
Millimeter-wave voltage-controlled oscillators in 0.13-μm CMOS technology. 1297-1304 - Andrea Mazzanti, Pietro Andreani:
On the amplitude and phase errors of quadrature LC-tank CMOS oscillators. 1305-1313 - Jongchan Kang, Jehyung Yoon, Kyoungjoon Min, Daekyu Yu, Joongjin Nam, Youngoo Yang, Bumman Kim:
A highly linear and efficient differential CMOS power amplifier with harmonic control. 1314-1322 - Mostafa Elmala, Jeyanandh Paramesh, Krishnamurthy Soumyanath:
A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion. 1323-1332 - Frank Zhang, Peter R. Kinget
Low-power programmable gain CMOS distributed LNA. 1333-1343 - Mehmet Tamer Ozgun, Yannis P. Tsividis, Gangadhar Burra:
Dynamic power optimization of active filters with application to zero-IF receivers. 1344-1352 - Kong-Pang Pun, Wang Tung Cheng, Chiu-Sing Choy, Cheong-Fat Chan:
A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator. 1353-1363 - Barbara Baggini, Philipp Basedau, Rolf Becker, Peter Bode, Ralf Burdenski, Farzad Esfahani, Willem H. Groeneweg, Markus Helfenstein, Alexander Lampe, Roland Ryter, Ralph Stephan:
Baseband and audio mixed-signal front-end IC for GSM/EDGE applications. 1364-1379 - Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu:
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. 1380-1390 - James F. Buckwalter, Mounir Meghelli, Daniel J. Friedman, Ali Hajimiri
Phase and amplitude pre-emphasis techniques for low-power serial links. 1391-1399 - Saravanan Rajapandian, Kenneth L. Shepard, Peter Hazucha, Tanay Karnik:
High-voltage power delivery through charge recycling. 1400-1410 - Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez:
Piezoelectric micro-power generation interface circuits. 1411-1420 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris
An adaptive checker for the fully differential analog code. 1421-1429 - Timothy G. Constandinou
A micropower centroiding vision processor. 1430-1443 - Marcos Ferretti, Peter A. Beerel:
High performance asynchronous design using single-track full-buffer standard cells. 1444-1454 - Satoshi Inaba
Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology. 1455-1462 - Marija Blagojevic, Maher Kayal, Marc Pastre, Louis Harik, Michel J. Declercq, Serguei Okhonin, Pierre C. Fazan:
Capacitorless 1T DRAM sensing scheme with automatic reference generation. 1463-1470 - Hakho Lee
IC/microfluidic hybrid system for magnetic manipulation of biological cells. 1471-1480 - Jipeng Li, Un-Ku Moon, John A. McNeill
Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC". 1481
Volume 41, Number 7, July 2006
- Olivier Charlon, Matthias Locher, Hendrik Arend (Henk) Visser, David Duperray, Jennie Chen, Marc Judson, Alan L. Landesman, C. Hritz, Ulrich Kohlschuetter, Yifeng Zhang, C. Ramesh, Anton Daanen, Minzhan Gao, S. Haas, Vijay Maheshwari, Andreas Bury, Gunnar Nitsche, Artur Wrzyszcz, William Redman-White, Hamid Bonakdar, Rachid El Waffaoui, Mark Bracey:
A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications. 1503-1512 - Adil Koukab, Yu Lei, Michel J. Declercq:
A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system. 1513-1521 - Remco van de Beek, Domine M. W. Leenaerts, Gerard van der Weide:
A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer. 1522-1529 - Namsoo Kim, Vladimir Aparin, Kenneth Barnett, Charles J. Persico:
A cellular-band CDMA 0.25-μm CMOS LNA linearized using active post-distortion. 1530-1534 - Woonyun Kim, Sung-Gi Yang, Jinhyuck Yu, Heeseon Shin, Woo-Seung Choo, Byeong-Ha Park:
A direct conversion receiver with an IP2 calibrator for CDMA/PCS/GPS/AMPS applications. 1535-1541 - Jussi Ryynänen
WCDMA multicarrier receiver for base-station applications. 1542-1550 - Lydi Smaini, Carlo Tinella, Didier Hélal, Claude Stoecklin, Laurent Chabert, Christophe Devaucelle, Régis Cattenoz, Nils Rinaldi, Didier Belot:
Single-chip CMOS pulse generator for UWB systems. 1551-1561 - Vincent Quiquempoix, Philippe Deval, Alexandre Barreto, Gabriele Bellini, János Márkus, José B. Silva, Gabor C. Temes:
A low-power 22-bit incremental ADC. 1562-1571 - Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers:
A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications. 1572-1577 - Trevor C. Caldwell, David A. Johns:
A time-interleaved continuous-time ΔΣ modulator with 20-MHz signal bandwidth. 1578-1588 - Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. 1589-1595 - Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Seung-Hoon Lee:
A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration. 1596-1605 - Carolien Hermans, Michiel S. J. Steyaert
A high-speed 850-nm optical receiver front-end in 0.18-μm CMOS. 1606-1614 - Roger Steadman, Gereon Vogtmeier, Armin Kemna, Salah Eddine Ibnou Quossai, Bedrich J. Hosticka:
A high dynamic range current-mode amplifier for computed tomography. 1615-1619 - Flavio Heer, Sadik Hafizovic, Wendy Franks, Axel W. Blau
CMOS microelectrode array for bidirectional interaction with neuronal networks. 1620-1629 - Stefano D'Amico
A 4th-order active-Gm-RC reconfigurable (UMTS/WLAN) filter. 1630-1637 - Ovidiu Vermesan, Lars-Cyril Julin Blystad, Roy Bahr, Magnus Hjelstuen, Lionel Beneteau, Benoit Froelich:
A mixed-signal BiCMOS front-end signal processor for high-temperature applications. 1638-1647 - Rolf Becker, Willem H. Groeneweg:
An audio amplifier providing up to 1 Watt in standard digital 90-nm CMOS. 1648-1653 - Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel:
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead. 1654-1661 - Andrea Lodi, Luca Ciccarelli, Roberto Guerrieri:
Low leakage techniques for FPGAs. 1662-1672 - Benton H. Calhoun, Anantha P. Chandrakasan:
Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. 1673-1679
Volume 41, Number 8, August 2006
- Lowell H. Miles, Jody W. Gambles, Gary K. Maki, William E. Ryan, Sterling R. Whitaker:
An 860-Mb/s (8158, 7136) Low-Density Parity-Check Encoder. 1686-1691 - James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen:
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. 1692-1706 - Aurangzeb Khan, Philip Watson, George Kuo, Due Le, Trung-Kien Nguyen, Steven Yang, Peter Bennett, Pokai Huang, Jaspal Gill, Chris Hawkins, John Goodenough, Demin Wang, Irfan Ahmed, Peter Tran, Helder Mak, Oanh Kim, Frank Martin, Yimu Fan, David Ge, Joseph Kung, Vincent Shek:
A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor. 1707-1717 - John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, John M. Cotte:
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. 1718-1725 - Jonathan Roderick, Harish Krishnaswamy, Kenneth Newton, Hossein Hashemi
Silicon-Based Ultra-Wideband Beam-Forming. 1726-1739 - Yuen-Hui Chee, Ali M. Niknejad, Jan M. Rabaey:
An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks. 1740-1748 - Abbas Komijani, Ali Hajimiri
A Wideband 77-GHz, 17.5-dBm Fully Integrated Power Amplifier in Silicon. 1749-1756 - Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath:
A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. 1757-1763 - Giuseppe Cusmai, Massimo Brandolini, Paolo Rossi, Francesco Svelto:
A 0.18-$muhbox m$CMOS Selective Receiver Front-End for UWB Applications. 1764-1771 - Khurram Muhammad, Yo-Chuol Ho, Terry Mayhugh Jr., Chih-Ming Hung
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process. 1772-1783 - Fred S. Lee, Anantha P. Chandrakasan:
A BiCMOS Ultra-Wideband 3.1-10.6-GHz Front-End. 1784-1791 - Babak Soltanian, Peter R. Kinget
Tail Current-Shaping to Improve Phase Noise in LC Voltage-Controlled Oscillators. 1792-1802 - Assad A. Abidi:
Phase Noise and Jitter in CMOS Ring Oscillators. 1803-1816 - Hai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton:
Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs. 1817-1829 - Timothy O. Dickson, Kenneth H. K. Yau, Theodoros Chalvatzis, Alain M. Mangan, Ekaterina Laskin, Rudy Beerkens, Paul Westergaard, Mihai Tazlauanu, Ming-Ta Yang, Sorin P. Voinigescu:
The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks. 1830-1845 - Ahmed M. A. Ali
A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter. 1846-1855 - Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan:
A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs. 1856-1866 - Jeff L. Sonntag, John T. Stonick:
A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links. 1867-1875 - Jinghong Chen, Fadi Saibi
A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication. 1876-1893 - Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Michael J. Gilsdorf:
A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. 1894-1907 - Xiaofeng Lin, Jin Liu, Hoi Lee, Hao Liu:
A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS. 1908-1918 - Jonathan Sewter, Anthony Chan Carusone
A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS. 1919-1929 - John W. Fattaruso, Benjamin Sheahan:
A 3-V 4.25-Gb/s Laser Driver with 0.4-V Output Voltage Compliance. 1930-1937 - Devrim Yilmaz Aksin
Switch Bootstrapping for Precise Sampling Beyond Supply Voltage. 1938-1943 - B. Robert Gregoire:
A Compact Switched-Capacitor Regulated Charge Pump Power Supply. 1944-1953
Volume 41, Number 9, September 2006
- Venkata Srinivas, Shanthi Pavan, Ashish Lachhwani, Naga Sasidhar:
A Distortion Compensating Flash Analog-to-Digital Conversion Technique. 1959-1969 - Nicola Ghittori, Andrea Vigna, Piero Malcovati
1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters. 1970-1982 - Michael W. Baker, Rahul Sarpeshkar:
Low-Power Single-Loop and Dual-Loop AGCs for Bionic Ears. 1983-1996 - Athanasios Vasilopoulos, Georgios Vitzilaios, Gerasimos Theodoratos, Yannis Papananos:
A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR. 1997-2008 - Alfredo Arnaud
Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors. 2009-2018 - Ganesh K. Balachandran, Raymond E. Barnett:
A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems. 2019-2028 - Bogdan Georgescu, Ivars G. Finvers, Fadhel M. Ghannouchi:
2 GHz$rm Q$-Enhanced Active Filter With Low Passband Distortion and High Dynamic Range. 2029-2039 - Charlotte Soens, Geert Van der Plas
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. 2040-2051 - Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa:
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. 2052-2057 - Jri Lee:
A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology. 2058-2066 - Ullas Singh, Lijun Li, Michael M. Green:
A 34 Gb/s Distributed 2: 1 MUX and CMU Using 0.18$muhbox m$CMOS. 2067-2076 - Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim:
A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. 2077-2082 - Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle:
Distributed Differential Oscillators for Global Clock Networks. 2083-2094 - Graeme Storm, Robert K. Henderson, J. E. D. Hurwitz, David Renshaw, Keith Findlater, Matthew Purcell:
Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor. 2095-2106 - Abhishek Bandyopadhyay, Guillermo J. Serrano
Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades. 2107-2114 - Hyouk-Kyu Cha, Ilhyun Yun, Jinbong Kim, Byeong-Cheol So, Kanghyup Chun, Ilku Nam, Kwyro Lee:
A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller. 2115-2124 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A 12.5 Gb/s Electro-Absorption-Modulator Driver Using an Adaptive Compensated Push-Pull Emitter Follower and a Cascode Output Switch With Dynamic Headroom Allocation. 2127-2143
- Scott Bardsley, Christopher Dillon, Ravi Kummaraguntla, Charles Lane, Ahmed M. A. Ali
A 100-dB SFDR 80-MSPS 14-Bit 0.35-$ muhbox m$BiCMOS Pipeline ADC. 2144-2153 - Daniel Kucharski, Kevin T. Kornegay
2.5 V 43-45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family. 2154-2165 - W. C. Edmund Neo, Yu Lin, Xiaodong Liu, Leo C. N. de Vreede, Lawrence E. Larson, Marco Spirito
Adaptive Multi-Band Multi-Mode Power Amplifier Using Integrated Varactor-Based Tunable Matching Networks. 2166-2176 - Su-Tarn Lim, John R. Long:
A Low-Voltage Broadband Feedforward-Linearized BJT Mixer. 2177-2187 - Tao Zhang, William R. Eisenstadt
Bipolar Microwave RMS Power Detectors. 2188-2192
Volume 41, Number 10, October 2006
- Ekaterina Laskin, Sorin P. Voinigescu:
A 60 mW per Lane, 4$, times, $23-Gb/s 2$ ^7 -$1 PRBS Generator. 2198-2208 - Joakim Hallin, Torgil Kjellberg, Thomas Swahn:
A 165-Gb/s 4: 1 Multiplexer in InP DHBT Technology. 2209-2214 - Robert E. Makon, Rachid Driad, Karl Schneider, Manfred Ludwig, Rolf Aidam, Rüdiger Quay
InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s. 2215-2223 - Adesh Garg, Anthony Chan Carusone
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology. 2224-2232 - Shahriar Shahramian, Anthony Chan Carusone
Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. 2233-2240 - Michael V. Aust, Arvind K. Sharma, Owen Fordham, Ronald Grundbacher, Richard To, Roger S. Tsai, Richard Lai:
A 2.8-W Q-Band High-Efficiency Power Amplifier. 2241-2247 - Kim B. Östman
Novel VCO Architecture Using Series Above-IC FBAR and Parallel LC Resonance. 2248-2256 - Mingquan Bao, Harald Jacobsson, Lars Aspemyr, Geert Carchon, Xiao Sun:
A 9-31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology. 2257-2264 - Frank Zhang, Peter R. Kinget
Design of Components and Circuits Underneath Integrated Inductors. 2265-2271 - Fengyi (Fred) Huang, Jingxue Lu, Nan Jiang, Xiaowen Zhang, Wengang Wu, Yangyuan Wang:
Frequency-Independent Asymmetric Double-$pi $Equivalent Circuit for On-Chip Spiral Inductors: Physics-Based Modeling and Parameter Extraction. 2272-2283 - Steven Eugene Turner, David E. Kotecki
Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology. 2284-2290 - Okjune Jeon, Robert M. Fox, Brent A. Myers:
Analog AGC Circuitry for a CMOS WLAN Receiver. 2291-2300 - Alberto Valdes-Garcia, Faisal Abdel-Latif Hussien, José Silva-Martínez, Edgar Sánchez-Sinencio:
An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing. 2301-2313 - Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Atila Alvandpour:
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization. 2314-2323 - Ming-Dou Ker, Shih-Lun Chen:
Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique. 2324-2333 - Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez:
Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. 2334-2343 - Jinhui Chen, Lawrence T. Clark, Tai-Hua Chen:
An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage. 2344-2353 - Jung-Hoon Chun, Boris Murmann
Analysis and Measurement of Signal Distortion due to ESD Protection Circuits. 2354-2358 - Derek K. Shaeffer, Thomas H. Lee:
Comment on Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier". 2359 - Francisco J. García-Sánchez
Comments on "A sinh Resistor and Its Application to tanh Linearization". 2359 - Maziar Tavakoli, Rahul Sarpeshkar:
Reply to Comments on "A sinh Resistor and Its Application to tanh Linearization". 2359-2360
Volume 41, Number 11, November 2006
- Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. 2366-2372 - Hyejung Kim, Byeong-Gyu Nam
A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System. 2373-2381 - Kohei Onizuka, Hiroshi Kawaguchi
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. 2382-2389 - Xiang Xie, Guolin Li, Xinkai Chen, Xiaowen Li, Zhihua Wang:
A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule. 2390-2400 - Che-Fu Liang, Shih-Tsai Liu, Shen-Iuan Liu:
A Calibrated Pulse Generator for Impulse-Radio UWB Applications. 2401-2407 - Kyoohyun Lim, Sang-Hoon Lee, Sunki Min, Sungmin Ock, Myung-woon Hwang, ChangHee Lee, Kyung-Lok Kim, Sangwoo Han:
A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications. 2408-2416 - Mutsuo Daito, Hirofumi Matsui, Masaya Ueda, Kunihiko Iizuka:
A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration. 2417-2423 - Sudip Shekhar, Jeffrey S. Walling
Bandwidth Extension Techniques for CMOS Amplifiers. 2424-2439 - Hervé F. Achigui
1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results. 2440-2448 - Stanley B. T. Wang, Ali M. Niknejad, Robert W. Brodersen:
Design of a Sub-mW 960-MHz UWB CMOS LNA. 2449-2456 - Luca Romanò, Andrea Bonfanti
5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS. 2457-2467 - Tzung-Han Wu, Chinchun Meng:
5.2/5.7-GHz 48-dB Image Rejection GaInP/GaAs HBT Weaver Down-Converter Using LO Frequency Quadrupler. 2468-2480 - Tadashi Maeda, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Hikaru Hida:
A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver. 2481-2490 - Ivan Chee Hong Lai, Minoru Fujishima
A New On-Chip Substrate-Coupled Inductor Model Implemented With Scalable Expressions. 2491-2499 - Yu-Che Yang, Shih-An Yu, Yu-Hsuan Liu, Tao Wang, Shey-Shi Lu
A Quantization Noise Suppression Technique for$DeltaSigma$Fractional-$N$Frequency Synthesizers. 2500-2511 - Yee William Li, Kenneth L. Shepard, Yannis P. Tsividis:
A Continuous-Time Programmable Digital FIR Filter. 2512-2520 - George Patounakis, Kenneth L. Shepard, Rastislav Levicky:
Active CMOS Array Sensor for Time-Resolved Fluorescence Detection. 2521-2530 - Saied Hemati, Amir H. Banihashemi, Calvin Plett:
A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32, 8) Low-Density Parity-Check (LDPC) Code. 2531-2540 - Hyeon-Min Bae, Jonathan B. Ashbrook, Jinki Park, Naresh R. Shanbhag, Andrew C. Singer
An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links. 2541-2554 - Hitoyuki Tagami, Seiji Kozaki, Kenichi Nakura, Shigeki Kohama, Masamichi Nogami, Kuniaki Motoshima:
A Burst-Mode Bit-Synchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON. 2555-2565 - Sangjin Byun
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector. 2566-2576 - Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene:
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies. 2577-2588 - Taku Ogura, Masahiro Hosoda, Tomoya Ogawa, Tamiyu Kato, Akihiko Kanda, Tomoyuki Fujisawa, Satoshi Shimizu, Masafumi Katsumata:
A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function. 2589-2600 - Ming-Dou Ker, Jia-Huei Chen:
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices. 2601-2609
Volume 41, Number 12, December 2006
- Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Donald Paterson, Steven Rose, Iuri Mehr, Qui Luu:
A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz. 2632-2640 - Gerhard Mitteregger, Christian Ebner, Stephan Mechnig, Thomas Blon, Christophe Holuigue, Ernesto Romani:
A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB. 2641-2649 - Sandeep K. Gupta, Michael A. Inerfield, Jingbo Wang:
A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture. 2650-2657 - John Kenneth Fiorenza, Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee:
Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies. 2658-2668 - Shuo-Wei Michael Chen, Robert W. Brodersen:
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS. 2669-2680 - Rameswor Shrestha, Eric A. M. Klumperink, Eisse Mensink, Gerard J. M. Wienk, Bram Nauta
A Polyphase Multipath Technique for Software-Defined Radio Transmitters. 2681-2692 - Supisa Lerstaveesin, Bang-Sup Song:
A Complex Image Rejection Circuit With Sign Detection Only. 2693-2702 - Pietro Andreani, Ali Fard:
More on the$1/{\rm f}^{2}$Phase Noise Performance of CMOS Differential-PairLC-Tank Oscillators. 2703-2712 - Stefano D'Amico
A 4.1-mW 10-MHz Fourth-Order Source-Follower-Based Continuous-Time Filter With 79-dB DR. 2713-2719 - Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. 2720-2728 - Rod Burt, Joy Zhang:
A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path. 2729-2736 - William W. Si, Srenik S. Mehta, Hirad Samavati, Manolis Terrovitis, Michael P. Mack, Keith Onodera, Steve H. Jen, Susan Luschas, Justin A. Hwang, Suni Mendis, David K. Su, Bruce A. Wooley:
A 1.9-GHz Single-Chip CMOS PHS Cellphone. 2737-2745 - Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Nati Dinur, Stewart S. Taylor, Krishnamurthy Soumyanath:
A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS. 2746-2756 - Ben W. Cook, Axel D. Berny, Alyosha C. Molnar, Steven Lanzisera, Kristofer S. J. Pister:
Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply. 2757-2766 - Wolfram Kluge, Frank Poegel, Hendrik Roller, Matthias Lange, Tilo Ferchland, Lutz Dathe, Dietmar Eggert:
A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications. 2767-2775 - Steve Lo, Isaac Sever, Ssu-Pin Ma, Peter Jang, Albert Zou, Chris Arnott, Kalyan Ghatak, Adam Schwartz, Lam Huynh, Ven Tim Phan, Thai Nguyen:
A Dual-Antenna Phased-Array UWB Transceiver in 0.18-$\mu{\hbox {m}}$ CMOS. 2776-2786 - Christoph Sandner, Sven Derksen, Dieter Draxelmayr, Staffan Ek, Voicu Filimon, Graham Leach, Stefano Marsili, Denis Matveev, Koen L. R. Mertens, Florian Michl, Hermann Paule, Manfred Punzenberger, Christian Reindl, Raffaele Salerno, Marc Tiebout, Andreas Wiesbauer, Ian Winter, Zisan Zhang:
A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB. 2787-2794 - Aydin Babakhani, Xiang Guan, Abbas Komijani, Arun Natarajan, Ali Hajimiri
A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas. 2795-2806 - Arun Natarajan, Abbas Komijani, Xiang Guan, Aydin Babakhani, Ali Hajimiri
A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase Shifting. 2807-2819 - Scott K. Reynolds, Brian A. Floyd
A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications. 2820-2831 - Antonio Liscidini
Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. 2832-2841 - Manoj Gupta, Bang-Sup Song:
A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration. 2842-2851 - Naratip Wongkomet, Luns Tee, Paul R. Gray:
A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications. 2852-2859 - Rahim Bagheri, Ahmad Mirzaei, Saeed Chehrazi, Mohammad E. Heidari, Minjae Lee, Mohyee Mikhemar, Wai K. Tang, Asad A. Abidi:
An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS. 2860-2876 - Eduard Säckinger, Aner Tennen, Dima Shulman, Barkat Wani, Marta Rambaud, Drahoslav Lím, Fred Larsen, George S. Moschytz:
A 5-V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction. 2877-2884 - John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. 2885-2900 - John G. Kenney, Declan Dalton, Eric Evans, Murat Hayri Eskiyerli, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Lawrence DeVito:
A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS. 2901-2910 - Koichi Nose, Mikihiro Kajita, Masayuki Mizuno:
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. 2911-2920 - Christian Kromer, Gion Sialm, Christian Menolfi, Martin L. Schmatz, Frank Ellinger, Heinz Jäckel:
A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects. 2921-2929 - Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore:
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. 2930-2944 - Behnam Analui, Drew Guckenberger, Daniel Kucharski, Adithyaram Narasimha:
A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13- $\mu{\hbox {m}}$ CMOS SOI Technology. 2945-2955 - Claudio Stagni, Carlotta Guiducci, Luca Benini
CMOS DNA Sensor Array With Integrated A/D Conversion Based on Label-Free Capacitance Measurement. 2956-2964 - Pamela T. Bhatti, Kensall D. Wise:
A 32-Site 4-Channel High-Density Electrode Array for a Cochlear Prosthesis. 2965-2973 - Jong-Hak Baek, Myunghee Lee, Jaehoon Lee, Han Su Pae, Chang-Ju Lee, Jin Tae Kim, ChangSik Choi, Hong Kwon Kim, Tae Jin Kim, Ho Kyoon Chung:
A Current-Mode Display Driver IC Using Sample-and-Hold Scheme for QVGA Full-Color AMOLED Displays. 2974-2982 - Babak Vakili-Amini, Reza Abdolvand, Farrokh Ayazi:
A 4.5-mW Closed-Loop $\Delta\Sigma$ Micro-Gravity CMOS SOI Accelerometer. 2983-2991 - Kofi A. A. Makinwa, Martijn F. Snoeij:
A CMOS Temperature-to-Frequency Converter With an Inaccuracy of Less Than$\pm \hbox{0.5}\, ^{\circ}{\hbox{C}}$(3$\sigma$) From$-\hbox{40}\, ^{\circ}\hbox{C}$to 105$\, ^{\circ}\hbox{C}$. 2992-2997 - Satoshi Yoshihara, Yoshikazu Nitta, Masaru Kikuchi, Ken Koseki, Yoshiharu Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano, Hiromi Kuriyama, Junichi Inutsuka, Akari Tajima, Tadashi Nakajima, Yoshiharu Kudoh, Fumihiko Koga, Yasuo Kasagi, Shinya Watanabe, Tetsuo Nomoto:
A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change. 2998-3006 - Martijn F. Snoeij, Albert J. P. Theuwissen, Kofi A. A. Makinwa, Johan H. Huijsing:
A CMOS Imager With Column-Level ADC Using Dynamic Column Fixed-Pattern Noise Reduction. 3007-3015
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