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IEEE Journal of Solid-State Circuits, Volume 42
Volume 42, Number 1, January 2007
- James D. Warnock, William Bidermann, Albert van der Werf, Katsuyuki Sato:
Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference. 3-6 - Ana Sonia Leon, Kenway W. Tam, Jinuk Luke Shin, David Weisner, Francis Schumacher:
A Power-Efficient High-Throughput 32-Thread SPARC Processor. 7-16 - Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. 17-25 - Sapumal B. Wijeratne, Nanda Siddaiah, Sanu K. Mathew, Mark A. Anders, Ram K. Krishnamurthy, Jeremy Anderson, Matthew Ernest, Mark D. Nardin:
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit. 26-37 - Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou:
Energy-Efficient GHz-Class Charge-Recovery Logic. 38-47 - Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A Leakage Current Replica Keeper for Dynamic Circuits. 48-55 - Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil:
Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements. 56-65 - Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner
, Saravanan Rajapandian, Tanay Karnik:
High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. 66-73 - Yusuke Kanno, Hiroyuki Mizuno
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. 74-83 - Eugenio Cantatore, Thomas C. T. Geuns, Gerwin H. Gelinck, Erik van Veenendaal, Arnold F. A. Gruijthuijsen, Laurens Schrijnemakers, Steffen Drews, Dago M. De Leeuw:
A 13.56-MHz RFID System Based on Organic Transponders. 84-92 - Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display. 93-100 - Hiroyuki Nakamoto, Daisuke Yamazaki, Takuji Yamamoto, Hajime Kurata, Satoshi Yamada, Kenji Mukaida, Tsuzumi Ninomiya, Takashi Ohkawa, Shoichi Masui, Kunihiko Gotoh:
A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology. 101-110 - Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. 111-122 - Reid R. Harrison, Paul T. Watkins, Ryan J. Kier, Robert O. Lovejoy, Daniel J. Black, Bradley Greger
A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System. 123-133 - Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer:
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. 134-144 - Simon Damphousse, Khalid Ouici, Ahmed Rizki, A. Martin Mallinson:
All Digital Spread Spectrum Clock Generator for EMI Reduction. 145-150 - Davide De Caro
A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS. 151-160 - Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Jiun-Yan Yang, Kang-Cheng Hou, Chen-Yi Lee:
A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications. 161-169 - Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. 170-182 - Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu:
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. 183-192 - Kyu-Hyoun Kim
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. 193-200 - Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. 201-209 - Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, KwangJin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Choong-Duk Ha, Ki-Sung Kim, Young-Ran Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim, YunSueng Shin:
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. 210-218 - Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima:
A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. 219-232 - Muhammad M. Khellah
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. 233-242
Volume 42, Number 2, February 2007
- Brian P. Ginsburg
Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver. 247-257 - Ding-Lan Shen, Tai-Cheng Lee:
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers. 258-268 - Bharath Kumar Thandri, José Silva-Martínez:
A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-µm SiGe BiCMOS Technology. 269-279 - Srinivasan Venkatesh, Guillermo J. Serrano
A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation. 280-291 - Jianhong Xiao, Iuri Mehr, José Silva-Martínez:
A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner. 292-301 - Sam Mandegaran, Ali Hajimiri
A Breakdown Voltage Multiplier for High Voltage Swing Drivers. 302-312 - Aleksandar Tasic, Su-Tarn Lim, Wouter A. Serdijn, John R. Long:
Design of Adaptive Multimode RF Front-End Circuits. 313-322 - Ahmed Amer, Emad Hegazi
A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation. 323-328 - Chih-Fan Liao, Shen-Iuan Liu:
A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers. 329-339 - Tsung-Hsien Lin
An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL. 340-349 - Antonio Giuseppe Maria Strollo
A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique. 350-360 - Rong-Jyi Yang, Shen-Iuan Liu:
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm. 361-373 - Ali Fard, Pietro Andreani:
An Analysis of 1/f2 Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators). 374-384 - Michael S. McCorquodale, Justin D. O'Day, Scott M. Pernia, Gordon A. Carichner, Sundus Kubba, Richard B. Brown:
A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0. 385-399 - Nathaniel J. Guilar, Frank Lau, Paul J. Hurst, Stephen H. Lewis:
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer. 400-409 - Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. 410-421 - Toshihiko Yamasaki, Tadashi Shibata:
A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection. 422-430 - Young-Ho Seo, Dong-Wook Kim:
VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000. 431-440 - Urs Frey
A Digital CMOS Architecture for a Micro-Hotplate Array. 441-450 - Sanjeev Manandhar, Steven Eugene Turner, David E. Kotecki
36-GHz, 16×6-Bit ROM in InP DHBT Technology Suitable for DDS Application. 451-456 - P. V. Ananda Mohan:
Comments on "A 4th-Order Active- Gm-RC Reconfigurable (UMTS/WLAN) Filter". 457-458 - Stefano D'Amico
Author's Reply. 458
Volume 42, Number 3, March 2007
- Sourja Ray, Bang-Sup Song:
A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching. 463-474 - Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania:
A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse. 475-485 - Dongwon Seo, Gene H. McAllister:
A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter. 486-495 - Kong-Pang Pun, Shouri Chatterjee
A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC. 496-507 - Juan M. Carrillo
1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage. 508-517 - Marco Grassi
A 160 dB Equivalent Dynamic Range Auto-Scaling Interface for Resistive Gas Sensors Arrays. 518-528 - Hakan Dogan, Robert G. Meyer:
Intermodulation Distortion in CMOS Attenuators and Switches. 529-539 - Arnoud P. van der Wel, Eric A. M. Klumperink, Jay S. Kolhatkar, Eric Hoekstra, Martijn F. Snoeij, Cora Salm
Low-Frequency Noise Phenomena in Switched MOSFETs. 540-550 - Patrick Reynaert
A 2.45-GHz 0.13-µm CMOS PA With Parallel Amplification. 551-562 - Qiang Li
CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency. 563-570 - Ankush Goel, Hossein Hashemi
Frequency Switching in Dual-Resonance Oscillators. 571-582 - Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin Ilker Karsilayan
A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz. 583-591 - Mahim Ranjan, Lawrence E. Larson:
A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems. 592-601 - Valentina Della Torre, Matteo Conta, Ramesh Chokkalingam, Giuseppe Cusmai, Paolo Rossi, Francesco Svelto:
A 20 mW 3.24mm2 Fully Integrated GPS Radio for Location Based Services. 602-612 - Niksa Tadic, Horst Zimmermann
Low-Power BiCMOS Optical Receiver With Voltage-Controlled Transimpedance. 613-626 - Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. 627-636 - Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology. 637-646 - Nicola Massari
A 100 dB Dynamic-Range CMOS Vision Sensor With Programmable Image Processing and Global Feature Extraction. 647-657 - Sai Kit Lau, Philip K. T. Mok
A Low-Dropout Regulator for SoC With Q-Reduction. 658-664 - H. Pooya Forghani-zadeh, Gabriel A. Rincón-Mora:
An Accurate, Continuous, and Lossless Self-Learning CMOS Current-Sensing Scheme for Inductor-Based DC-DC Converters. 665-679 - Benton H. Calhoun, Anantha P. Chandrakasan:
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation. 680-688 - David Levacq, Vincent Dessard, Denis Flandre
Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode. 689-702
Volume 42, Number 4, April 2007
- Krishnaswamy Nagaraj:
New Associate Editor. 719 - Stephen V. Kosonocky, Kazuo Yano:
Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits. 720-721 - Shouri Chatterjee
A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR. 722-729 - Patrick Y. Wu, Vincent Sin-Luen Cheung, Howard C. Luong
A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture. 730-738 - Brian P. Ginsburg
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC. 739-747 - Echere Iroaga, Boris Murmann
A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling. 748-756 - Kazutaka Honda, Masanori Furuta, Shoji Kawahito:
A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques. 757-765 - Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito:
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters. 766-774 - Ting Wu, Kartikeya Mayaram, Un-Ku Moon:
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. 775-783 - Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. 784-789 - Yuichi Hori, Tadahiro Kuroda:
A 0.79-mm2 29-mW Real-Time Face Detection Core. 790-797 - Ken Ueno, Tetsuya Hirose, Tetsuya Asai
CMOS Smart Sensor for Monitoring the Quality of Perishables. 798-803 - Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto:
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. 804-812 - Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler:
An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. 813-819 - Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. 820-829 - Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo
MRAM Cell Technology for Over 500-MHz SoC. 830-838 - Stefan Dietrich, Michael Angerbauer, Milena Ivanov, Dietmar Gogl, Heinz Hoenigschmid, Michael Kund, Corvin Liaw, Michael Markert, Ralf Symanczyk, Laith Altimime, Serge Bournat, Gerhard Müller:
A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control. 839-845 - Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava:
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. 846-852 - Fukashi Morishita
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. 853-861 - Kunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno:
A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor. 862-871 - Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori:
A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS. 872-880 - Jackie Koon Lun Wong, Alexander V. Rylyakov, Chih-Kong Ken Yang:
A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. 881-888 - Azita Emami-Neyestanak
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. 889-896 - Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, Philip John Crawley, James T. Kao, Zhiwei Dong, Madhu Chennam, Tim Nutt, David S. Trager, Mitchell Reid:
A Fully Integrated 0.13 µm CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration. 897-921 - Dejan Markovic, Borivoje Nikolic
Power and Area Minimization for Multidimensional Signal Processing. 922-934 - Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio:
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication. 935-948
Volume 42, Number 5, May 2007
- Krishnaswamy Nagaraj:
New Associate Editor. 951 - Derek K. Shaeffer:
Introduction to the Special Issue on the 2006 Radio Frequency Integrated Circuits (RFIC) Symposium. 952-953 - Asad A. Abidi:
The Path to the Software-Defined Radio Receiver. 954-966 - Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, Philip John Crawley, James T. Kao, Zhiwei Dong, Madhu Chennam, Tim Nutt, David S. Trager:
A Fully Integrated 0.13-µm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. 967-982 - Tzung-Ming Chen, Yung-Ming Chiu, Chun-Cheng Wang, Ka-Un Chan, Ying-Hsi Lin, Ming-Chong Huang, Chao-Hua Lu, Wen-Shan Wang, Che-Sheng Hu, Chao-Cheng Lee, Jiun-Zen Huang, Bin-I Chang, Shih-Chieh Yen, Ying-Yao Lin:
A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA. 983-991 - Khurram Muhammad, Thomas Murphy, Robert Bogdan Staszewski
Verification of Digital RF Processors: RF, Analog, Baseband, and Software. 992-1002 - Denis C. Daly, Anantha P. Chandrakasan:
An Energy-Efficient OOK Transceiver for Wireless Sensor Networks. 1003-1011 - Taeksang Song, Hyoung-Seok Oh, Euisik Yoon, Songcheol Hong:
A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network. 1012-1022 - Michael Reiha, John R. Long:
A 1.2 V Reactive-Feedback 3.1-10.6 GHz Low-Noise Amplifier in 0.13 µm CMOS. 1023-1033 - Saman Asgaran, M. Jamal Deen
Analytical Determination of MOSFET's High-Frequency Noise Parameters From NF50 Measurements and Its Application in RFIC Design. 1034-1043 - Terry Yao, Michael Q. Gordon, Keith K. W. Tang, Kenneth H. K. Yau, Ming-Ta Yang, Peter Schvan, Sorin P. Voinigescu:
Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio. 1044-1057 - Swaminathan Sankaran, Kenneth K. O:
A Ultra-Wideband Amplitude Modulation (AM) Detector Using Schottky Barrier Diodes Fabricated in Foundry CMOS Technology. 1058-1064 - Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, Sorin P. Voinigescu:
A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz for Direct Sampling Receivers. 1065-1075 - Paulo G. R. Silva, Lucien J. Breems, Kofi A. A. Makinwa, Raf Roovers, Johan H. Huijsing:
An IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range. 1076-1089 - Atsushi Yoshizawa, Yannis P. Tsividis:
A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation. 1090-1099 - Refet Firat Yazicioglu, Patrick Merken, Robert Puers
A 60 µW 60 nV/√Hz Readout Front-End for Portable Biopotential Acquisition Systems. 1100-1110 - Huei-Yan Huang, Jun-Chau Chien, Liang-Hung Lu:
A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback. 1111-1120 - Karan S. Bhatia, Sami Hyvonen, Elyse Rosenbaum:
A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications. 1121-1130 - Jintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang:
A Large-Swing Transformer-Boosted Serial Link Transmitter With > VDD Swing. 1131-1142 - Sten E. Gunnarsson, Camilla Kärnfelt
60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication. 1143-1157 - Ming-Dou Ker, Shih-Hung Chen:
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology. 1158-1168 - Shantanu Chakrabartty, Gert Cauwenberghs
Sub-Microwatt Analog VLSI Trainable Pattern Classifier. 1169-1179 - Chiu-Chiao Chung, Hongchin Lin
A Multilevel Read and Verifying Scheme for Bi-NAND Flash Memories. 1180-1188
Volume 42, Number 6, June 2007
- Krishnaswamy Nagaraj:
New Associate Editor. 1195 - Naveen Verma, Anantha P. Chandrakasan:
An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes. 1196-1205 - Kye-Shin Lee, Sunwoo Kwon, Franco Maloberti:
A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications. 1206-1215 - Hoi Lee, Philip K. T. Mok
An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp. 1216-1229 - Ping-Chen Huang, Ming-Da Tsai, George D. Vendelin, Huei Wang, Chun-Hung Chen, Chih-Sheng Chang:
A Low-Power 114-GHz Push-Push CMOS VCO Using LC Source Degeneration. 1230-1239 - Yanping Ding, Kenneth K. O:
A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS. 1240-1249 - Hui Zheng, Howard C. Luong
A 1.5 V 3.1 GHz-8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers. 1250-1260 - Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology. 1261-1270 - Feipeng Wang, Donald F. Kimball, Donald Y. C. Lie, Peter M. Asbeck, Lawrence E. Larson:
A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier. 1271-1281 - Kazuya Yamamoto, Takao Moriwaki, Hiroyuki Otsuka, Nobuyuki Ogawa, Kosei Maemura, Teruyuki Shimura:
A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V. 1282-1290 - Hamid Rafati, Behzad Razavi:
A Receiver Architecture for Dual-Antenna Systems. 1291-1299 - Takayasu Norimatsu, Ryosuke Fujiwara, Masaru Kokubo, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
A UWB-IR Transmitter With Digitally Controlled Pulse Generator. 1300-1309 - Massimo Brandolini, Marco Sosio, Francesco Svelto:
A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS. 1310-1317 - Hoesam Jeong, Byoung-Joo Yoo, Cheol Kyu Han, Sang-Yoon Lee, Kang-Yoon Lee, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. 1318-1327 - David Simmonds, Raymond T. Cheung, Taoling Fu, Peter Borowitz, Richard Schwab, Robert Ruth, Per Karlsen, Klaas van Zalinge:
A CDMA Dual-Band Zero-IF Receiver With Integrated LNAs and VCOs in an Advanced SiGe BiCMOS Process. 1328-1338 - Jongrit Lerdworatawee, Won Namgoong:
Generalized Linear Periodic Time-Varying Analysis for Noise Reduction in an Active Mixer. 1339-1351 - Jeongwook Koh, Doris Schmitt-Landsiedel, Roland Thewes, Ralf Brederlow
A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs. 1352-1361 - Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya:
Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. 1362-1369 - Saibal Mukhopadhyay, Keejong Kim, Hamid Mahmoodi
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS. 1370-1382 - Nad E. Gilbert, Michael N. Kozicki:
An Embeddable Multilevel-Cell Solid Electrolyte Memory Array. 1383-1391 - Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija:
The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements. 1392-1404 - Suwen Yang, Brian D. Winters, Mark R. Greenstreet:
Surfing Pipelines: Theory and Implementation. 1405-1414 - Anup P. Jose, Kenneth L. Shepard:
Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication. 1415-1424 - Krishnakumar Sundaresan, Gavin K. Ho, Siavash Pourkamali, Farrokh Ayazi:
Electronically Temperature Compensated Silicon Bulk Acoustic Resonator Reference Oscillators. 1425-1434
Volume 42, Number 7, July 2007
- Krishnaswamy Nagaraj:
New Associate Editors. 1451-1452 - Andreas Kaiser
Introduction to the Special Issue on ESSCIRC 2006. 1453-1454 - Ullrich R. Pfeiffer
A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control. 1455-1463 - Ahmet Öncü
22-29 GHz Ultra-Wideband CMOS Pulse Generator for Short-Range Radar Applications. 1464-1471 - Dries Hauspie, Eun-Chul Park, Jan Craninckx
Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size. 1472-1480 - Aminghasem Safarian, Lei Zhou, Payam Heydari:
CMOS Distributed Active Power Combiners and Splitters for Multi-Antenna UWB Beamforming Transceivers. 1481-1491 - Mikael Gustafsson, Aarno Pärssinen
A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver. 1492-1500 - Vito Giannini
Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends. 1501-1512 - David Chamla, Andreas Kaiser
A Switchable-Order Gm-C Baseband Filter With Wide Digital Tuning for Configurable Radio Receivers. 1513-1521 - Paolo Bruschi
A Fully Integrated Single-Ended 1.5-15-Hz Low-Pass Filter With Linear Tuning Law. 1522-1528 - Johan F. Witte, Kofi A. A. Makinwa, Johan H. Huijsing:
A CMOS Chopper Offset-Stabilized Opamp. 1529-1535 - Giuseppe de Vita, Giuseppe Iannaccone
A Sub-1-V, 10 ppm/°C, Nanopower Voltage Reference Generator. 1536-1542 - Marco Grassi
A 141-dB Dynamic Range CMOS Gas-Sensor Interface Circuit Without Calibration With 16-Bit Digital Output Word. 1543-1554 - David Stoppa, Monica Vatteroni
A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity. 1555-1563 - Theodoros Chalvatzis, Kenneth H. K. Yau, Ricardo Andres Aroca, Peter Schvan, Ming-Ta Yang, Sorin P. Voinigescu:
Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS. 1564-1573 - Jean-Michel Redoute
An EMI Resisting LIN Driver in 0.35-micron High-Voltage CMOS. 1574-1582 - Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations. 1583-1592 - Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz:
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. 1593-1606 - Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A Low-Power Embedded SRAM for Wireless Applications. 1607-1617 - Behzad Mesgarzadeh, Martin Hansson, Atila Alvandpour:
Jitter Characteristic in Charge Recovery Resonant Clock Distribution. 1618-1625
Volume 42, Number 8, August 2007
- Krishnaswamy Nagaraj:
Message from the Outgoing Editor-in-Chief. 1631 - Bram Nauta
Message from the Incoming Editor-in-Chief. 1632 - Ravi K. Kolagotla, Krzysztof Iniewski, Ranjit Gharpurey:
Introduction to the Special Issue on the IEEE 2006 Custom Integrated Circuits Conference. 1633-1634 - Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. 1635-1641 - Prabir C. Maulik, Douglas A. Mercer:
A DLL-Based Programmable Clock Multiplier in 0.18-µm CMOS With -70 dBc Reference Spur. 1642-1648 - Changhua Cao, Yanping Ding, Kenneth K. O:
A 50-GHz Phase-Locked Loop in 0.13-µm CMOS. 1649-1656 - David S. Ricketts, Xiaofeng Li, Nan Sun, Kyoungho Woo, Donhee Ham
On the Self-Generation of Electrical Soliton Pulses. 1657-1668 - Nuntachai Poobuapheun, Wei-Hung Chen, Zdravko Boos, Ali M. Niknejad:
A 1.5-V 0.7-2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers. 1669-1677 - Jau-Jr Lin, Hsin-Ta Wu, Yu Su, Li Gao, Aravind Sugavanam, Joe E. Brewer, Kenneth K. O:
Communication Using Antennas Fabricated in Silicon Integrated Circuits. 1678-1687 - Douglas A. Mercer:
Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-µm CMOS. 1688-1698 - Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon:
Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters. 1699-1709 - Albert C. Jerng, Charles G. Sodini:
A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters. 1710-1722 - Chunlei Shi, Brett C. Walker, Eric Zeisel, Brian Hu, Gene H. McAllister:
A Highly Integrated Power Management IC for Advanced Mobile Applications. 1723-1731 - Mohammad Al-Shyoukh, Hoi Lee, Raul A. Perez:
A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation. 1732-1742 - Mona Safi-Harb, Gordon W. Roberts:
70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS. 1743-1757 - Shanthi Pavan, Tonse Laxminidhi:
Accurate Characterization of Integrated Continuous-Time Filters. 1758-1766 - Byeong-Gyu Nam
A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems. 1767-1778 - Christoph Hagleitner, Anthony R. Bonaccio, Hugo E. Rothuizen, Jan Lienemann
Modeling, Design, and Verification for the Analog Front-End of a MEMS-Based Parallel Scanning-Probe Storage Device. 1779-1789 - Ajit Sharma, Faisal Zaman, Farrokh Ayazi:
A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork Microgyroscopes. 1790-1802 - Levent Yobas, Hongmiao Ji, Wing-Cheong Hui, Yu Chen, Tit Meng Lim, Chew-Kiat Heng
Nucleic Acid Extraction, Amplification, and Detection on Si-Based Microfluidic Platforms. 1803-1813
Volume 42, Number 9, September 2007
- Hugo Veenstra:
Introduction to the 2006 Bipolar/BiCMOS Circuits and Technology Meeting. 1819-1820 - Sean T. Nicolson, Kenneth H. K. Yau, Pascal Chevalier
Design and Scaling of W-Band SiGe BiCMOS VCOs. 1821-1833 - André van Bezooijen, Freek van Straten, Reza Mahmoudi, Arthur H. M. van Roermund:
Power Amplifier Protection by Adaptive Output Power Control. 1834-1841 - Jean-Christophe Giraudin, Franck Badets
Development of Embedded Three-Dimensional 35-nF/mm2 MIM Capacitor and BiCMOS Circuits Characterization. 1842-1850 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A 54 dBOmega + 42 dB 10 Gb/s SiGe transimpedance-limiting amplifier using bootstrap photodiode capacitance neutralization and vertical threshold adjustment. 1851-1864
- Sunghyun Park, Yorgos Palaskas, Michael P. Flynn:
A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. 1865-1872 - Zhimin Li, Terri S. Fiez:
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth. 1873-1883 - Paolo Bruschi
A Current-Mode, Dual Slope, Integrated Capacitance-to-Pulse Duration Converter. 1884-1891 - Payam Heydari:
Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA. 1892-1905 - Jun-Chau Chien, Liang-Hung Lu:
Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection. 1906-1915 - Ahmad Mirzaei, Mohammad E. Heidari, Rahim Bagheri, Saeed Chehrazi, Asad A. Abidi:
The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking. 1916-1932 - Alan W. L. Ng, Howard C. Luong
A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling. 1933-1941 - Jun-Chau Chien, Liang-Hung Lu:
Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture. 1942-1952 - Svetoslav Gueorguiev, Saska Lindfors, Torben Larsen
A 5.2 GHz CMOS I/Q Modulator With Integrated Phase Shifter for Beamforming. 1953-1962 - Hsiao-Chin Chen, Tao Wang, Shey-Shi Lu
A 5-6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler. 1963-1975 - Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. 1976-1985 - Lincoln Lai Kan Leung, Dennis M. C. Lau, Shuzuo Lou, Alan W. L. Ng, Rachel Dan Wang, Gary Wing-Kei Wong, Patrick Y. Wu, Hui Zheng, Vincent Sin-Luen Cheung, Howard C. Luong
A 1-V 86-mW-RX 53-mW-TX Single-Chip CMOS Transceiver for WLAN IEEE 802.11a. 1986-1998 - Srikanth Gondi, Behzad Razavi:
Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers. 1999-2011 - Won-Jun Choe, Bong-Joon Lee, Jaeha Kim, Deog-Kyoon Jeong, Gyudong Kim:
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme. 2012-2020 - Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo:
A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications. 2021-2033 - Kwen-Siong Chong, Bah-Hwee Gwee
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. 2034-2045 - Hideo Yamasaki, Tadashi Shibata:
A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture. 2046-2053 - Nitin Mohan, Manoj Sachdev:
Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs. 2054-2060 - Fang-Shi Lai, Chia-Fu Lee:
On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology. 2061-2070
Volume 42, Number 10, October 2007
- Peter Katzin, Peter J. Zampardi:
Introduction to the Special Issue on the Third IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). 2075-2076 - Timothy O. Dickson, Sorin P. Voinigescu:
Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS. 2077-2085 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A 3.3 V 12.5 Gb/s 0.2 µm SiGe BiCMOS Laser Diode Driver Using Bias Current Modulation Cancellation. 2086-2098
- Saverio Trotta, Herbert Knapp, Klaus Aufinger, Thomas F. Meister, Josef Böck, Bernhard Dehlink, Werner Simbürger, Arpad L. Scholtz:
An 84 GHz Bandwidth and 20 dB Gain Broadband Amplifier in SiGe Bipolar Technology. 2099-2106 - William R. Deal, Michael Biedenbender, Po-Hsin Liu, Jansen Uyeda, Mansoor Siddiqui, Richard Lai:
Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers. 2107-2115 - Kevin W. Kobayashi:
Linearized Darlington Cascode Amplifier Employing GaAs PHEMT and GaN HEMT Technologies. 2116-2122 - Tohru Oka, Masatomo Hasegawa, Michitoshi Hirata, Yoshihisa Amano, Yoshiteru Ishimaru, Hiroshi Kawamura, Keiichi Sakuno:
A High-Power Low-Distortion GaAs HBT Power Amplifier for Mobile Terminals Used in Broadband Wireless Applications. 2123-2129 - David Schmelzer, Stephen I. Long:
A GaN HEMT Class F Amplifier at 2 GHz With > 80% PAE. 2130-2136 - Andre G. Metzger, Ravi Ramanathan, Jiang Li, Hsiang-Chih Sun, Cristian Cismaru, Hongxiao Shao, Lance Rushing, Kenneth P. Weller, Ce-Jun Wei, Yu Zhu, Alexei Klimashov, Yevgeniy A. Tkachenko, Bin Li, Peter J. Zampardi:
An InGaP/GaAs Merged HBT-FET (BiFET) Technology and Applications to the Design of Handset Power Amplifiers. 2137-2148 - Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration. 2149-2160 - Hao-Chiao Hong
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC. 2161-2168 - Zhiheng Cao, Tongyu Song, Shouli Yan:
A 14 mW 2.5 MS/s 14 bit ΣΔ Modulator Using Split-Path Pseudo-Differential Amplifiers. 2169-2179 - Raymond T. Perry, Stephen H. Lewis, A. Paul Brokaw, T. R. Viswanathan:
A 1.4 V Supply CMOS Fractional Bandgap Reference. 2180-2186 - Yu M. Chi, Udayan Mallik
CMOS Camera With In-Pixel Temporal Change Detection and ADC. 2187-2196 - You Zheng, Carlos E. Saavedra
A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique. 2197-2203 - Paul T. M. van Zeijl, Manel Collados:
A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS. 2204-2211 - Emanuele Lopelli, Johan van der Tang, Arthur H. M. van Roermund:
A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion. 2212-2223 - Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker:
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. 2224-2234 - Armin Tajalli, Paul Muller, Yusuf Leblebici:
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. 2235-2244 - Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon, Bruce F. Cockburn, Duncan G. Elliott
Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder. 2245-2256 - Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. 2257-2269 - Alberto Fazzi, Luca Magagni, Mauro Mirandola, Barbara Charlet, Léa Di Cioccio, Erik Jung
3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly. 2270-2282 - Ran Li, Xiaoling Guo, Dong-Jun Yang, Kenneth K. O:
Wireless Clock Distribution System Using an External Antenna. 2283-2292 - Anand Pappu, Xuan Zhang
Process-Invariant Current Source Design: Methodology and Examples. 2293-2302 - Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy:
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM. 2303-2313 - Abumoslem Jannesari, Mahmoud Kamarei:
Comments on "A General Theory of Phase Noise in Electrical Oscillators". 2314 - Kong-Pang Pun, Shouri Chatterjee, Peter R. Kinget
Author's Response. 2315 - Kong-Pang Pun, Shouri Chatterjee, Peter R. Kinget
Correction to "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC". 2315 - Atsushi Yoshizawa, Yannis P. Tsividis:
Correction to "A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation". 2316
Volume 42, Number 11, November 2007
- Sung-Bae Park, Suhwan Kim:
Introduction to the Special Issue on the 2006 Asian Solid-State Circuits Conference (A-SSCC'06). 2323-2325 - Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura:
A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. 2326-2337 - Rong-Jyi Yang, Shen-Iuan Liu:
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology. 2338-2347 - Simone Gambini, Jan M. Rabaey:
Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS. 2348-2356 - Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo, Kai-Jiun Yang:
A 2.5-V 14-bit, 180-mW Cascaded ΣΔ ADC for ADSL2+ Application. 2357-2368 - Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn:
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. 2369-2377 - Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo
A 16-Mb Toggle MRAM With Burst Modes. 2378-2385 - Tao Chen, Georges G. E. Gielen
A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration. 2386-2394 - Masato Koutani, Hiroshi Kawamura, Shinji Toyoyama, Kunihiko Iizuka:
A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers. 2395-2403 - Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. 2404-2410 - Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio:
A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter. 2411-2420 - Sang Wook Park, José L. Ausín
Nonlinear Shaping SC Oscillator With Enhanced Linearity. 2421-2431 - Sunyoung Kim, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A 0.9 V 96 µW Fully Operational Digital Hearing Aid Chip. 2432-2440 - Patrick Y. Wu, Philip K. T. Mok
A Monolithic Buck Converter With Near-Optimum Reference Tracking Response Using Adaptive-Output-Feedback. 2441-2450 - Hong-Wei Huang, Ke-Horng Chen
Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications. 2451-2465 - Keith E. Sanborn, Dongsheng Ma, Vadim V. Ivanov:
A Sub-1-V Low-Noise Bandgap Voltage Reference. 2466-2481 - Ralf M. Philipp, David Orr, Viktor Gruev, Jan Van der Spiegel, Ralph Etienne-Cummings:
Linear Current-Mode Active Pixel Sensor. 2482-2491 - Leonid Belostotski
Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 Ω Signal-Source Impedance. 2492-2502 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture. 2503-2514
- Julien Ryckaert, Marian Verhelst
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. 2515-2527 - Haifeng Xu, Kenneth K. O:
A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells. 2528-2534 - Kwang-Jin Koh, Gabriel M. Rebeiz:
0.13-µm CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays. 2535-2546 - Byung-Wook Min
A 10-50-GHz CMOS Distributed Step Attenuator With Low Loss and Low Phase Imbalance. 2547-2554 - Walter D. Leon-Salas, Sina Balkir, Khalid Sayood, Nathan Schemm, Michael W. Hoffman:
A CMOS Imager With Focal Plane Compression Using Predictive Coding. 2555-2572 - Rafal Karakiewicz, Roman Genov, Gert Cauwenberghs
480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition. 2573-2584 - Xu Cheng, Russell Duane
Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device. 2585-2593 - Yasuyuki Suzuki, Masayuki Mamada, Zin Yamazaki:
Over-100-Gb/s 1: 2 Demultiplexer Based on InP HBT Technology. 2594-2599 - Michael Wieckowski, Sandeep Patil, Martin Margala
Portless SRAM - A High-Performance Alternative to the 6T Methodology. 2600-2610 - Kazutami Arimoto, Fukashi Morishita
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. 2611-2619
Volume 42, Number 12, December 2007
- Jan Sevenhans, John T. Stonick, Matt Miller, J. E. D. Hurwitz:
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. 2635-2638 - Ashok Swaminathan, Kevin J. Wang, Ian Galton:
A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation. 2639-2650 - Matti Paavola, Mika Kämäräinen, Jere A. M. Järvinen, Mikko Saukoski, Mika Laiho
A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer. 2651-2665 - Tae-Woo Kwak, Min-Chul Lee, Gyu-Hyeong Cho:
A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters. 2666-2676 - Lane Brooks, Hae-Seung Lee:
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC. 2677-2687 - Seung-Chul Lee, Young-Deuk Jeon, Jong-Kee Kwon, Jongdae Kim:
A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications. 2688-2695 - Lucien J. Breems, Robert Rutten, Robert H. M. van Veldhoven, Gerard van der Weide:
A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band. 2696-2705 - Hanh-Phuc Le
A Single-Inductor Switching DC-DC Converter With Five Outputs and Ordered Power-Distributive Control. 2706-2714 - Jun-Chau Chien, Liang-Hung Lu:
40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-µm CMOS. 2715-2725 - Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. 2726-2735 - Adithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Sherif Abdalla, Erwin Balmater, Steffen Gloeckner, Drew Guckenberger, Mark Harrison, Roger G. M. P. Koumans, Daniel Kucharski, Attila Mekis, Sina Mirsaidi, Dan Song, Thierry Pinguet:
A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology. 2736-2744 - John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz:
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. 2745-2757 - Waleed Khalil, Bertan Bakkaloglu
A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With -75 dBc Single-Tone Sensitivity at 100 kHz Offset. 2758-2765 - Hooman Darabi:
A Blocker Filtering Technique for SAW-Less Wireless Receivers. 2766-2773 - Petri Eloranta, Pauli Seppinen, Sami Kallioinen, Tuomas Saarela, Aarno Pärssinen
A Multimode Transmitter in 0.13 µm CMOS Using Direct-Digital RF Modulator. 2774-2784 - Josef Zipper, Claus Stoger, Gernot Hueber, Rastislav Vazny, Werner Schelmbauer, Bernd Adler, Richard Hagelauer:
A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 µm CMOS. 2785-2794 - Arya Behzad, Keith A. Carter, Hung-Ming Chien, Stephen Wu, Meng-An Pan, C. Paul Lee, Qiang (Tom) Li, John C. Leete, Stephen Au, Michael S. Kappes, Zhimin Zhou, Dayo Ojo, Lijun Zhang, Alireza Zolfaghari, Jesse Castaneda, Hooman Darabi, Benson Yeung, Ahmadreza Rofougaran, Maryam Rofougaran, Jason Trachewsky, Tushar Moorti, Rohit V. Gaikwad, Amit Bagchi, Joachim S. Hammerschmidt, Jay Pattin, Jacob J. Rael, Bojko Marholev:
A Fully Integrated MIMO Multiband Direct Conversion CMOS Transceiver for WLAN Applications (802.11n). 2795-2808 - Jean-Robert Tourret, Sébastien Amiot, Maxime Bernard, Mohamed Bouhamame, Claude Caron, Olivier Crand, Gilles Denise, Vincent Fillatre, Thibault Kervaon, Markus Kristen, Luca Lo Coco, Frédéric Mercier, Jean Marc Paris, François Pichon, Sébastien Prouet, Vincent Rambeau, Sebastien Robert, Jan van Sinderen, Olivier Susplugas:
SiP Tuner With Integrated LC Tracking Filter for Both Cable and Terrestrial TV Reception. 2809-2821 - Scott Chiu, Issy Kipnis, Marc Loyer, Jan Rapp, David Westberg, Jonas Johansson, Peter Johansson:
A 900 MHz UHF RFID Reader Transceiver IC. 2822-2833 - Ta-Shun Chu, Jonathan Roderick, Hossein Hashemi
An Integrated Ultra-Wideband Timed Array Receiver in 0.13µm CMOS Using a Path-Sharing True Time Delay Architecture. 2834-2850 - Fred S. Lee, Anantha P. Chandrakasan:
A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS. 2851-2859 - Julien Ryckaert, Geert Van der Plas
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. 2860-2869 - Giuseppe Cusmai, Matteo Repossi
A Magnetically Tuned Quadrature Oscillator. 2870-2877 - KaChun Kwok, John R. Long:
A 23-to-29 GHz Transconductor-Tuned VCO MMIC in 0.13 µm CMOS. 2878-2886 - Behzad Razavi:
Heterodyne Phase Locking: A Technique for High-Speed Frequency Division. 2887-2892 - Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad:
Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS. 2893-2903 - Chris J. Brown, Hiromi Kato, Kazuhiro Maeda, Ben Hadwen
A Continuous-Grain Silicon-System LCD With Optical Input Function. 2904-2912 - Jin-Seong Kang, Jin-Ho Kim
10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs). 2913-2922 - Christian Schott, Robert Racz, Angelo Manco, Nicolas Simonne:
CMOS Single-Chip Electronic Compass With Microcontroller. 2923-2933 - Tim Denison
A 2 µW 100 nV/rtHz Chopper-Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field Potentials. 2934-2945 - Maurits Ortmanns, André Rocke, Marcus Gehrke, Hans-Jürgen Tiedtke:
A 232-Channel Epiretinal Stimulator ASIC. 2946-2959 - Hidekazu Takahashi, Tomoyuki Noda, Takashi Matsuda, Takanori Watanabe, Mahito Shinohara, Toshiaki Endo, Shunsuke Takimoto, Ryuichi Mishima, Shigeru Nishimura, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue:
A 1/2.7-in 2.96 MPixel CMOS Image Sensor With Double CDS Architecture for Full High-Definition Camcorders. 2960-2967 - Martijn F. Snoeij, Albert J. P. Theuwissen, Kofi A. A. Makinwa, Johan H. Huijsing:
Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors. 2968-2977 - Jaehyuk Choi, Sang-Wook Han, Seong-Jin Kim
A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects in Region-of-Interest and Suppressing Motion Blur. 2978-2989
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