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Matteo Sonza Reorda

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affiliation: Polytechnic University of Turin, Italy

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2020 – today

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2024
[j86]
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Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda:
Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs. J. Electron. Test. 40(2): 215-228 (2024)
[c433]
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V. Turco, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda:
Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related Metrics. DDECS 2024: 13-18
[c432]
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Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS 2024: 104-109
[c431]
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Serag E.-D. Habib:
Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults. DDECS 2024: 124-129
[c430]
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Tobias Faller, Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Bernd Becker:
Special Session: Software-Based Self-Test Generation for RISC-V - Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration -. DFT 2024: 1-6
[c429]
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Riccardo Cantoro, Michelangelo Grosso, Iacopo Guglielminetti, Reza Khoshzaban, Matteo Sonza Reorda:
Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test. ETS 2024: 1-4
[c428]
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Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Robert Limas Sierra, Matteo Sonza Reorda:
Analyzing the Structural and Operational Impact of Faults in Floating-Point and Posit Arithmetic Cores for CNN Operations. ETS 2024: 1-4
[c427]
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Michelangelo Bartolomucci, Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda:
Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects. IOLTS 2024: 1-6
[c426]
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Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda:
Enhancing the Reliability of Split Computing Deep Neural Networks. IOLTS 2024: 1-7
[c425]
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Francesco Pessia, Juan-David Guerrero-Balaguera, Robert Limas Sierra, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda:
Effective Application-level Error Modeling of Permanent Faults on AI Accelerators. IOLTS 2024: 1-7
[c424]
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Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda:
Assessing the Reliability of Different Split Computing Neural Network Applications. LATS 2024: 1-6
[c423]
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Junchao Chen, Giuseppe Esposito, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Angeliki Kritikakou, Milos Krstic, Robert Limas Sierra, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Marcello Traiola, Alessandro Veronesi:
Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy. VLSI-SoC 2024: 1-10
[c422]
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Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola:
Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS 2024: 1-11
[c421]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda:
Evaluating the Reliability of Supervised Compression for Split Computing. VTS 2024: 1-6
[c420]
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Robert Limas Sierra, Juan-David Guerrero-Balaguera, Francesco Pessia, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Analyzing the Impact of Scheduling Policies on the Reliability of GPUs Running CNN Operations. VTS 2024: 1-7
2023
[j85]
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Francesco Angione, Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Quer, Matteo Sonza Reorda, Vincenzo Tancorre, Roberto Ugioli:
A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips. IEEE Access 11: 105655-105676 (2023)
[j84]
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Josie E. Rodriguez Condia, Felipe Augusto da Silva, Ahmet Çagri Bagbaga, Juan-David Guerrero-Balaguera, Said Hamdioui, Christian Sauer, Matteo Sonza Reorda:
Using STLs for Effective In-Field Test of GPUs. IEEE Des. Test 40(2): 109-117 (2023)
[j83]
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  - journals/dt/GuerreroBalagueraCR23
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
STLs for GPUs: Using High-Level Language Approaches. IEEE Des. Test 40(4): 51-60 (2023)
[j82]
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  - journals/mam/DeligiannisCR23
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda:
Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques. Microprocess. Microsystems 98: 104775 (2023)
[j81]
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Francesco Angione, Davide Appello, Paolo Bernardi, Claudia Bertani, Giovambattista Gallo, Stefano Littardi, Giorgio Pollaccia, Walter Ruggeri, Matteo Sonza Reorda, Vincenzo Tancorre, Roberto Ugioli:
A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress. IEEE Trans. Computers 72(5): 1447-1459 (2023)
[j80]
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  - journals/tcad/AnghelCMPSR23
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Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda:
Self-Test Library Generation for In-Field Test of Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4246-4259 (2023)
[j79]
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Nikolaos Ioannis Deligiannis, Tobias Faller, Riccardo Cantoro, Tobias Paxian, Bernd Becker, Matteo Sonza Reorda:
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4270-4281 (2023)
[c419]
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Nikolaos Ioannis Deligiannis, Tobias Faller, Iacopo Guglielminetti, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda:
Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors. ATS 2023: 1-6
[c418]
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Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, J. Guerrero, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, J. Aribido, Jyotika Athavale:
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections. DATE 2023: 1-6
[c417]
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Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Vincenzo Tancorre:
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults. DDECS 2023: 21-26
[c416]
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Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
A Reliability-aware Environment for Design Exploration for GPU Devices. DDECS 2023: 169-174
[c415]
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  - conf/dft/CantoroSRAP23
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Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan:
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. DFT 2023: 1-7
[c414]
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Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. DFT 2023: 1-6
[c413]
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  - conf/dft/TurcoRGSR23
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V. Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sánchez, Matteo Sonza Reorda:
Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test Libraries. DFT 2023: 1-6
[c412]
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  - conf/dsd/MirabellaFCGR23
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Nunzio Mirabella, Andrea Floridia, Riccardo Cantoro, Michelangelo Grosso, Matteo Sonza Reorda:
Targeting different defect-oriented fault models in IC testing: an experimental approach. DSD 2023: 214-219
[c411]
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Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric:
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. ETS 2023: 1-10
[c410]
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Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda:
Evaluating the Prevalence of SFUs in the Reliability of GPUs. ETS 2023: 1-6
[c409]
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Nikolaos Ioannis Deligiannis, Tobias Faller, Chenghan Zhou, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda:
Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing. ETS 2023: 1-5
[c408]
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Tobias Faller, Nikolaos Ioannis Deligiannis, Markus Schwörer, Matteo Sonza Reorda, Bernd Becker:
Constraint-Based Automatic SBST Generation for RISC-V Processor Families. ETS 2023: 1-6
[c407]
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Annachiara Ruospo, Gabriele Gavarini, A. Porsia, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, J. Aribido, Jyotika Athavale:
Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs. ETS 2023: 1-6
[c406]
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Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS 2023: 1-7
[c405]
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  - conf/isie/GuerreroBalagueraHCLR23
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Juan-David Guerrero-Balaguera, Ian Harshbarger, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda:
Reliability Estimation of Split DNN Models for Distributed Computing in IoT Systems. ISIE 2023: 1-4
[c404]
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Francesco Angione, Paolo Bernardi, Riccardo Cantoro, Nicola Di Gruttola Giardino, Davide Piumatti, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre:
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems. LATS 2023: 1-6
[c403]
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Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda:
Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs. LATS 2023: 1-6
[c402]
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William Fornaciari, Federico Reghenzani, Federico Terraneo, Davide Baroffio, Cecilia Metra, Martin Omaña, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Robert Birke, Iacopo Colonnelli, Gianluca Mittone, Marco Aldinucci, Gabriele Mencagli, Francesco Iannone, Filippo Palombi, Giuseppe Zummo, Daniele Cesarini, Federico Tesser:
RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters. SAMOS 2023: 395-410
[c401]
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Juan-David Guerrero-Balaguera, Josie Esteban Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech:
Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units. SC 2023: 46:1-46:14
[c400]
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  - conf/supercomputer/CondiaDSCR23
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Josie E. Rodriguez Condia, Nikolaos Ioannis Deligiannis, Jacopo Sini, Riccardo Cantoro, Matteo Sonza Reorda:
Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters. ISC Workshops 2023: 444-457
[c399]
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Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs. VLSI-SoC 2023: 1-6
[c398]
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Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Evaluating the Impact of Transition Delay Faults in GPUs. VLSID 2023: 353-358
[i12]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech:
Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units. CoRR abs/2306.10856 (2023)
2022
[j78]
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Marcio M. Gonçalves, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone, José Rodrigo Azambuja:
Evaluating low-level software-based hardening techniques for configurable GPU architectures. J. Supercomput. 78(6): 8081-8105 (2022)
[c397]
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Nikolaos Ioannis Deligiannis, Tobias Faller, Josie E. Rodriguez Condia, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda:
Using Formal Methods to Support the Development of STLs for GPUs. ATS 2022: 84-89
[c396]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
A Compaction Method for STLs for GPU in-field test. DATE 2022: 454-459
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Francesco Angione, Paolo Bernardi, Gabriele Filipponi, Claudia Tempesta, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli:
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level. DFT 2022: 1-6
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea:
Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms. DSN (Supplements) 2022: 23-24
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Hussam Amrouch, Krishnendu Chakrabarty, Dirk Pflüger, Ilia Polian, Matthias Sauer, Matteo Sonza Reorda:
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. ETS 2022: 1-6
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Francesco Angione, Davide Appello, J. Aribido, Jyotika Athavale, Nicolò Bellarmino, Paolo Bernardi, Riccardo Cantoro, Corrado De Sio, Tommaso Foscale, Gabriele Gavarini, J. Guerrero, Martin Huch, Giusy Iaria, Tobias Kilian, Riccardo Mariani, Raffaele Martone, Annachiara Ruospo, Ernesto Sánchez, Ulf Schlichtmann, Giovanni Squillero, Matteo Sonza Reorda, Luca Sterpone, Vincenzo Tancorre, Roberto Ugioli:
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip. ETS 2022: 1-10
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Francesco Angione, Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli:
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip. ETS 2022: 1-6
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Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel:
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS 2022: 1-2
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Neural Network's Reliability to Permanent Faults: Analyzing the Impact of Performance Optimizations in GPUs. ICECS 2022 2022: 1-4
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Nunzio Mirabella, Andrea Floridia, Riccardo Cantoro, Michelangelo Grosso, Matteo Sonza Reorda:
A comparative overview of ATPG flows targeting traditional and cell-aware fault models. ICECS 2022 2022: 1-4
[c387]
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Paolo Bernardi, Riccardo Cantoro, Anthony Coyette, W. Dobbeleare, Moritz Fieback, Andrea Floridia, G. Gielenk, Jhon Gomez, Michelangelo Grosso, Andrea Guerriero, Iacopo Guglielminetti, Said Hamdioui, Giorgio Insinga, N. Mautone, Nunzio Mirabella, Sandro Sartoni, Matteo Sonza Reorda, Rudolf Ullmann, Ronny Vanhooren, N. Xamak, Lizhou Wu:
Recent Trends and Perspectives on Defect-Oriented Testing. IOLTS 2022: 1-10
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Juan-David Guerrero-Balaguera, Robert Limas Sierra, Matteo Sonza Reorda:
Effective fault simulation of GPU's permanent faults for reliability estimation of CNNs. IOLTS 2022: 1-6
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Giusy Iaria, Tommaso Foscale, Paolo Bernardi, Luca Presicce, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli:
A novel SEU injection setup for Automotive SoC. ISIE 2022: 623-626
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Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Matteo Sonza Reorda:
Reliability Assessment of Neural Networks in GPUs: A Framework For Permanent Faults Injections. ISIE 2022: 959-962
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Josie E. Rodriguez Condia, Riccardo Faggiano, Matteo Sonza Reorda:
Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUs. ISVLSI 2022: 26-31
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Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI 2022: 394-397
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Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech:
A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability. ITC 2022: 278-287
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Gabriele Filipponi, Giusy Iaria, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre:
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip. ITC 2022: 646-649
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Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Ernesto Sánchez, Matteo Sonza Reorda:
Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network. ITC-Asia 2022: 96-101
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Giusy Iaria, Francesco Angione, Paolo Bernardi, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre:
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip. LATS 2022: 1-6
[c377]
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Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda:
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. VTS 2022: 1-7
[c376]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages. VTS 2022: 1-7
[i11]
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  - journals/corr/abs-2205-12177
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Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Matteo Sonza Reorda:
Reliability Assessment of Neural Networks in GPUs: A Framework For Permanent Faults Injections. CoRR abs/2205.12177 (2022)
[i10]
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Fernando Fernandes dos Santos, Angeliki Kritikakou, Josie Esteban Rodriguez Condia, Juan-David Guerrero-Balaguera, Matteo Sonza Reorda, Olivier Sentieys, Paolo Rech:
Characterizing a Neutron-Induced Fault Model for Deep Neural Networks. CoRR abs/2211.13094 (2022)
2021
[j77]
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea:
Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks. IEEE Access 9: 155998-156012 (2021)
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Marcelo Lubaszewki, Matteo Sonza Reorda:
Guest Editors' Introduction: SBCCI 2019. IEEE Des. Test 38(4): 60-61 (2021)
[j75]
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Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability. J. Supercomput. 77(10): 11625-11642 (2021)
[c375]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
A Novel Compaction Approach for SBST Test Programs. ATS 2021: 67-72
[c374]
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  - conf/ats/DeligiannisCFPB21
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Tobias Faller, Tobias Paxian, Bernd Becker, Matteo Sonza Reorda:
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor. ATS 2021: 73-78
[c373]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
On the Functional Test of Special Function Units in GPUs. DDECS 2021: 81-86
[c372]
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda:
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques. DSD 2021: 535-540
[c371]
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Fernando Fernandes dos Santos, Josie E. Rodriguez Condia, Luigi Carro, Matteo Sonza Reorda, Paolo Rech:
Revealing GPUs Vulnerabilities by Combining Register-Transfer and Software-Level Fault Injection. DSN 2021: 292-304
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Walter Ruggeri, Paolo Bernardi, Stefano Littardi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli:
Innovative methods for Burn-In related Stress Metrics Computation. DTIS 2021: 1-6
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Using Hardware Performance Counters to support infield GPU Testing. ICECS 2021: 1-4
[c368]
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Davide Appello, H. H. Chen, Matthias Sauer, Ilia Polian, Paolo Bernardi, Matteo Sonza Reorda:
System-Level Test: State of the Art and Challenges. IOLTS 2021: 1-7
[c367]
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Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel:
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS 2021: 1-4
[c366]
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Josie E. Rodriguez Condia, Paolo Rech, Fernando Fernandes dos Santos, Luigi Carro, Matteo Sonza Reorda:
Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening. IOLTS 2021: 1-7
[c365]
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Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda:
Comparing different solutions for testing resistive defects in low-power SRAMs. LATS 2021: 1-6
[c364]
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Josie E. Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech:
Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs. VTS 2021: 1-7
[c363]
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Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matthias Sauer, Bernd Becker, Matteo Sonza Reorda:
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core. VTS 2021: 1-7
[i9]
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Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. CoRR abs/2103.06656 (2021)
[i8]
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Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
A Novel Compaction Approach for SBST Test Programs. CoRR abs/2109.00958 (2021)
[i7]
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Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda:
Comparing different solutions for testing resistive defects in low-power SRAMs. CoRR abs/2112.15176 (2021)
2020
[j74]
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Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
An On-Line Testing Technique for the Scheduler Memory of a GPGPU. IEEE Access 8: 16893-16912 (2020)
[j73]
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Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero:
A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks. IEEE Trans. Computers 69(1): 87-98 (2020)
[j72]
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Cecilia Metra, Matteo Sonza Reorda:
Guest Editor's Introduction: Special Section on High Dependability Systems. IEEE Trans. Emerg. Top. Comput. 8(2): 416-417 (2020)
[c362]
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Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. ATS 2020: 1-6
[c361]
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Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE 2020: 388-393
[c360]
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Paolo Bernardi, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, D. Petrali:
Applicative System Level Test introduction to Increase Confidence on Screening Quality. DDECS 2020: 1-6
[c359]
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Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs. DDECS 2020: 1-6
[c358]
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Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea:
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network. DFT 2020: 1-4
[c357]
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Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Sandro Sartoni, Riccardo Cantoro, Matteo Sonza Reorda, Said Hamdioui, Christian Sauer:
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs. ETS 2020: 1-6
[c356]
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Josie E. Rodriguez Condia, Matteo Sonza Reorda:
On the testing of special memories in GPGPUs. IOLTS 2020: 1-6
[c355]
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Josie E. Rodriguez Condia, Marcio Gonçalves, José Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone:
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets. ISVLSI 2020: 380-385
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Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan:
New Perspectives on Core In-field Path Delay Test. ITC 2020: 1-5
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Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea:
Evaluating the Code Encryption Effects on Memory Fault Resilience. LATS 2020: 1-6
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Marcio Gonçalves, José Rodrigo Azambuja, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU. LATS 2020: 1-6
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Davide Piumatti, Matteo Vincenzo Quitadamo, Matteo Sonza Reorda, Franco Fiori:
Testing Heatsink Faults in Power Transistors by means of Thermal Model. LATS 2020: 1-6
[c350]
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Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy. VLSI-SOC 2020: 153-158
[c349]
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Josie Esteban Rodriguez Condia, Matteo Sonza Reorda:
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs. VLSI-SoC (Selected Papers) 2020: 205-233
[c348]
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Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda:
In-field Functional Test of CAN Bus Controllers. VTS 2020: 1-6
[c347]
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Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs. VTS 2020: 1-6
[c346]
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Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer:
Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks. VTS 2020: 1-9
[i6]
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Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. CoRR abs/2009.11621 (2020)

2010 – 2019

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2019
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Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda:
Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications. IEEE Access 7: 63578-63587 (2019)
[j70]
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Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero:
An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests. J. Circuits Syst. Comput. 28(Supplement-1): 1940007:1-1940007:25 (2019)
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Davide Piumatti, Stefano Borlo, Fabio Mandrile, Matteo Sonza Reorda, Radu Bojoi:
Assessing the Effectiveness of the Test of Power Devices at the Board Level. DCIS 2019: 1-6
[c344]
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F. Almeida, Paolo Bernardi, D. Calabrese, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli, Gulio Zoppi:
Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test. DDECS 2019: 1-6
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Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
On the in-field test of the GPGPU scheduler memory. DDECS 2019: 1-6
[c342]
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Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. DDECS 2019: 1-4
[c341]
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Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu:
Challenges of Reliability Assessment and Enhancement in Autonomous Systems. DFT 2019: 1-6
[c340]
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Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
An extended model to support detailed GPGPU reliability analysis. DTIS 2019: 1-6
[c339]
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Luciano Bonaria, Maurizio Raganato, Matteo Sonza Reorda, Giovanni Squillero:
A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers. ETS 2019: 1-2
[c338]
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Josie E. Rodriguez Condia, Felipe Augusto da Silva, Said Hamdioui, Christian Sauer, Matteo Sonza Reorda:
Untestable faults identification in GPGPUs for safety-critical applications. ICECS 2019: 570-573
[c337]
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Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach. IOLTS 2019: 97-102
[c336]
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Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu:
IEEE European Test Symposium (ETS). ITC 2019: 1-4
[c335]
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Luciano Bonaria, Maurizio Raganato, Giovanni Squillero, Matteo Sonza Reorda:
Test-Plan Optimization for Flying-Probes In-Circuit Testers. ITC-Asia 2019: 19-24
[c334]
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Julio Pérez Acle, Ernesto Sánchez, Matteo Sonza Reorda:
About Performance Faults in Microprocessor Core in-field Testing. LASCAS 2019: 229-232
[c333]
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Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
On the evaluation of SEU effects in GPGPUs. LATS 2019: 1-6
[c332]
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Michelangelo Grosso, Matteo Sonza Reorda, Salvatore Rinaudo:
Software-Based Self-Test for Delay Faults. VLSI-SoC (Selected Papers) 2019: 1-19
[c331]
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Michelangelo Grosso, Salvatore Rinaudo, Andrea Casalino, Matteo Sonza Reorda:
Software-Based Self-Test for Transition Faults: a Case Study. VLSI-SoC 2019: 76-81
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João Antonio Martino, Marcelo Lubaszewski, Matteo Sonza Reorda:
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019. ACM 2019, ISBN 978-1-4503-6844-5 [contents]
[e2]
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Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis:
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 500, Springer 2019, ISBN 978-3-030-15662-6 [contents]
[i5]
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Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu:
Challenges of Reliability Assessment and Enhancement in Autonomous Systems. CoRR abs/1909.03040 (2019)
[i4]
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Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR abs/1912.01561 (2019)
2018
[j69]
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Riccardo Cantoro, Farrokh Ghani Zadegan, Marco Palena, Paolo Pasini, Erik Larsson, Matteo Sonza Reorda:
Test of Reconfigurable Modules in Scan Networks. IEEE Trans. Computers 67(12): 1806-1817 (2018)
[j68]
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Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray:
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6(2): 278-287 (2018)
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Davide Piumatti, Matteo Sonza Reorda:
Assessing Test Procedure Effectiveness for Power Devices. DCIS 2018: 1-6
[c329]
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Riccardo Cantoro, Luigi San Paolo, Matteo Sonza Reorda, Giovanni Squillero:
An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test. DDECS 2018: 129-134
[c328]
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Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda:
RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME 2018: 45-50
[c327]
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Sara Carbonara, Andrea Firrincieli, Matteo Sonza Reorda, Jan-Gerd Mess:
On the test of a COTS-based system for space applications. IOLTS 2018: 47-48
[c326]
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Panagiotis Georgiou, Xrysovalantis Kavousianos, Riccardo Cantoro, Matteo Sonza Reorda:
Fault-Independent Test-Generation for Software-Based Self-Testing. IOLTS 2018: 79-84
[c325]
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Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
About the functional test of the GPGPU scheduler. IOLTS 2018: 85-90
[c324]
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Jacopo Sini, Matteo Sonza Reorda, Massimo Violante, Peter Sarson:
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard. IOLTS 2018: 287-290
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Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero:
A New Technique to Generate Test Sequences for Reconfigurable Scan Networks. ITC 2018: 1-9
[c322]
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Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero:
A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks. ITC-Asia 2018: 55-60
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Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda:
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications. LATS 2018: 1-6
[c320]
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Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda, Jan-Gerd Mess:
An analysis of test solutions for COTS-based systems in space applications. VLSI-SoC 2018: 59-64
[c319]
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Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda, Jan-Gerd Mess:
Improved Test Solutions for COTS-Based Systems in Space Applications. VLSI-SoC (Selected Papers) 2018: 187-206
2017
[j67]
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Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017)
[j66]
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Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. J. Electron. Test. 33(1): 53-64 (2017)
[j65]
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Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26(8): 1740007:1-1740007:18 (2017)
[j64]
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Matteo Sonza Reorda, Luca Sterpone, Anees Ullah:
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Trans. Computers 66(6): 1022-1033 (2017)
[j63]
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Marco Gaudesi, Irith Pomeranz, Matteo Sonza Reorda, Giovanni Squillero:
New Techniques to Reduce the Execution Time of Functional Test Programs. IEEE Trans. Computers 66(7): 1268-1273 (2017)
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Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke:
BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE 2017: 115-120
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R. Cantora, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Emanuele Valea:
On the optimization of SBST test program compaction. DFT 2017: 1-4
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Paolo Bernardi, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda:
On the in-field test of embedded memories. IOLTS 2017: 67-70
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Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda:
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. ISVLSI 2017: 533-538
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Gaiping An, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda:
On the detection of board delay faults through the execution of functional programs. LATS 2017: 1-6
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Enea Bagalini, Jacopo Sini, Matteo Sonza Reorda, Massimo Violante, H. Klimesch, Peter Sarson:
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard. LATS 2017: 1-6
2016
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Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016)
[j61]
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Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros:
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32(3): 273-289 (2016)
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Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ACM J. Emerg. Technol. Comput. Syst. 13(2): 16:1-16:13 (2016)
[j59]
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Julio Pérez Acle, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation. Microprocess. Microsystems 47: 392-403 (2016)
[j58]
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Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers 65(6): 1846-1855 (2016)
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Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
A Flexible Framework for the Automatic Generation of SBST Programs. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3055-3066 (2016)
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Riccardo Cantoro, Marco Palena, Paolo Pasini, Matteo Sonza Reorda:
Test Time Minimization in Reconfigurable Scan Networks. ATS 2016: 119-124
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Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar:
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS 2016: 304-309
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Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective approach for functional test programs compaction. DDECS 2016: 119-124
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Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov:
FPGA-controlled PCBA power-on self-test using processor's debug features. DDECS 2016: 125-130
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Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson:
On the diagnostic analysis of IEEE 1687 networks. ETS 2016: 1-2
[c307]
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Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2
[c306]
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Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, Jan-Gerd Mess, Robert Schmidt:
On the robustness of DCT-based compression algorithms for space applications. IOLTS 2016: 1-2
[c305]
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Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson:
Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks. IOLTS 2016: 167-172
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Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI 2016: 731-736
[c303]
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Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath:
A suite of IEEE 1687 benchmark networks. ITC 2016: 1-10
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Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. LATS 2016: 14-19
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Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda:
Hybrid soft error mitigation techniques for COTS processor-based systems. LATS 2016: 99-104
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Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
Effective generation and evaluation of diagnostic SBST programs. VTS 2016: 1-6
2015
[j56]
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Ernesto Sánchez, Matteo Sonza Reorda:
On the Functional Test of Branch Prediction Units. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1675-1688 (2015)
[c299]
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Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson:
On the testability of IEEE 1687 networks. ATS 2015: 211-216
[c298]
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Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
On the automatic generation of SBST test programs for in-field test. DATE 2015: 1186-1191
[c297]
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Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. DATE 2015: 1277-1280
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Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective ATPG flow for Gate Delay Faults. DTIS 2015: 1-6
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Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Scan-chain intra-cell defects grading. DTIS 2015: 1-6
[c294]
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Marco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz:
On test program compaction. ETS 2015: 1-6
[c293]
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Riccardo Cantoro, Matteo Sonza Reorda, Alireza Rohani, Hans G. Kerkhoff:
On the maximization of the sustained switching activity in a processor. IOLTS 2015: 34-35
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Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS 2015: 89-94
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Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ISVLSI 2015: 491-496
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Julio Pérez Acle, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda:
On the functional test of the cache coherency logic in multi-core systems. LASCAS 2015: 1-4
[c289]
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Paolo Bernardi, Lyl M. Ciganda Brasca, Matteo Sonza Reorda, Said Hamdioui:
SW-based transparent in-field memory testing. LATS 2015: 1-6
[c288]
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Ronaldo Rodrigues Ferreira, Ernesto Sánchez, Jean da Rolt, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro, Matteo Sonza Reorda:
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture. LATS 2015: 1-6
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N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls:
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS 2015: 1-6
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Matteo Sonza Reorda:
In-field test of safety-critical systems: is functional test a feasible solution? LATS 2015: 1-2
2014
[j55]
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Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test. J. Electron. Test. 30(3): 317-328 (2014)
[j54]
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Stefano Di Carlo, Marco Gaudesi, Edgar E. Sánchez, Matteo Sonza Reorda:
A Functional Approach for Testing the Reorder Buffer Memory. J. Electron. Test. 30(4): 469-481 (2014)
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Letícia Maria Bolzani Poehls, Matteo Sonza Reorda:
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013. J. Low Power Electron. 10(1): 163-164 (2014)
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results. Microelectron. Reliab. 54(11): 2621-2628 (2014)
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Paolo Bernardi, Lyl Mercedes Ciganda, Ernesto Sánchez, Matteo Sonza Reorda:
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test. IEEE Trans. Computers 63(11): 2760-2771 (2014)
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 813-823 (2014)
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Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich:
High Quality System Level Test and Diagnosis. ATS 2014: 298-305
[c284]
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Leonardo Arturo Bautista-Gomez, Franck Cappello, Luigi Carro, Nathan DeBardeleben, Bo Fang, Sudhanva Gurumurthi, Karthik Pattabiraman, Paolo Rech, Matteo Sonza Reorda:
GPGPUs: How to combine high computational power with high reliability. DATE 2014: 1-9
[c283]
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Andreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker:
An effective approach to automatic functional processor test generation for small-delay faults. DATE 2014: 1-6
[c282]
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Marco Gaudesi, S. Saleem, Ernesto Sánchez, Matteo Sonza Reorda, E. Tanowe:
On the in-field test of Branch Prediction Units using the correlated predictor mechanism. DDECS 2014: 286-289
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Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Ernesto Sánchez, Matteo Sonza Reorda, Sergio de Luca, Renato Meregalli, Alessandro Sansonetti:
On the in-field functional testing of decode units in pipelined RISC processors. DFT 2014: 299-304
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Hakob Hakobyan, Paolo Rech, Matteo Sonza Reorda, Massimo Violante:
Early reliability evaluation of a biomédical system. IDT 2014: 45-50
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Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
A new solution to on-line detection of Control Flow Errors. IOLTS 2014: 105-110
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Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda:
Permanent faults on LIN networks: On-line test generation. IOLTS 2014: 176-181
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M. De Carvalho, Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
Fault injection in GPGPU cores to validate and debug robust parallel applications. IOLTS 2014: 210-211
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Anna Vaskova, A. Fabregat, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda:
Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques. LATW 2014: 1-6
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
Soft error effects analysis and mitigation in VLIW safety-critical applications. VLSI-SoC 2014: 1-6
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Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda:
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? VTS 2014: 1-2
2013
[j49]
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Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard:
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. 9(2): 253-263 (2013)
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Paolo Bernardi, Lyl M. Ciganda, Matteo Sonza Reorda, Said Hamdioui:
An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase. Asian Test Symposium 2013: 227-232
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Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda:
Reliability analysis reloaded: how will we survive? DATE 2013: 358-367
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Paolo Bernardi, Michele Bonazza, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
On-line functionally untestable fault identification in embedded processor cores. DATE 2013: 1462-1467
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Stefano Di Carlo, Ernesto Sánchez, Matteo Sonza Reorda:
On the on-line functional test of the Reorder Buffer memory in superscalar processors. DDECS 2013: 36-41
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Matteo Sonza Reorda, Luca Sterpone, Anees Ullah:
An error-detection and self-repairing method for dynamically and partially reconfigurable systems. ETS 2013: 1-7
[c268]
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Paolo Bernardi, D. Boyang, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan:
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors. IDT 2013: 1-6
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Marco Desogus, Matteo Sonza Reorda, Luca Sterpone, V. A. Avantaggiati, G. Audisio, Marco Sabatini:
Validation and robustness assessment of an automotive system. IDT 2013: 1-6
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
On the evaluation of soft-errors detection techniques for GPGPUs. IDT 2013: 1-6
[c265]
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Anna Vaskova, Marta Portela-García, Matteo Sonza Reorda:
Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus. IOLTS 2013: 13-18
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Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
Increasing fault coverage during functional test in the operational phase. IOLTS 2013: 43-48
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Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
Exploiting the debug interface to support on-line test of control flow errors. IOLTS 2013: 98-103
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D. Changdao, Mariagrazia Graziano, Ernesto Sánchez, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan:
On the functional test of the BTB logic in pipelined and superscalar processors. LATW 2013: 1-6
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Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan:
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors. MTV 2013: 52-57
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the development of diagnostic test programs for VLIW processors. VLSI-SoC 2013: 84-89
[c259]
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
Partition-Based Faults Diagnosis of a VLIW Processor. VLSI-SoC (Selected Papers) 2013: 208-226
2012
[j48]
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Michelangelo Grosso, Wilson-Javier Pérez-Holguín, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, Jaime Velasco-Medina:
Software-Based Testing for System Peripherals. J. Electron. Test. 28(2): 189-200 (2012)
[j47]
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Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil:
On the use of embedded debug features for permanent and transient fault resilience in microprocessors. Microprocess. Microsystems 36(5): 334-343 (2012)
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Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka:
Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium 2012: 167-172
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
A new SBST algorithm for testing the register file of VLIW processors. DATE 2012: 412-417
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Matteo Sonza Reorda:
On-line test of embedded systems: Which role for functional test? DDECS 2012: 1
[c255]
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Paolo Bernardi, Lyl M. Ciganda, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
A SBST strategy to test microprocessors' Branch Target Buffer. DDECS 2012: 306-311
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the development of Software-Based Self-Test methods for VLIW processors. DFT 2012: 25-30
[c253]
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Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella:
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125
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Paolo Bernardi, Lyl M. Ciganda, Mauricio de Carvalho, Michelangelo Grosso, Jorge Luis Lagos-Benites, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
On-line software-based self-test of the Address Calculation Unit in RISC processors. ETS 2012: 1-6
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Michele Riga, Ernesto Sánchez, Matteo Sonza Reorda:
On the functional test of L2 caches. IOLTS 2012: 84-90
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Luca Sterpone, Davide Sabena, Matteo Sonza Reorda:
A New Fault Injection Approach for Testing Network-on-Chips. PDP 2012: 530-535
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Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the optimized generation of Software-Based Self-Test programs for VLIW processors. VLSI-SoC 2012: 129-134
[c248]
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Davide Sabena, Luca Sterpone, Matteo Sonza Reorda:
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors. VLSI-SoC (Selected Papers) 2012: 162-180
[i3]
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Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda:
Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012)
2011
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Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Luciano Bonaria, Roberto Losco, Luciano Marcigot, Maurizio Straiotto:
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test. J. Electron. Test. 27(3): 389-402 (2011)
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Michelangelo Grosso, Wilson-Javier Pérez-Holguín, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, Jaime Velasco-Medina:
Functional Verification of DMA Controllers. J. Electron. Test. 27(4): 505-516 (2011)
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Massimo Violante, Cristina Meinhardt, Ricardo Reis, Matteo Sonza Reorda:
A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. IEEE Trans. Ind. Electron. 58(7): 2617-2626 (2011)
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Paolo Bernardi, Matteo Sonza Reorda:
A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing. Asian Test Symposium 2011: 142-147
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Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda:
Fault injection analysis of transient faults in clustered VLIW processors. DDECS 2011: 207-212
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Mauricio de Carvalho, Paolo Bernardi, Matteo Sonza Reorda, Nicola Campanelli, Tamas Kerekes, Davide Appello, Mario Barone, Vincenzo Tancorre, Marco Terzi:
Optimized embedded memory diagnosis. DDECS 2011: 347-352
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Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch:
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT 2011: 226-232
[c243]
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Jorge Luis Lagos-Benites, Michelangelo Grosso, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini, V. A. Avantaggiati:
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems. DFT 2011: 391-398
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Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda:
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS 2011: 153-158
[c241]
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Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini:
A Low-Cost Emulation System for Fast Co-verification and Debug. ETS 2011: 212
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Paolo Bernardi, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda:
An effective methodology for on-line testing of embedded microprocessors. IOLTS 2011: 270-275
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Ernesto Sánchez, Matteo Sonza Reorda:
On the functional test of MESI controllers. LATW 2011: 1-6
[c238]
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Wilson J. Pérez H., Ernesto Sánchez, Matteo Sonza Reorda, Alberto Tonda, Jaime Velasco-Medina:
Functional test generation for the pLRU replacement mechanism of embedded cache memories. LATW 2011: 1-6
[c237]
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Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda:
On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture. VLSI-SoC (Selected Papers) 2011: 110-123
[c236]
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Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda:
On the functional test of Branch Prediction Units based on Branch History Table. VLSI-SoC 2011: 278-283
2010
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Mihalis Psarakis, Dimitris Gizopoulos, Edgar E. Sánchez, Matteo Sonza Reorda:
Microprocessor Software-Based Self-Testing. IEEE Des. Test Comput. 27(3): 4-19 (2010)
[j42]
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Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug. IET Comput. Digit. Tech. 4(2): 104-113 (2010)
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Paolo Bernardi, Letícia Maria Veiras Bolzani Poehls, Michelangelo Grosso, Matteo Sonza Reorda:
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs. IEEE Trans. Dependable Secur. Comput. 7(4): 439-445 (2010)
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Nicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone:
Cumulative embedded memory failure bitmap display & analysis. DDECS 2010: 255-260
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Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda:
A hardware accelerated framework for the generation of design validation programs for SMT processors. DDECS 2010: 289-292
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Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An Exact and Efficient Critical Path Tracing Algorithm. DELTA 2010: 164-169
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Michelangelo Grosso, Wilson J. Pérez H., Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Jaime Velasco-Medina:
A software-based self-test methodology for system peripherals. ETS 2010: 195-200
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Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda:
An adaptive tester architecture for volume diagnosis. ETS 2010: 227-232
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Paolo Rech, Michelangelo Grosso, Fabio Melchiori, Domenico Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda:
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. IOLTS 2010: 29-34
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Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena:
An on-line fault detection technique based on embedded debug features. IOLTS 2010: 167-172
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M. Di Marzio, Michelangelo Grosso, Matteo Sonza Reorda, Luca Sterpone, G. Audisio, Marco Sabatini:
A novel scalable and reconfigurable emulation platform for embedded systems verification. ISCAS 2010: 865-868
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Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Y. Zhang:
A programmable BIST for DRAM testing and diagnosis. ITC 2010: 447-456
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Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Maurizio Straiotto, Luciano Bonaria:
A tester architecture suitable for MEMS calibration and testing. ITC 2010: 806
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Michelangelo Grosso, Wilson J. Pérez H., Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda, Jaime Velasco-Medina:
Functional test generation for DMA controllers. LATW 2010: 1-6
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Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda:
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization. MTV 2010: 29-34
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Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda:
Generating power-hungry test programs for power-aware validation of pipelined processors. SBCCI 2010: 61-66

2000 – 2009

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What is the meaning of the colors in the publication lists?

2009
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Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda:
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices. IEEE Des. Test Comput. 26(2): 52-63 (2009)
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Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1654-1659 (2009)
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Wilson J. Pérez H., Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda:
On the Generation of Functional Test Programs for the Cache Replacement Logic. Asian Test Symposium 2009: 418-423
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Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. DATE 2009: 352-357
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Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS 2009: 50-55
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Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda:
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. DDECS 2009: 258-263
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Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. DFT 2009: 254-262
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Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda:
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. ETS 2009: 93-98
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Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Davide Appello:
Evaluating Alpha-induced soft errors in embedded microprocessors. IOLTS 2009: 69-74
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Michelangelo Grosso, Matteo Sonza Reorda:
Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores. IOLTS 2009: 95-100
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Cristina Meinhardt, Ricardo Reis, Massimo Violante, Matteo Sonza Reorda:
Recovery scheme for hardening system on programmable chips. LATW 2009: 1-6
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Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Design validation of multithreaded architectures using concurrent threads evolution. SBCCI 2009
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Davide Appello, Paolo Bernardi, Simone Gerardin, Michelangelo Grosso, Alessandro Paccagnella, Paolo Rech, Matteo Sonza Reorda:
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study. VTS 2009: 276-281
2008
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Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante:
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. J. Electron. Test. 24(1-3): 45-56 (2008)
[j37]
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Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 570-574 (2008)
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Paolo Bernardi, Matteo Sonza Reorda:
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. DATE 2008: 194-199
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Wilson J. Pérez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs. DDECS 2008: 339-344
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Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez, Matteo Sonza Reorda:
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. EvoWorkshops 2008: 224-234
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Wilson J. Pérez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs. IOLTS 2008: 143-148
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Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores. MTV 2008: 103-108
[c206]
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Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. VTS 2008: 389-394
2007
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Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro:
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electron. Test. 23(1): 47-54 (2007)
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Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
A System-layer Infrastructure for SoC Diagnosis. J. Electron. Test. 23(5): 389-404 (2007)
[c205]
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Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor. DATE 2007: 1158-1163
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Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda:
Extended Fault Detection Techniques for Systems-on-Chip. DDECS 2007: 55-60
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Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante:
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT 2007: 96-104
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Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. DFT 2007: 291-300
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Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Safety Evaluation of NanoFabrics. DFT 2007: 418-426
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Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. ETS 2007: 179-184
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Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda:
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. ACM Great Lakes Symposium on VLSI 2007: 411-416
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Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda:
A Hybrid Approach to Fault Detection and Correction in SoCs. IOLTS 2007: 107-112
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Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante:
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196
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Letícia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. IOLTS 2007: 265-270
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Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction. MTV 2007: 71-76
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W. Di Palma, Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
Automotive Microcontroller End-of-Line Test via Software-Based Methodologies. MTV 2007: 77-82
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Letícia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda:
An optimized hybrid approach to provide fault detection and correction in SoCs. SBCCI 2007: 342-347
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Letícia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda:
A software-based methodology for the generation of peripheral test sets based on high-level descriptions. SBCCI 2007: 348-353
[i2]
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Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda:
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. CoRR abs/0710.4688 (2007)
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Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. CoRR abs/0710.4840 (2007)
2006
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Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Software-Implemented Hardware Fault Tolerance. Springer 2006, ISBN 978-0-387-26060-0, pp. I-XI, 1-224
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Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante:
Early, Accurate Dependability Analysis of CAN-Based Networked Systems. IEEE Des. Test Comput. 23(1): 38-45 (2006)
[j33]
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Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda:
System-in-Package Testing: Problems and Solutions. IEEE Des. Test Comput. 23(3): 203-211 (2006)
[j32]
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Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Efficient Techniques for Automatic Verification-Oriented Test Set Optimization. Int. J. Parallel Program. 34(1): 93-109 (2006)
[j31]
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Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante:
A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006)
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Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis. IEEE Congress on Evolutionary Computation 2006: 859-864
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Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. DATE 2006: 412-417
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Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante:
Online hardening of programs against SEUs and SETs. DFT 2006: 280-290
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Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena:
Fault Injection-based Reliability Evaluation of SoPCs. ETS 2006: 75-82
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Matteo Sonza Reorda, Massimo Violante:
Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. IOLTS 2006: 229-234
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Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Embedded Memory Diagnosis: An Industrial Workflow. ITC 2006: 1-9
[c185]
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Marta Portela-García, Luca Sterpone, Celia López-Ongil, Matteo Sonza Reorda, Massimo Violante:
A Fault Injection Environment for SoPC's Embedded Microprocessors. LATW 2006: 68-73
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Massimiliano Schillaci, Matteo Sonza Reorda, Massimo Violante:
A New Approach to Cope with Single Event Upsets in Processor-based Systems. LATW 2006: 145-150
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Paolo Bernardi, Letícia Maria Veiras Bolzani, Alberto Manzone, Massimo Osella, Massimo Violante, Matteo Sonza Reorda:
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV 2006: 3-8
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Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
On the Automation of the Test Flow of Complex SoCs. VTS 2006: 166-171
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Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. VTS 2006: 386-391
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Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek:
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, ISBN 1-4244-0185-2 [contents]
2005
[c180]
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Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda:
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. DATE 2005: 1290-1295
[c179]
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Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453
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Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors. DFT 2005: 494-504
[c177]
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Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante:
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58
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Matteo Sonza Reorda, Luca Sterpone, Massimo Violante:
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. ETS 2005: 136-141
[c175]
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Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs. ETS 2005: 202-207
[c174]
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Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Automatic Completion and Refinement of Verification Sets for Microprocessor Cores. EvoWorkshops 2005: 205-214
[c173]
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Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante:
New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO 2005: 2193-2194
[c172]
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Matteo Sonza Reorda, Luca Sterpone, Massimo Violante:
Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS 2005: 54-59
[c171]
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Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda:
Integrating BIST Techniques for On-Line SoC Testing. IOLTS 2005: 235-240
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Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. MTV 2005: 37-41
[c169]
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Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. MTV 2005: 55-62
[c168]
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Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
Automatic generation of test sets for SBST of microprocessor IP cores. SBCCI 2005: 74-79
2004
[j30]
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Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Automatic Test Program Generation: A Case Study. IEEE Des. Test Comput. 21(2): 102-109 (2004)
[j29]
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Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda:
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. J. Electron. Test. 20(1): 79-87 (2004)
[j28]
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Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Code Generation for Functional Validation of Pipelined Microprocessors. J. Electron. Test. 20(3): 269-278 (2004)
[j27]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A New Approach to Software-Implemented Fault Tolerance. J. Electron. Test. 20(4): 433-437 (2004)
[j26]
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Cecilia Metra, Matteo Sonza Reorda:
Guest Editorial. J. Electron. Test. 20(5): 463 (2004)
[j25]
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Matteo Sonza Reorda, Massimo Violante:
A New Approach to the Analysis of Single Event Transients in VLSI Circuits. J. Electron. Test. 20(5): 511-521 (2004)
[j24]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Evolutionary Simulation-Based Validation. Int. J. Artif. Intell. Tools 13(4): 897-916 (2004)
[j23]
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Matteo Sonza Reorda, Massimo Violante:
Efficient analysis of single event transients. J. Syst. Archit. 50(5): 239-246 (2004)
[c167]
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Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
Automatic Generation of Validation Stimuli for Application-Specific Processors. DATE 2004: 188-193
[c166]
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Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. DATE 2004: 228-233
[c165]
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M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin:
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. DATE 2004: 584-589
[c164]
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Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco:
Coupling Different Methodologies to Validate Obsolete Microprocessors. DFT 2004: 250-255
[c163]
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Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an I-IP for In-Field SOC Test. DFT 2004: 404-412
[c162]
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Matteo Sonza Reorda, Massimo Violante:
On-Line Analysis and Perturbation of CAN Networks. DFT 2004: 424-432
[c161]
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Fulvio Corno, Julio Pérez Acle, Mattia Ramasso, Matteo Sonza Reorda, Massimo Violante:
Validation of the dependability of CAN-based networked systems. HLDVT 2004: 161-164
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Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante:
Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88
[c159]
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Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante:
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS 2004: 115-120
[c158]
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Fulvio Corno, Matteo Sonza Reorda, Simonluca Tosato, F. Esposito:
Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems. ITC 2004: 1332-1339
[c157]
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W. Lindsay, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Automatic Test Programs Generation Driven by Internal Performance Counters. MTV 2004: 8-13
[c156]
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Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda:
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. MTV 2004: 22-27
[c155]
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Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante:
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. SBCCI 2004: 71-75
2003
[j22]
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Cecilia Metra, Matteo Sonza Reorda:
Guest Editorial. J. Electron. Test. 19(5): 499 (2003)
[j21]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. J. Electron. Test. 19(5): 577-584 (2003)
[j20]
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Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
New techniques for efficiently assessing reliability of SOCs. Microelectron. J. 34(1): 53-61 (2003)
[c154]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. DATE 2003: 10602-10607
[c153]
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Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. DATE 2003: 10720-10725
[c152]
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Fully Automatic Test Program Generation for Microprocessor Cores. DATE 2003: 11006-11011
[c151]
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Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343
[c150]
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Julio Pérez, Matteo Sonza Reorda, Massimo Violante:
Dependability Analysis of CAN Networks: An Emulation-Based Approach. DFT 2003: 537-
[c149]
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Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Soft-Error Detection Using Control Flow Assertions. DFT 2003: 581-588
[c148]
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Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda:
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores. ETFA (1) 2003: 417-421
[c147]
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Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda:
Code generation for functional validation of pipelined microprocessors. ETW 2003: 113-118
[c146]
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Matteo Sonza Reorda, Massimo Violante:
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. FPL 2003: 616-626
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Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
High-level test generation for hardware testing and software validation. HLDVT 2003: 143-148
[c144]
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Matteo Sonza Reorda, Massimo Violante:
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. IOLTS 2003: 101-105
[c143]
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Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori:
Analyzing SEU Effects in SRAM-based FPGAs. IOLTS 2003: 119-123
[c142]
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Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
An RT-level Concurrent Error Detection Technique for Data Dominated Systems. IOLTS 2003: 159
[c141]
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Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Letícia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda:
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? IOLTS 2003: 163
[c140]
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Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante:
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. ITC 2003: 379-385
[c139]
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Automatic Test Program Generation for Pipeline Processors. SAC 2003: 736-740
[c138]
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Julio Pérez, Matteo Sonza Reorda, Massimo Violante:
Accurate Dependability Analysis of CAN-Based Networked Systems. SBCCI 2003: 337-342
2002
[j19]
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Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electron. Test. 18(3): 261-271 (2002)
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
Initializability analysis of synchronous sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7(2): 249-264 (2002)
[c137]
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Evolutionary Test Program Induction for Microprocessor Design Verification. Asian Test Symposium 2002: 368-373
[c136]
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Efficient machine-code test-program induction. IEEE Congress on Evolutionary Computation 2002: 1486-1491
[c135]
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Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López:
New Techniques for Speeding-Up Fault-Injection Campaigns. DATE 2002: 847-852
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Matteo Sonza Reorda, Massimo Violante:
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. DFT 2002: 263-274
[c133]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A New Functional Fault Model for FPGA Application-Oriented Testing. DFT 2002: 372-380
[c132]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Evolutionary Techniques for Minimizing Test Signals Application Time. EvoWorkshops 2002: 183-189
[c131]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. FPL 2002: 607-615
[c130]
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Matteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis:
A hierarchical approach for designing dependable systems. HLDVT 2002: 63-68
[c129]
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Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
High-level and hierarchical test sequence generation. HLDVT 2002: 169-174
[c128]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Analysis of SEU Effects in a Pipelined Processor. IOLTW 2002: 112-116
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Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. IOLTW 2002: 193
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Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda:
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. IOLTW 2002: 206-210
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Automatic Test Program Generation from RT-Level Microprocessor Descriptions. ISQED 2002: 120-125
[c124]
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Matteo Sonza Reorda:
An Overview Covering the Different Solutions: from radiation testing to Software Fault Injection. LATW 2002: 2
[c123]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A New Approach to Software-Implemented Fault Tolerance. LATW 2002: 22-25
[c122]
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Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda:
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. MTDT 2002: 12-16
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
An evolutionary algorithm for reducing integrated-circuit test application time. SAC 2002: 608-612
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Reducing Test Application Time through Interleaved Scan. SBCCI 2002: 89-94
[c119]
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Bogdan Nicolescu, Raoul Velazco, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante:
A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks. SBCCI 2002: 101-108
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Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López:
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. VTS 2002: 229-236
2001
[c117]
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Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. Asian Test Symposium 2001: 97-102
[c116]
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Effective Techniques for High-Level ATPG. Asian Test Symposium 2001: 225-
[c115]
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Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304-
[c114]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
On the test of microprocessor IP cores. DATE 2001: 209-213
[c113]
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Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
System safety through automatic high-level code transformations: an experimental evaluation. DATE 2001: 297-301
[c112]
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Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258
[c111]
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
ARPIA: A High-Level Evolutionary Test Signal Generator. EvoWorkshops 2001: 298-306
[c110]
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Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502
[c109]
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Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13
[c108]
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Bogdan Nicolescu, Raoul Velazco, Matteo Sonza Reorda:
Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study. IOLTW 2001: 172-177
[c107]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Evolving effective CA/CSTP: BIST architectures for sequential circuits. SAC 2001: 345-350
[c106]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano:
A Source-to-Source Compiler for Generating Dependable Software. SCAM 2001: 35-44
[c105]
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Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante:
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371-
2000
[j17]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
RT-Level ITC'99 Benchmarks and First ATPG Results. IEEE Des. Test Comput. 17(3): 44-53 (2000)
[c104]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Exploiting the Selfish Gene algorithm for evolving hardware cellular automata. CEC 2000: 1401-1406
[c103]
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Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Automatic test bench generation for simulation-based validation. CODES 2000: 136-140
[c102]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti:
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. DATE 2000: 385-389
[c101]
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Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590
[c100]
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Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante:
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. DFT 2000: 257-265
[c99]
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Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
System-level test bench generation in a co-design framework. ETW 2000: 25-30
[c98]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
CA-CSTP: a new BIST architecture for sequential circuits. ETW 2000: 167-172
[c97]
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Automatic Validation of Protocol Interfaces Described in VHDL. EvoWorkshops 2000: 205-213
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Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Prediction of Power Requirements for High-Speed Circuits. EvoWorkshops 2000: 247-254
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Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
An RT-level fault model with high gate level correlation. HLDVT 2000: 3-8
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Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
Behavioral-level test vector generation for system-on-chip designs. HLDVT 2000: 21-26
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Evolving Cellular Automata for Self-Testing Hardware. ICES 2000: 31-40
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
A genetic algorithm-based system for generating test programs for microprocessor IP cores. ICTAI 2000: 195-198
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata. IJCNN (6) 2000: 577-584
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Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco:
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. IOLTW 2000: 17-
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B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
New Techniques for Accelerating Fault Injection in VHDL Descriptions. IOLTW 2000: 61-66
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
An improved cellular automata-based BIST architecture for sequential circuits. ISCAS 2000: 76-79
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Ph. Cheynet, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Hardening the Software with Respect to Transient Errors: a Method and Experimental Results. LATW 2000: 36-40
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Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante:
Early Power Estimation for System-on-Chip Designs. PATMOS 2000: 108-117
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B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Speeding-Up Fault Injection Campaigns in VHDL Models. SAFECOMP 2000: 27-36
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Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
Low Power BIST via Non-Linear Hybrid Cellular Automata. VTS 2000: 29-34
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
High-Level Observability for Effective High-Level ATPG. VTS 2000: 411-416

1990 – 1999

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1999
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Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Fault Injection for Embedded Microprocessor-based Systems. J. Univers. Comput. Sci. 5(10): 693-711 (1999)
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Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante:
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 191-202 (1999)
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Verifying the equivalence of sequential circuits with genetic algorithms. CEC 1999: 1293-1298
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Optimizing deceptive functions with the SG-Clans algorithm. CEC 1999: 2190-2198
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms. DATE 1999: 754-755
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Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante:
Soft-Error Detection through Software Fault-Tolerance Techniques. DFT 1999: 210-218
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Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante:
Optimal Vector Selection for Low Power BIST. DFT 1999: 219-226
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Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A new BIST architecture for low power circuits. ETW 1999: 160-164
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Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Test Pattern Generation Under Low Power Constraints. EvoWorkshops 1999: 162-170
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms. EvoWorkshops 1999: 182-192
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Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI 1999: 350-353
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Simulation-based sequential equivalence checking of RTL VHDL. ICECS 1999: 351-354
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Matteo Sonza Reorda:
High-level ATPG: a real topic or an academic amusement? ITC 1999: 1118
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Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda:
FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems. SAFECOMP 1999: 323-335
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Maurizio Rebaudengo, Matteo Sonza Reorda:
Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . VTS 1999: 452-459
1998
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Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Integrating Online and Offline Testing of a Switching Memory. IEEE Des. Test Comput. 15(1): 63-70 (1998)
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Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
The General Product Machine: a New Model for Symbolic FSM Traversal. Formal Methods Syst. Des. 12(3): 267-289 (1998)
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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
EXFI: a low-cost fault injection system for embedded microprocessor-based boards. ACM Trans. Design Autom. Electr. Syst. 3(4): 626-634 (1998)
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Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. DATE 1998: 570-576
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante:
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE 1998: 670-677
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Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera:
An Integrated HW and SW Fault Injection Environment for Real-Time Systems. DFT 1998: 117-
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Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti:
A System for Evaluating On-Line Testability at the RT-level. DFT 1998: 284-291
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
VEGA: a verification tool based on genetic algorithms. ICCD 1998: 321-326
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Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti:
Enhancing topological ATPG with high-level information and symbolic techniques. ICCD 1998: 504-509
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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A fault injection environment for microprocessor-based boards. ITC 1998: 768-773
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Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
The selfish gene algorithm: a new evolutionary optimization strategy. SAC 1998: 349-355
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Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda:
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. VTS 1998: 424-429
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A Test Pattern Generation Methodology for Low-Power Consumption. VTS 1998: 453-459
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Maurizio Rebaudengo, Matteo Sonza Reorda:
The training environment for the course on microprocessor systems at the Politecnico di Torino. WCAE@ISCA 1998: 8
1997
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Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Guaranteeing Testability in Re-encoding for Low Power. Asian Test Symposium 1997: 30-35
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. Asian Test Symposium 1997: 56-61
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium 1997: 68-73
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Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero:
Simulation-based verification of network protocols performance. CHARME 1997: 236-251
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
New static compaction techniques of test sequences for sequential circuits. ED&TC 1997: 37-43
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Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Hybrid symbolic-explicit techniques for the graph coloring problem. ED&TC 1997: 422-426
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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar:
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC 1997: 560-565
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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217
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F. Bianchi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Roberto Ansaloni:
Boolean Function Manipulation on a Parallel System Using BDDs. HPCN Europe 1997: 916-928
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. ICCD 1997: 381-386
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S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. ICTAI 1997: 133-
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Testability Analysis and ATPG on Behavioral RT-Level VHDL. ITC 1997: 753-759
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. SAC 1997: 228-232
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Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Cellular automata for deterministic sequential test pattern generation. VTS 1997: 60-67
1996
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Circular Self-Test Path for FSMs. IEEE Des. Test Comput. 13(4): 50-60 (1996)
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Maurizio Rebaudengo, Matteo Sonza Reorda:
GALLO: a genetic algorithm for floorplan area optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 943-951 (1996)
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 991-1000 (1996)
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, R. Mosca:
Advanced Techniques for GA-based sequential ATPGs. ED&TC 1996: 375-379
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study. ED&TC 1996: 610
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore:
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. EDCC 1996: 190-202
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Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda:
Fault tolerant and BIST design of a FIFO cell. EURO-DAC 1996: 233-238
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Paolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo:
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment. EURO-DAC 1996: 536-541
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. HPCN Europe 1996: 454-459
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Gavril Godza, Maurizio Rebaudengo, Matteo Sonza Reorda:
Using Parallel Genetic Algorithms for Solving the Min-Cut Problem. HPCN Europe 1996: 985-986
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Maurizio Rebaudengo, Matteo Sonza Reorda:
A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture. HPCN Europe 1996: 987-988
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits. ICTAI 1996: 10-16
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. ITC 1996: 39-47
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. ITC 1996: 558-564
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. PPSN 1996: 792-800
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Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Scan insertion criteria for low design impact. VTS 1996: 26-31
1995
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Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina:
Industrial BIST of Embedded RAMs. IEEE Des. Test Comput. 12(3): 86-95 (1995)
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
GARDA: a diagnostic ATPG for large synchronous sequential circuits. ED&TC 1995: 267-273
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Using symbolic techniques to find the maximum clique in very large sparse graphs. ED&TC 1995: 320-324
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Pier Paolo Delsanto, S. Biancotto, Marco Scalerandi, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting massively parallel architectures for the solution of diffusion and propagation problems. HPCN Europe 1995: 1-6
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva:
A PVM tool for automatic test generation on parallel and distributed systems. HPCN Europe 1995: 39-44
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Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Testing a Switching Memory in a Telcommunication System. ITC 1995: 947-956
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Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda:
An improved data parallel algorithm for Boolean function manipulation using BDDs. PDP 1995: 33-41
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Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva:
A portable ATPG tool for parallel and distributed systems. VTS 1995: 29-34
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus:
Improving topological ATPG with symbolic techniques. VTS 1995: 338-343
1994
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Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda:
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. EDAC-ETC-EUROASIC 1994: 46-50
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Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda:
An experimental analysis of the effectiveness of the circular self-test path technique. EURO-DAC 1994: 246-251
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Maurizio Rebaudengo, Matteo Sonza Reorda:
Floorplan area optimization using genetic algorithms. Great Lakes Symposium on VLSI 1994: 22-25
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Matteo Sonza Reorda, Maurizio Rebaudengo:
A Genetic Algorithm for Floorplan Area Optimization. International Conference on Evolutionary Computation 1994: 93-96
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Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva:
GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. ICTAI 1994: 411-417
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Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. ITC 1994: 240-249
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Making the Circular Self-Test Path Technique Effective for Real Circuits. ITC 1994: 949-957
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Gianpiero Cabodi, Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda:
A BDD Package For A Massively Parallel SIMD Architecture. PDP 1994: 212-219
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Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina:
An industrial experience in the built-in self test of embedded RAMs. VTS 1994: 306-311
1993
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Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
An approach to sequential circuit diagnosis based on formal verification techniques. J. Electron. Test. 4(1): 11-17 (1993)
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Gianpiero Balboni, Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda:
A Parallel System for Test Pattern Generation. Parallel Comput. 19(2): 177-185 (1993)
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Maurizio Rebaudengo, Matteo Sonza Reorda:
An experimental analysis of the effects of migration in parallel genetic algorithms. PDP 1993: 232-238
1992
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Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda:
A New Model for Improving symbolic Product Machine Traversal. DAC 1992: 614-619
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Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Cross-fertilizing FSM verification techniques and sequential diagnosis. EURO-DAC 1992: 306-311
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Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Sequential Circuit Diagnosis Based on Formal Verification Techniques. ITC 1992: 187-196
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Paolo Camurati, Fulvio Corno, Fulvio Prinetto, Matteo Sonza Reorda:
A simulation-based approach to test pattern generation for synchronous sequential circuits. VTS 1992: 263-267
1991
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Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
TPDL: Extended Temporal Profile Description Language. Softw. Pract. Exp. 21(4): 355-374 (1991)
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Antonio Lioy, Enrico Macii, Angelo Raffaele Meo, Matteo Sonza Reorda:
An algebraic approach to test generation for sequential circuits. Great Lakes Symposium on VLSI 1991: 115-120
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Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
Proving finite state machines correct with an automaton-based method. Great Lakes Symposium on VLSI 1991: 255-258
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Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda:
Fast Differential Fault Simulation by Dynamic Fault Ordering. ICCD 1991: 60-63
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Gianpiero Balboni, Gianpiero Cabodi, Silvano Gai, D. Sismondi, Matteo Sonza Reorda:
A parallel system for test pattern generation. SPDP 1991: 708-715
1990
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Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
Exact probabilistic testability measures for multi-output circuits. J. Electron. Test. 1(3): 229-234 (1990)
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Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Assessing the diagnostic power of test pattern sets. Microprocessing and Microprogramming 30(1-5): 413-419 (1990)
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Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda:
A transputer-based gate-level fault simulator. Microprocessing and Microprogramming 30(1-5): 529-534 (1990)
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Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
The Use of Model Checking in ATPG for Sequential Circuits. CAV 1990: 86-95
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Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
Model Checking and Graph Theory in Sequential ATPG. CAV (DIMACS/AMS volume) 1990: 505-518
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Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Diagnosis oriented test pattern generation. EURO-DAC 1990: 470-474
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Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda:
A diagnostic test pattern generation algorithm. ITC 1990: 52-58

1980 – 1989

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1989
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Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
Expressing logical and temporal conditions in simulation environments: TPDL^*. Microprocessing and Microprogramming 26(4): 241-252 (1989)
1988
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Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
Random testability analysis: comparing and evaluating existing approaches. ICCD 1988: 70-73

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