Welcome to my GitHub profile! Explore my projects, contributions, and more. I'm passionate about Data Science with innovative Ideas and Web Dev. Let's connect and collaborate!
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Updated
Apr 14, 2026
Welcome to my GitHub profile! Explore my projects, contributions, and more. I'm passionate about Data Science with innovative Ideas and Web Dev. Let's connect and collaborate!
Custom Yocto Linux bring-up on Alinx VD100 (XCVE2302). v1: SD/Ethernet/USB. v2: I2C/GPIO/PL LED/kernel driver. v3: XRT + AIE-ML pipeline + Ethereum. No VCK190. No MATLAB. AMD EDF 25.11 / Scarthgap.
Yocto Scarthgap meta layer for VD100 (XCVE2302) — XRT 2025.2, zocl, AIE-ML v2 pipeline. Fixes undocumented BOOT.BIN CDO gap that leaves all AIE tiles clock-gated under Linux. Submodule of versal-ai-edge-vd100-linux.
PS userspace XRT application for the VD100 MA Crossover AIE-ML v2 pipeline. Drives mm2s/s2mm HLS kernels and mygraph via XRT 2025.2 on XCVE2302. Includes golden test vector validation and XRT lifecycle performance analysis.
Live Binance WebSocket feed → MA crossover signal → Ethereum smart contract on Versal AI Edge XCVE2302 (VD100). SW mode: 1440ns on A72. AIE-ML v2 XRT pipeline integrated and benchmarked. XRT architectural findings documented.
First documented end-to-end PL + AIE-ML + PS pipeline on Versal AI Edge XCVE2302 (VD100). MA crossover trading signal via HLS DMA + AIE graph + XRT host app. No VCK190. No MATLAB. Ethereum audit log on Hardhat.
AIE-ML v2 moving average crossover kernel for VD100 (XCVE2302). Dual MA (fast 10 / slow 50 period), BUY/SELL/HOLD signal. 56 int32 samples/iteration via HLS DMA. Used in vd100-aie-pipeline. Vitis 2025.2.
Post-link Vitis pipeline platform for VD100 (XCVE2302). Add new HLS or AIE kernels to the existing Vitis region without starting a new Vivado project. Built from vd100_ma_system_project post-link XSA.
Vitis 2025.2 system project for VD100 (XCVE2302) — v++ link + package for AIE-ML v2 + HLS kernel integration. Produces aie.xclbin and BOOT.BIN CDO artifacts. Reusable: swap AIE kernel or add HLS kernels without new project.
Vivado 2025.2 block design for VD100 (XCVE2302) — CIPS, NoC, AIE-ML v2, AXI interrupt controller, MyLEDIP. Reusable hardware platform for Vitis AIE kernel projects. Exports XSA for vd100_platform. No VCK190 required.
A real-time business management dashboard built with JavaScript, Supabase, and Vercel.
Custom Yocto layer for the Alinx VD100 (Versal AI Edge Series XCVE2302-SFVA784-1LP-E-S). Adds AXI-lite PL LED kernel driver (myledip) via M_AXI_FPD — PS LED via libgpiod, PL LED via /dev/plledip. Custom AXI-lite IP (MyLEDIP), Linux platform driver, C++ demo. AMD EDF 25.11 / Scarthgap.
VS Code extension for Xilinx embedded debugging. Features XSDB-driven board bring-up, FPGA programming, and GDB/LLDB support for Zynq, ZynqMP, Versal, and MicroBlaze targets.
Custom Yocto layer for the Alinx VD100 (XCVE2302-SFVA784-1LP-E-S). SD boot, Ethernet, USB, SSH, I2C, LM75, EEPROM, sysmon, and PS LED via libgpiod. AMD EDF 25.11 / Scarthgap. No VCK190 — accessible Versal bring-up on a $1,285 board.
Reference architecture for FPGA-accelerated multi-agent reasoning on AMD Versal AI Core (VCK190). Safety-gated parallel inference lanes with reservoir computing and feedforward neural classification.
AXI 1G Ethernet ref designs for the Opsero Ethernet FMC Max (OP080)
CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
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