vitis
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This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
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Jan 8, 2024 - C
Error detection enabled tau-NAF conversion on Koblitz Curves
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May 12, 2023 - C
example of using iio to stream data from AD9361 with a coax cable loopback
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Apr 14, 2024 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
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Dec 3, 2023 - C
CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy
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Jul 20, 2024 - C
A TFTP server running on Zynq-7000
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May 15, 2024 - C
FPGA-driven CNC / pen-plotter control system built around the AMD/Xilinx Zynq-7000 ZedBoard. The machine uses a ballpoint pen as its toolhead and draws 2D paths on paper by coordinating X/Y motion and pen lift on the Z axis.
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Apr 19, 2026 - C
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Dec 24, 2022 - C
Example workflow project for firmware development in Vitis.
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Feb 19, 2023 - C
Baremetal C application that displays encoder values on a serial interface, starting from a Vivado block design and transitioning to a Vitis application.
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Jun 11, 2024 - C
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