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written in SystemVerilog
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
RSD: RISC-V Out-of-Order Superscalar Processor
Common SystemVerilog components
BaseJump STL: A Standard Template Library for SystemVerilog
The root repo for lowRISC project and FPGA demos.
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Test suite designed to check compliance with the SystemVerilog standard.
Tile based architecture designed for computing efficiency, scalability and generality
4 stage, in-order, compute RISC-V core based on the CV32E40P
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Generic Register Interface (contains various adapters)
The multi-core cluster of a PULP system.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Advanced Architecture Labs with CVA6
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
GPU for OENG1167 in Verilog HDL for DE10 series boards