LTC4367

100V Overvoltage,
Undervoltage and Reverse
Supply Protection Controller
FEATURES DESCRIPTION
n Wide Operating Voltage Range: 2.5V to 60V The LTC®4367 protects applications where power sup-
n Overvoltage Protection to 100V ply input voltages may be too high, too low or even
n Reverse Supply Protection to –40V negative. It does this by controlling the gate voltages of
n LTC4367: Blocks 50Hz and 60Hz AC Power a pair of external N-channel MOSFETs to ensure that the
n LTC4367: 32ms Recovery from Fault output stays within a safe operating range.The LTC4367
n LTC4367-1: Fast 500µs Recovery from Fault withstands voltages between –40V and 100V and has an
n No Input Capacitor or TVS Required for Most operating range of 2.5V to 60V, while consuming only
Applications 70µA in normal operation.
n Adjustable Undervoltage and Overvoltage Thresholds
Two comparator inputs allow configuration of the over-
n Controls Back-to-Back N-Channel MOSFETs voltage (OV) and undervoltage (UV) set points using an
n Low Operating Current: 70µA
external resistive divider. A shutdown pin provides external
n Low Shutdown Current: 5µA
control for enabling and disabling the MOSFETs as well
n 8-Pin MSOP and 3mm × 3mm DFN Packages
as placing the device in a low current shutdown state. A
n AEC-Q100 Qualified for Automotive Applications
fault output indicates that the GATE pin is pulling low when
the part is in shutdown or the input voltage is outside the
APPLICATIONS UV and OV set points.
n Portable Instrumentation The LTC4367 has a 32ms turn-on delay that debounces
n Industrial Automation live connections and blocks 50Hz to 60Hz AC power. For
n Automotive Surge (Load Dump) Protection fast recovery after faults, the LTC4367-1 has a reduced
n Network Equipment turn-on delay of 500µs.
All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION
24V Automotive Application with +100V, –40V Protection Load Protected from Reverse and Overvoltage at VIN
Si7942
VIN VOUT OV = 36V
24V 2A +70V
20V/DIV UV = 7V
VIN

GATE
VIN VOUT VALID WINDOW
464k
SHDN GND
VOUT VOUT
1500k
UV
–40V
121k FAULT 20V/DIV VIN
OV
OV = 36V
UV = 7V 29.4k GND
4367 TA01b
4367 TA01a 200ms/DIV

LTC4367
Rev. C

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LTC4367
ABSOLUTE MAXIMUM RATINGS
(Note 1, Note 2)
Supply Voltage Input Currents
VIN......................................................... –40V to 100V SHDN, UV ..........................................................–1mA
Input Voltages (Note 3) OV.......................................................................–1mA
UV, SHDN............................................... –0.3V to 80V Operating Ambient Temperature Range
OV............................................................. –0.3V to 5V LTC4367C................................................. 0°C to 70°C
VOUT....................................................... –0.3V to 80V LTC4367I..............................................–40°C to 85°C
Output Voltages LTC4367H........................................... –40°C to 125°C
FAULT...................................................... –0.3V to 80V Storage Temperature Range................... –65°C to 150°C
GATE (Note 4).......................................... –40V to 75V Lead Temperature (Soldering, 10sec)
for MSOP Only................................................... 300°C

PIN CONFIGURATION

TOP VIEW

VIN 1 8 GATE TOP VIEW

UV 2 7 VOUT VIN 1 8 GATE
9 UV 2 7 VOUT
OV 3 6 FAULT
OV 3 6 FAULT
GND 4 5 SHDN GND 4 5 SHDN
MS8 PACKAGE
DD PACKAGE 8-LEAD PLASTIC MSOP
8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 160°C/W

EXPOSED PAD (PIN 9) PCB GROUND CONNECTION OPTIONAL

TJMAX = 150°C, θJA = 43°C/W, θJC = 5.5°C/W

Rev. C

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 LTC4367
ORDER INFORMATION
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4367CDD#PBF LTC4367CDD#TRPBF LGTF 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC4367CDD-1#PBF LTC4367CDD-1#TRPBF LGVW 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC4367IDD#PBF LTC4367IDD#TRPBF LGTF 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4367IDD-1#PBF LTC4367IDD-1#TRPBF LGVW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4367HDD#PBF LTC4367HDD#TRPBF LGTF 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC4367HDD-1#PBF LTC4367HDD-1#TRPBF LGVW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC4367CMS8#PBF LTC4367CMS8#TRPBF LTGTD 8-Lead Plastic MSOP 0°C to 70°C
LTC4367CMS8-1#PBF LTC4367CMS8-1#TRPBF LTGVX 8-Lead Plastic MSOP 0°C to 70°C
LTC4367IMS8#PBF LTC4367IMS8#TRPBF LTGTD 8-Lead Plastic MSOP –40°C to 85°C
LTC4367IMS8-1#PBF LTC4367IMS8-1#TRPBF LTGVX 8-Lead Plastic MSOP –40°C to 85°C
LTC4367HMS8#PBF LTC4367HMS8#TRPBF LTGTD 8-Lead Plastic MSOP –40°C to 125°C
LTC4367HMS8-1#PBF LTC4367HMS8-1#TRPBF LTGVX 8-Lead Plastic MSOP –40°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC4367IDD#WPBF LTC4367IDD#WTRPBF LGTF 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4367IDD-1#WPBF LTC4367IDD-1#WTRPBF LGVW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4367HDD#WPBF LTC4367HDD#WTRPBF LGTF 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC4367HDD-1#WPBF LTC4367HDD-1#WTRPBF LGVW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC4367IMS8#WPBF LTC4367IMS8#WTRPBF LTGTD 8-Lead Plastic MSOP –40°C to 85°C
LTC4367IMS8-1#WPBF LTC4367IMS8-1#WTRPBF LTGVX 8-Lead Plastic MSOP –40°C to 85°C
LTC4367HMS8#WPBF LTC4367HMS8#WTRPBF LTGTD 8-Lead Plastic MSOP –40°C to 125°C
LTC4367HMS8-1#WPBF LTC4367HMS8-1#WTRPBF LTGVX 8-Lead Plastic MSOP –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 60V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN, VOUT
VIN Input Voltage: Operating Range l 2.5 60 V
Protection Range l –40 100 V
VIN(UVLO) Input Supply Undervoltage Lockout VIN Rising l 1.8 2.2 2.4 V
IVIN Input Supply Current: On SHDN = 2.5V l 30 90 µA
Off SHDN = 0V, VIN = VOUT l 5 20 µA
IVIN(R) Reverse Input Supply Current VIN = –40V, VOUT = 0V l –1.5 –2.5 mA
IVOUT VOUT Input Current: On SHDN = 2.5V, VIN = VOUT l 40 110 µA
Off SHDN = 0V, VIN = VOUT l 3 15 µA
Reverse VIN = –40V, VOUT = 0V l 20 50 µA

Rev. C

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LTC4367
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 60V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
GATE
ΔVGATE Gate Drive (GATE – VOUT) VIN = VOUT = 5.0V, IGATE = 0µA, –1µA l 7.2 8.7 10.8 V
VIN = VOUT = 12V to 60V, IGATE = 0µA, –1µA l 10 11 13.1 V
IGATE(UP) Gate Pull Up Current GATE = 15V, VIN = VOUT = 12V l –20 –35 –60 µA
IGATE(SLOW) Gate Slow Pull Down Current GATE = 20V, VIN = VOUT = 12V l 50 90 160 µA
IGATE(FAST) Gate Fast Pull Down Current GATE = 20V, VIN = VOUT = 12V l 30 60 90 mA
tGATE(SLOW) Slow Turn Off Delay CGATE = 2.2nF, SHDN Falling, VIN = VOUT = 12V l 150 250 575 µs
tGATE(FAST) Gate Fast Turn Off Delay CGATE = 2.2nF, UV or OV Fault l 2 6 µs
tD(ON) GATE Turn-On Delay Time VIN = 12V, Power Good to ΔVGATE > 0V, CGATE = 2.2nF
LTC4367 l 22 32 45 ms
LTC4367-1 l 0.2 0.5 1.2 ms
UV, OV
VUV UV Input Threshold Voltage UV Falling l 492.5 500 507.5 mV
VOV OV Input Threshold Voltage OV Rising l 492.5 500 507.5 mV
VUVHYST UV Input Hysteresis VIN = VOUT = 12V l 20 25 32 mV
VOVHYST OV Input Hysteresis VIN = VOUT = 12V l 20 25 32 mV
ILEAK UV, OV Leakage Current V = 0.5V, VIN = 60V l ±10 nA
tFAULT UV, OV Fault Propagation Delay Overdrive = 50mV l 1 2 µs
VIN = VOUT = 12V
SHDN
VSHDN SHDN Input Threshold SHDN Falling l 0.4 0.75 1.2 V
ISHDN SHDN Input Current SHDN = 10V, VIN = 60V l ±15 nA
tSTART Delay Coming Out of Shutdown Mode SHDN Rising to FAULT Released, VIN = VOUT = 12V l
LTC4367 400 800 1400 µs
LTC4367-1 125 250 500 µs
tSHDN(F) SHDN to FAULT Asserted VIN = VOUT = 12V l 1.5 3 µs
tLOWPWR Delay from Turn Off to Low Power VIN = VOUT = 12V
Operation LTC4367 l 20 32 48 ms
LTC4367-1 l 0.125 0.3 0.6 ms
FAULT
VOL FAULT Output Voltage Low IFAULT = 500µA, VIN = 12V l 0.15 0.4 V
IFAULT FAULT Leakage Current FAULT = 5V, VIN = 60V l ±200 nA

Note 1. Stresses beyond those listed under Absolute Maximum Ratings Note 3. These pins have a diode to GND. They may go below –0.3V if the
may cause permanent damage to the device. Exposure to any Absolute current magnitude is limited to less than 1mA.
Maximum Rating condition for extended periods may affect device Note 4. The GATE pin is referenced to VOUT and does not exceed 73V for
reliability and lifetime. the entire operating range.
Note 2. All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.

Rev. C

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 LTC4367
TYPICAL PERFORMANCE CHARACTERISTICS
VIN Operating Current vs VIN Shutdown Current vs VIN Supply Current vs Voltage
Temperature Voltage (–40V to 100V)
50 8 500
SHDN = 2.5V SHDN = 0V UV = SHDN = 0V
VIN = VOUT VIN = VOUT VOUT = 0V
40 0
VIN = 60V 6

30 VIN = 12V –500

IVIN (µA)
IVIN (µA)

IVIN (µA)
4
20 –1000
VIN = 2.5V
2 TA = 125°C
10 TA = 70°C –1500 TA = 125°C
TA = 25°C TA = 25°C
TA = –45°C TA = –45°C
0 0 –2000
–50 –25 0 25 50 75 100 125 0 10 20 30 40 50 60 –50 –25 0 25 50 75 100
TEMPERATURE (°C) VIN (V) VIN (V)
4367 G01 4367 G02 4367 G03

VOUT Operating Current vs VOUT Shutdown Current vs

Temperature Temperature VOUT Current vs Reverse VIN
50 6 20
SHDN = 2.5V VOUT = 60V SHDN = 0V VOUT = 0V
–45°C
VIN = VOUT VIN = VOUT
5
40
VOUT = 60V 15
VOUT = 12V 4
30
IVOUT (µA)

IVOUT (µA)
IVOUT (µA)

3 10 25°C

20 VOUT = 2.5V VOUT = 12V

2
5
10 125°C
1

VOUT = 2.5V
0 0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 –10 –20 –30 –40
TEMPERATURE (°C) TEMPERATURE (°C) VIN (V)
4367 G04 4367 G05 4367 G06

GATE Drive vs
VIN Supply Voltage GATE Drive vs Temperature GATE Drive vs GATE Current
16 15 12
IGATE = 1µA VIN = VOUT = 12V TA = 125°C
VOUT = 0V VIN = VOUT = 60V TA = 25°C
10 TA = –45°C
12
12

VIN = VOUT VIN = VOUT = 12V 8

9
∆VGATE (V)
∆VGATE (V)

∆VGATE (V)

8 6
6
4
4
3 VIN = VOUT = 2.5V
2
TA = 25°C
IGATE = –1µA
0 0 0
0 10 20 30 40 50 60 –50 –25 0 25 50 75 100 125 0 –10 –20 –30 –40 –50 –60
VIN (V) TEMPERATURE (°C) IGATE(UP) (µA)
4367 G07 4367 G08 4367 G09

Rev. C

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LTC4367
TYPICAL PERFORMANCE CHARACTERISTICS
UV/OV/SHDN Leakage vs
UV Threshold vs Temperature OV Threshold vs Temperature Temperature
508 508 8
VIN = VOUT = 12V VIN = VOUT = 12V VIN = VOUT = 60V

6
504 504

ILEAK (nA)
VUV (mV)

VOV (mV)
SHDN = 60V
500 500
2

496 496
0
UV/OV = 0.5V

492 492 –2
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
4367 G10 4367 G11 4367 G12

UV/OV Propagation Delay vs LTC4367 GATE Turn-On Delay LTC4367 GATE Turn-On Delay
Overdrive Time vs Temperature Time vs VIN
50 50 Recovery Delay Time vs 50
VIN = VOUT = 12V
TA = 25°C Temperature
40 40 40
TA = 125°C TA = –45°C

30 30 30
t D(ON) (ms)

t D(ON) (ms)
t FAULT (µs)

VIN = 12V, 60V TA = 25°C

20 20 20

VIN = 2.5V
10 10 10

0 0 0
1 10 100 1k –50 –25 0 25 50 75 100 125 0 10 20 30 40 50 60
OVERDRIVE (mV) TEMPERATURE (°C) VIN (V)
4367 G13 4367 G14 4367 G15

LTC4367 AC Blocking Turn-On Timing Turn-Off Timing

1V/DIV VOUT DUAL Si7942 MOSFET
GND GATE 100µF, 12Ω LOAD
5V/DIV GATE
VOUT VIN = 12V
VIN
20V/DIV 5V/DIV VOUT
GND
GATE
GND VIN = 12V GND
DUAL Si7942 MOSFET
100µF, 12Ω LOAD
DUAL Si7942
1k, 10µF LOAD ON VOUT 3V/DIV SHDN
3V/DIV SHDN
4367 G16 4367 G17 4367 G18
5ms/DIV 400µs/DIV 400µs/DIV

Rev. C

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 LTC4367
PIN FUNCTIONS
Exposed Pad: The exposed pad may be left open or con- SHDN: Shutdown Control Input. SHDN high enables the
nected to device ground. GATE charge pump which in turn enhances the gate of an
FAULT: Fault Indication Output. This high voltage open drain external N-channel MOSFET. A low on SHDN generates a
output is pulled low if UV is below its monitor threshold, pull down on the GATE output with a 90µA current sink
if OV is above its monitor threshold, if SHDN is low, or if and places the LTC4367 in low current mode (5µA). If
VIN has not risen above VIN(UVLO). unused, connect to VIN with a 510k resistor. If VIN goes
above 80V, the SHDN pin voltage must be kept below 80V
GATE: Gate Drive Output for External N-channel MOSFETs. (see Applications Information).
An internal charge pump provides 35µA of pull-up current
UV: Undervoltage Comparator Input. Connect this pin to an
and up to 13.1V of enhancement to the gate of an external
external resistive divider to set the desired VIN undervolt-
N-channel MOSFET. When turned off, GATE is pulled just
age fault threshold. This input connects to an accurate,
below the lower of VIN or VOUT. When VIN goes negative,
fast (1µs) comparator with a 0.5V falling threshold and
GATE is automatically connected to VIN.
25mV of hysteresis. When UV falls below its threshold, a
GND: Device Ground. 60mA current sink pulls down on the GATE output. When
OV: Overvoltage Comparator Input. Connect this pin to an UV rises back above 0.525V, and after a 32ms GATE turn-
external resistive divider to set the desired VIN overvoltage on delay waiting period (500µs for LTC4367-1), the GATE
fault threshold. This input connects to an accurate, fast charge pump is enabled. The low leakage current of the
(1µs) comparator with a 0.5V rising threshold and 25mV UV input allows the use of large valued resistors for the
of hysteresis. When OV rises above its threshold, a 60mA external resistive divider. If unused and VIN is less than
current sink pulls down on the GATE output. When OV falls 80V, connect to VIN with a 510k resistor.
back below 0.475V, and after a 32ms GATE turn-on delay VIN: Power Supply Input. Maximum protection range:
waiting period (500µs for LTC4367-1), the GATE charge –40V to 100V. Operating range: 2.5V to 60V.
pump is enabled. The low leakage current of the OV input
VOUT: Output Voltage Sense Input. This pin senses the volt-
allows the use of large valued resistors for the external
age at the output side of the external N-channel MOSFET.
resistive divider. Connect to GND if unused. If the voltage
The GATE charge pump voltage is referenced to VOUT. It
at the OV pin can rise above 5V, place a low leakage Zener
is used as the charge pump input when VOUT is greater
clamp on the OV pin.
than approximately 5V.

Rev. C

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LTC4367
BLOCK DIAGRAM

VIN REVERSE
–40V TO 100V PROTECTION GATE

–
+
5V INTERNAL CLOSES SWITCH
SUPPLY WHEN VIN IS NEGATIVE
LDO 5V INTERNAL
SUPPLY
IGATE
GATE 35µA
VOUT CHARGE
PUMP
ENABLE f = 400kHz

2.2V FAULT TURN

UVLO DELAY TIMERS OFF OFF SHDN
SHDN
LOGIC
UV –
+ 60mA 90µA FAULT
0.5V
25mV
GATE PULLDOWN
OV HYSTERESIS
+

0.5V –

GND
4367 BD

Rev. C

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 LTC4367
OPERATION
Many of today’s electronic systems get their power from unexpected supply voltage conditions, while providing a
external sources such as AC or wall adaptors, batteries low loss path for qualified power.
and custom power supplies. Figure 1 shows a supply ar- In the past, to protect electronic systems from improperly
rangement using a DC barrel connector. Power is supplied
connected power supplies, system designers often added
by an AC adaptor or, if the plug is withdrawn, by a remov-
discrete diodes, transistors and high voltage comparators.
able battery. Note that the polarity of the AC adaptor and
The high voltage comparators enable system power only
barrel connector varies by manufacturer. Trouble arises
if the input supply falls within a desired voltage window.
when any of the following occurs:
A Schottky diode or P-channel MOSFET typically added
• The battery is installed backwards in series with the supply protects against reverse supply
• An AC adaptor of opposite polarity is attached connections.

• An AC adaptor of excessive voltage is attached The LTC4367 provides accurate overvoltage and undervolt-
age comparators to ensure that power is applied to the
• The battery is discharged below a safe level system only if the input supply meets the user selectable
This can lead to supply voltages that are too high, too voltage window. Reverse supply protection circuits au-
low, or even negative. If these power sources are applied tomatically isolate the load from negative input voltages.
directly to the electronic systems, the systems could be During normal operation, a high voltage charge pump
subject to damage. The LTC4367 is an input voltage fault enhances the gate of external N-channel power MOSFETs.
protection N-channel MOSFET controller. The part isolates Power consumption is 5µA during shutdown and 70µA
an input supply from its load to protect the load from while operating. The LTC4367 integrates all these func-
tions in 8-lead MSOP and 3mm × 3mm DFN packages.

–40V TO 100V PROTECTION RANGE M1 M2

+
AC
BATTERY LOAD
ADAPTOR
INPUT CIRCUIT
– GATE
VIN VOUT

R4 LTC4367

SHDN

OV, UV PROTECTION R3 FAULT

THRESHOLDS SET TO
SATISFY LOAD CIRCUIT UV

R2

OV
2.5V TO 60V
R1 GND OPERATING RANGE
4367 F01

Figure 1. Polarity Protection for DC Barrel Connectors

Rev. C

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LTC4367
APPLICATIONS INFORMATION
The LTC4367 is an N-channel MOSFET controller that GATE Drive
protects a load from faulty supply connections. A basic The LTC4367 turns on the external N-channel MOSFETs by
application circuit using the LTC4367 is shown in Figure 2 driving the GATE pin above VOUT. The voltage difference
The circuit provides a low loss connection from VIN to
between the GATE and VOUT pins (gate drive) is a function
VOUT as long as the voltage at VIN is between 3.5V and of VIN and VOUT.
18V. Voltages at VIN outside of the 3.5V to 18V range are
prevented from getting to the load and can be as high as Figure 3 highlights the dependence of the gate drive on VIN
100V and as low as –40V. The circuit of Figure 2 protects and VOUT. When system power is first turned on (SHDN
against negative voltages at VIN as shown. No other external low to high, VOUT = 0V), gate drive is at a maximum for all
components are needed. values of VIN. This helps prevent start-up problems into
heavy loads by ensuring that there is enough gate drive
During normal operation, the LTC4367 provides up to to support the load.
13.1V of gate enhancement to the external back-to-back
N-channel MOSFETs. This turns on the MOSFETs, thus As VOUT ramps up from 0V, the absolute value of the GATE
connecting the load at VOUT to the supply at VIN. voltage remains fixed until VOUT is greater than the lower
of (VIN – 1V) or 5V. Once VOUT crosses this threshold,
gate drive begins to increase up to a maximum of 13.1V
Si7942
VIN
100V DUAL
VOUT
(for VIN ≥ 12V). The curves of Figure 3 were taken with
12V NOMINAL
+
3.5V TO 18V a GATE load of –1µA. If there were no load on GATE, the
M1 M2 COUT
100µF gate drive for each VIN would be slightly higher.
VIN
GATE
VOUT Note that when VIN is at the lower end of the operating
R4 LTC4367 range, the external N-channel MOSFET must be selected
453k
with a corresponding lower threshold voltage.
SHDN
R3
1370k 14
TA = 25°C
UV FAULT IGATE = –1µA
R2 12
243k
OV = 18V VIN = 60V
OV 10
UV = 3.5V VIN = 12V
R1
GND
∆VGATE (V)

59k 8
4367 F02 VIN = 5V
6
VIN = 3.3V
Figure 2. LTC4367 Protects Load from –40V 4
to 100V VIN Faults VIN = 2.5V
2

0
0 5 10 15
VOUT (V)
4367 F03

Figure 3. Gate Drive (GATE – VOUT) vs VOUT

Rev. C

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 LTC4367
APPLICATIONS INFORMATION
Table 1 lists some external MOSFETs compatible with Overvoltage and Undervoltage Protection
different VIN supply voltages. The LTC4367 provides two accurate comparators to moni-
Table 1. Dual MOSFETs for Various Supply Ranges tor for overvoltage (OV) and undervoltage (UV) conditions
VIN MOSFET VTH(MAX) VGS(MAX) VDS(MAX) RDS(ON) at VIN. If the input supply rises above the user adjustable
(Ω) OV threshold, the gate of the external MOSFET is quickly
2.5V SiA920 0.7V 5V 8V 0.027 turned off, thus disconnecting the load from the input.
3.3V SiA910 1.0V 8V 12V 0.028 Similarly, if the input supply falls below the user adjust-
3.3V Si6926 1.0V 8V 20V 0.030 able UV threshold, the gate of the external MOSFET also
5V SiA906 1.4V 12V 20V 0.046 is quickly turned off. Figure 4 shows a UV/OV application
5V Si9926 1.5V 12V 20V 0.018 for an input supply of 12V.
>12V SiZ340 2.4V 20V 30V 0.010
The external resistive divider allows the user to select
>12V Si4288 2.5V 20V 40V 0.020
an input supply range that is compatible with the load at
>12V Si7220 3V 20V 60V 0.060
VOUT. Furthermore, the UV and OV inputs have very low
>12V Si4946 3V 20V 60V 0.040 leakage currents (typically < 1nA at 100°C), allowing for
>12V FDS3890 4V 20V 80V 0.044 large values in the external resistive divider. In the applica-
>12V Si7942 4V 20V 100V 0.049 tion of Figure 4, the load is connected to the supply only if
>12V FDS3992 4V 20V 100V 0.054 VIN lies between 3.5V and 18V. In the event that VIN goes
>12V Si7956 4V 20V 150V 0.105 above 18V or below 3.5V, the gate of the external N-channel
MOSFET is immediately discharged with a 60mA current
sink, thus isolating the load from the supply.

LTC4367
12V VIN

R3 UV
1820k COMPARATOR
UV –
UV = 3.5V
25mV
R2 0.5V
+
DISCHARGE GATE
243k WITH 60mA SINK
OV
COMPARATOR
OV
OV = 18V +
25mV
R1
59k 0.5V –

4367 F04

Figure 4. UV, OV Comparators Monitor 12V Supply

Rev. C

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LTC4367
APPLICATIONS INFORMATION
Figure 5 shows the timing associated with the UV pin. Procedure for Selecting UV/OV External Resistor Values
Once a UV fault propagates through the UV comparator The following 3-step procedure helps select the resistor
(tFAULT), the FAULT output is asserted low and a 60mA values for the resistive divider of Figure 4. This procedure
current sink discharges the GATE pin. As VOUT falls, the
minimizes UV and OV offset errors caused by leakage
GATE pin tracks VOUT.
currents at the respective pins.
VUV VUV + VUVHYST 1. Choose maximum tolerable offset error at the UV pin,
UV
VOS(UV). Divide by the worst case leakage current at
tFAULT the UV pin, ILEAK (10nA). Set the sum of R1 + R2 equal
to VOS(UV) divided by 10nA. Note that due to the
FAULT
presence of R3, the actual offset at UV will be slightly
tGATE(FAST) tD(ON) lower:
EXTERNAL N-CHANNEL MOSFETS
GATE
TURN OFF
VOS(UV)
4367 F05 R1+ R2 �
I LEAK

Figure 5. UV Timing (OV < (VOV – VOVHYST), SHDN > 1.2V)
2. Select the desired VIN UV trip threshold, UVTH. Find
the value of R3:
Figure 6 shows the timing associated with the OV pin.
Once an OV fault propagates through the OV comparator VOS(UV) � UV TH – 0.5V�
R3 = • � ÷
(tFAULT), the FAULT output is asserted low and a 60mA I LEAK � 0.5V �
current sink discharges the GATE pin. As VOUT falls, the
GATE pin tracks VOUT. 3. Select the desired VIN OV trip threshold, OVTH. Find
the values of R1 and R2:
VOV
OV VOV – VOVHYST
� VOS(UV) �
tFAULT � ÷+ R3
� ILEAK �
R1 = • 0.5V
FAULT OV TH
tGATE(FAST) tD(ON)

EXTERNAL N-CHANNEL MOSFET VOS(UV)

GATE
TURNS OFF R2 = – R1
4367 F06
ILEAK
Figure 6. OV Timing (UV > (VUV + VUVHYST), SHDN > 1.2V)
The example of Figure 4 uses standard 1% resistor values.
The following parameters were selected:
When both the UV and OV faults are removed, the ex-
ternal MOSFET is not immediately turned on. The input VOS(UV) = 3mV
supply must remain within the user selected power good ILEAK = 10nA
window for at least 32ms (tD(ON)) before the load is again
connected to the supply. This GATE turn-on delay period UVTH = 3.5V
filters noise (including line noise) at the input supply and OVTH = 18V
prevents chattering of power at the load. For applications
that require faster turn-on after a fault, the LTC4367-1
provides a 500µs GATE turn-on delay.

Rev. C

12 For more information www.analog.com

 LTC4367
APPLICATIONS INFORMATION
The resistor values can then be solved: As shown in Figure 7, external back-to-back N-channel
MOSFETs are required for reverse supply protection. When
3mV
1. R1 + R2 = = 300k VIN goes negative, the reverse VIN comparator closes the
10nA internal switch, which in turn connects the gates of the
external MOSFETs to the negative VIN voltage. The body
3mV ( 3.5V – 0.5V ) diode (D1) of M1 turns on, but the body diode (D2) of
2. R3 = • = 1.8M M2 remains in reverse blocking mode. This means that
10nA 0.5V
the common source connection of M1 and M2 remains
The closest 1% value: R3 = 1.82M: about a diode drop higher than VIN. Since the gate voltage
of M2 is shorted to VIN, M2 will be turned off and no cur-
300k + 1.82M rent can flow from VIN to the load at VOUT. Note that the
3. R1 = = 58.9 k
2 • 18V voltage rating of M2 must withstand the reverse voltage
excursion at VIN.
The closest 1% value: R1 = 59k:
Figure 8 illustrates the waveforms that result when VIN
R2 = 300k – 59k = 241k is hot plugged to –20V. VIN, GATE and VOUT start out at
The closest 1% value: R2 = 243k ground just before the connection is made. Due to the
parasitic inductance of the VIN and GATE connections, the
Therefore: OV = 17.93V, UV = 3.51V. voltage at the VIN and GATE pins ring significantly below
–20V. Therefore, a 40V N-channel MOSFET was selected
Reverse VIN Protection to survive the overshoot.
The LTC4367’s rugged and hot-swappable VIN input helps The speed of the LTC4367 reverse protection circuits is
protect the more sensitive circuits at the output load. If evident by how closely the GATE pin follows VIN during
the input supply is plugged in backwards, or a negative the negative transients. The two waveforms are almost
supply is inadvertently connected, the LTC4367 prevents indistinguishable on the scale shown.
this negative voltage from passing to the output load.
The trace at VOUT, on the other hand, does not respond
The LTC4367 employs a novel, high speed reverse supply to the negative voltage at VIN, demonstrating the desired
voltage monitor. When the negative VIN voltage is detected, reverse supply protection. The waveforms of Figure 8 were
an internal switch connects the gates of the external back- captured using a 40V dual N-channel MOSFET, a 10µF
to-back N-channel MOSFETs to the negative input supply. ceramic output capacitor and no load current on VOUT.
D1 D2

M1 M2 GND
VIN = –40V TO LOAD VOUT
+
COUT
5V/DIV

VIN GATE VOUT

VIN
LTC4367 –20V
REVERSE VIN GATE
COMPARATOR

–
+ CLOSES SWITCH
GND WHEN VIN IS NEGATIVE 4367 F08
400ns/DIV
4367 F07

Figure 8. Hot Swapping VIN to –20V

Figure 7. Reverse VIN Protection Circuits
Rev. C

For more information www.analog.com 13

LTC4367
APPLICATIONS INFORMATION
GATE Turn-On Delay Timer further decrease GATE pin slew rate, place a capacitor
The LTC4367 has a GATE turn-on delay timer that filters across the gate and source terminals of the external MOS-
FETs. The waveforms of Figure 10 were captured using
noise at VIN and helps prevent chatter at VOUT. After either
the Si7942 dual N-channel MOSFETs, and a 2A load with
an OV or UV fault has occurred, the input supply must
100µF output capacitor.
return to the desired operating voltage window for at least
32ms (tD(ON)) in order to turn the external MOSFET back 100µF, 6Ω LOAD ON VOUT
on as illustrated in Figure 5 and Figure 6. For applications GATE DUAL Si7942 MOSFET
VIN = 12V
that require faster turn-on after a fault, the LTC4367-1
provides a 500µs GATE turn-on delay. VOUT

Going out of and then back into fault in less than tD(ON) 5V/DIV

will keep the MOSFET off continuously. Similarly, coming SHDN

out of shutdown (SHDN low to high) triggers an 800µs GND
start-up delay timer (see Figure 11).
The GATE turn-on delay timer is also active while the part 4367 F10

is powering up. The timer starts once VIN rises above 400µs/DIV

VIN(UVLO) and VIN lies within the user selectable UV/OV Figure 10. Shutdown: GATE Tracks VOUT as VOUT Decays
power good window. See Figure 9.
FAULT Status
VIN VIN(UVLO)
The FAULT high voltage open drain output is driven low if
SHDN is asserted low, if VIN is outside the desired UV/OV
voltage window, or if VIN has not risen above VIN(UVLO).
tD(ON)
Figure 5, Figure 6 and Figure 11 show the FAULT output
timing.
GATE
MOSFET OFF MOSFET ON
4367 F09
SHDN

Figure 9. GATE Turn-On Delay Timing During tGATE(SLOW) tSTART

Power-On (OV = GND, UV = SHDN = VIN)
GATE
∆VGATE

Shutdown GATE = VOUT

The SHDN input turns off the external MOSFETs in a VOUT

controlled manner. When SHDN is asserted low, a 90µA tSHDN(F)

current sink slowly begins to turn off the external MOSFETs.
FAULT
Once the voltage at the GATE pin falls below the voltage 4367 F11

at the VOUT pin, the current sink is throttled back and a

Figure 11. Shutdown Timing
feedback loop takes over. This loop forces the GATE voltage
to track VOUT, thus keeping the external MOSFETs off as
VOUT decays. Note that when VOUT < 2.2V, the GATE pin Select Between Two Input Supplies
is pulled to within 400mV of ground.
With the part in shutdown, the VIN and VOUT pins can be
Weak gate turn off reduces load current slew rates and driven by separate power supplies. The LTC4367 then
mitigates voltage spikes due to parasitic inductances. To automatically drives the GATE pin just below the lower of
Rev. C

14 For more information www.analog.com

 LTC4367
APPLICATIONS INFORMATION
the two supplies, thus turning off the external back-to-back Limiting Inrush Current During Turn-On
MOSFETs. The application of Figure 12 uses two LTC4367s
The LTC4367 turns on the external N-channel MOSFET
to select between two power supplies. Care should be taken
with a 35µA current source. The maximum slew rate at
to ensure that only one of the two LTC4367s is enabled
the GATE pin can be reduced by adding a capacitor on
at any given time.
the GATE pin:
M1 M2
V1 35µA
Slew Rate =
C GATE
GATE
VIN VOUT Since the MOSFET acts like a source follower, the slew
LTC4367 OUT
rate at VOUT equals the slew rate at GATE.
SHDN

SEL OUT
Therefore, inrush current is given by:
0 V1
1 V2 C OUT
M1 M2 IINRUSH = • 35µA
V2 C GATE

For example, a 1A inrush current to a 330µF output

VIN
GATE
VOUT capacitance requires a GATE capacitance of:
LTC4367

SEL SHDN 35µA • C OUT

C GATE =
4367 F12
IINRUSH
Figure 12. Selecting One of Two Supplies
35µA • 330µF
C GATE = = 11.6nF
Single MOSFET Application 1A
When reverse VIN protection is not needed, a single external The 12nF CGATE capacitor in the application circuit of
N-channel MOSFET may be used. The application circuit of Figure 14 limits the inrush current to just under 1A. RGATE
Figure 13 connects the load to VIN when VIN is less than makes sure that CGATE does not affect the fast GATE turn
30V, and uses the minimal set of external components. off characteristics during UV/OV faults, or during reverse
VIN connection. R5A and R5B help prevent high frequency
SiR870 oscillations with the external N-channel MOSFET and
100V
VIN
24V
VOUT related board parasitics.
+ COUT
100µF
GATE M1 M2
VIN VOUT VIN VOUT
R4 LTC4367 +
499k COUT
SHDN R5A R5B 330µF
10Ω 10Ω

UV FAULT
R2 RGATE
1870k VIN GATE VOUT 5.1k
OV = 30V OV
LTC4367 CGATE
R1 GND 12nF
40.2k
4367 F13

4367 F14

Figure 13. Single MOSFET Application Protects Against 100V Figure 14. Limiting Inrush Current with CGATE

Rev. C

For more information www.analog.com 15

LTC4367
APPLICATIONS INFORMATION
Transients During OV Fault pacitance at the VIN node. D1 is an optional power clamp
The circuit of Figure 15 is used to display transients dur- (TVS, TransZorb) recommended for applications where
ing an overvoltage condition. The nominal input supply VIN can ring above 100V. No clamp was used to capture
is 48V and it has an overvoltage threshold of 60V. The the waveforms of Figure 16. In order to maintain reverse
parasitic inductance is that of a 1 foot wire (roughly 300nH). supply protection, D1 must be a bidirectional clamp rated
Figure 16 shows the waveforms during an overvoltage for at least 225W peak pulse power dissipation.
condition at VIN. These transients depend on the parasitic
inductance and resistance of the wire along with the ca-

12 INCH WIRE Si7942

LENGTH 100V DUAL VOUT
VIN
48V
+ CIN +
M1 M2 COUT
1000µF 22Ω
100µF
GATE
VIN VOUT
R4 LTC4367
523k
D1 SHDN
OPTIONAL

UV FAULT
R2
2430k
OV
OV = 60V
R1 GND
20.5k
4367 F15

Figure 15. OV Fault with Large VIN Inductance

GATE
VOUT 60V
20V/DIV

VIN
20V/DIV 60V

IIN
2A/DIV
0A
4367 F16
400ns/DIV

Figure 16. Transients During OV Fault When No

TransZorb (TVS) Is Used

Rev. C

16 For more information www.analog.com

 LTC4367
APPLICATIONS INFORMATION
REGULATOR APPLICATIONS from the parasitic inductance of the VIN connector. See
Transient During 0V Fault section for more details.
Hysteretic Regulator
Solar Charger
Built-in hysteresis and the availability of both inverting
and noninverting control inputs (OV and UV) facilitate the Figure 19 shows a series regulator for a solar charger.
design of hysteretic regulators. Figure 17 shows how the The LTC4367-1 connects the solar charger to the battery
LTC4367-1 can protect a load from OV transients, while when the battery voltage falls below 13.9V (after a 500µs
regulating the output voltage at a user-defined level. When delay). Conversely, when the battery reaches 14.6V, the
the output voltage reaches its OV limit, the LTC4367-1 LTC4367-1 immediately (2µs) opens the charging path.
turns off the external MOSFETs. The load current then Regulation of the battery voltage is achieved by connect-
discharges the output capacitance until OV falls below the ing a resistive divider from the battery to the accurate OV
hysteresis voltage. The external MOSFETs are turned back comparator input (with 5% hysteresis). The fast rising
on after a 500µs delay. Figure 18 shows the waveforms for response of the OV comparator prevents the battery voltage
the circuit of Figure 17. The voltage spikes on VIN result from rising above the user-selected threshold.
Si4946
DUAL
VIN
VIN VOUT
R7 + CLOAD RLOAD
1Ω 47µF 100Ω
OPTIONAL 1µF
SNUBBER GATE
R4 VIN VOUT 5V/DIV
VOUT
510k
LTC4367-1
UV
R2
SHDN FAULT 1820k
GND
OV
R1 COV
GND 220pF
59k
4367 F17 4367 F18
1ms/DIV

Figure 17. Hysteretic Regulation of VOUT During OV Transients Figure 18. VOUT Regulates at 16V When VIN
Rises Above Desired Level

1/2 OF Si4214 1/2 OF Si4214

D1 D2
D4
B130
M1 M2
TO LOAD
CBYP + CBATT
15W 100nF
SOLAR 100µF
PANEL

12V, 8Ah
SHDN UV VOUT GATE VIN GELCELL

LTC4367-1 R2
3.24M
OV
GND R1 COV
115k 220pF

14.6V OFF
13.9V ON 4367 F19

Figure 19. Series Hysteretic Solar Charger with Reverse-Battery and Solar Panel Protection
Rev. C

For more information www.analog.com 17

LTC4367
APPLICATIONS INFORMATION
Note that during initial start-up, the LTC4367-1 will not handling capability, drain and gate breakdown voltages,
turn on the external MOSFETs until a battery is first con- and threshold voltage.
nected to the VIN pin. To begin operation, VIN must initially The drain to source breakdown voltage must be higher
rise above the 2.2V UVLO lockout voltage. Connecting the than the maximum voltage expected between VIN and VOUT.
battery ensures that the LTC4367-1 comes out of UVLO. Note that if an application generates high energy transients
12V Application with 150V Transient Protection during normal operation or during hot swap, the external
MOSFET must be able to withstand this transient voltage.
Figure 20 shows a 12V application that withstands input
supply transients up to 150V. When the input voltage ex- Due to the high impedance nature of the charge pump
ceeds 17.9V, the OV resistive divider turns off the external that drives the GATE pin, the total leakage on the GATE pin
MOSFETs. As VIN rises to 150V, the gate of transistor M1 must be kept low. The gate drive curves of Figure 3 were
remains in the Off condition, thus preventing conduction measured with a 1µA load on the GATE pin. Therefore,
from VIN to VOUT. Note that M1 must have an operating the leakage on the GATE pin must be no greater than 1µA
range above 150V. in order to match the curves of Figure 3. Higher leakage
currents will result in lower gate drive. The dual N-channel
Resistor R6 and diode D3 clamp the LTC4367 supply volt- MOSFETs shown in Table 1 all have a maximum gate leakage
age to 50V. To prevent R6 from interfering with reverse current of 100nA. Additionally, Table 1 lists representative
operation, the recommended value is 1k or less. Note that MOSFETs that would work at different values of VIN.
the power handling capability of R6 must be considered in
order to avoid overheating during transients. D3 is shown Layout Considerations
as a bidirectional clamp in order to achieve reverse-polarity
protection at VIN. M2 is also required in order to protect The trace length between the VIN pin and the drain of the
VOUT from negative voltages at VIN and should have an external MOSFET should be minimized, as well as the trace
operating range beyond the breakdown of D3. If reverse length between the GATE pin of the LTC4367 and the gates
protection is not desired remove M2 and connect the of the external MOSFETs.
source of M1 directly to VOUT. Place the bypass capacitors at VOUT as close as possible
to the external MOSFET. Use high frequency ceramic
MOSFET Selection capacitors in addition to bulk capacitors to mitigate hot
To protect against a negative voltage at VIN, the external swap ringing. Place the high frequency capacitors closest
N-channel MOSFETs must be configured in a back-to- to the MOSFET. Note that bulk capacitors mitigate ringing
back arrangement. Dual N-channel packages are thus the by virtue of their ESR. Ceramic capacitors have low ESR
best choice. The MOSFET is selected based on its power and can thus ring near their resonant frequency.

M1 M2
VIN FDD2572 FDS5680
VOUT
12V
R6
1k
GATE
VIN VOUT
R4
LTC4367
510k
D3
SHDN
R2
2050k UV
OV = 17.9V OV FAULT
R1
GND
D3: SMAJ43CA BI-DIRECTIONAL 59k
4367 F20

Figure 20. 12V Application Protected from 150V Transients

Rev. C

18 For more information www.analog.com

 LTC4367
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)

0.889 ±0.127
(.035 ±.005)

5.10
(.201) 3.20 – 3.45
MIN (.126 – .136)

3.00 ±0.102
0.42 ± 0.038 0.65 (.118 ±.004) 0.52
(.0165 ±.0015) (.0256) (NOTE 3) 8 7 6 5 (.0205)
TYP BSC REF
RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102
4.90 ±0.152
DETAIL “A” (.118 ±.004)
0.254 (.193 ±.006)
(NOTE 4)
(.010)
0° – 6° TYP
GAUGE PLANE
1 2 3 4
0.53 ±0.152
(.021 ±.006) 1.10 0.86
(.043) (.034)
DETAIL “A” MAX REF
0.18
(.007)
SEATING
PLANE 0.22 – 0.38 0.1016 ±0.0508
(.009 – .015) (.004 ±.002)
TYP 0.65 MSOP (MS8) 0213 REV G
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

Rev. C

For more information www.analog.com 19

LTC4367
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05 1.65 ±0.05

2.10 ±0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 ±0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.125 0.40 ±0.10
TYP
5 8

3.00 ±0.10 1.65 ±0.10

(4 SIDES) (2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C

4 1
0.200 REF 0.75 ±0.05 0.25 ±0.05
0.50 BSC
2.38 ±0.10
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE

Rev. C

20 For more information www.analog.com

 LTC4367
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 03/16 Updated Typical Application and Figures 1, 2, 13, 15 1, 9, 10, 15, 16
Updated SHDN, UV input current rating 2
Changed ISHDN test condition to 10V from 0.75V 4
Updated graphs G09 and G12 5, 6
Updated SHDN and UV Pin Functions 7
B 10/17 Increased tGATE(SLOW) max limit to 575µs 3
Increased tGATE(FAST) max limit to 6µs 3
Increased tSTART max limit to 1400µs 4
C 08/20 Added AEC-Q100 qualification and "W" part numbers 1, 3

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For moreby
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 21
LTC4367
TYPICAL APPLICATION
LTC4367 Protects Step Down Regulator from –30V to 30V VIN Faults

Si4214 30V
DUAL N-CHANNEL VOUT OUTPUT
VIN
5V
12V NOMINAL
3.5A
VOUT PROTECTED 10µF
VIN BD
FROM –30V TO 30V
RUN/SS BOOST
GATE 0.47µF
VIN VOUT LT1913 4.7µH
15k
LTC4367 VC SW
510k
680pF
SHDN RT
1820k 536k
UV FAULT PG FB
SYNC GND
243k 63.4k 100k 47µF

OV
OV = 18V 4367 TA02
UV = 3.5V 59k GND

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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Protection Controller No TVS Required for Most Applications
LTC4368 LTC4367 + Bidirectional Circuit Breaker ±50mV or 50mV/–3mV Circuit Breaker Thresholds;
MSOP-10, DFN-10 Packages
LTC4380 8µA Quiescent Current Surge Stopper 4V to 72V Operation; –60V Input Protection; Pin-Selectable Clamp
LT4363 Surge Stopper Overvoltage/Overcurrent Protection Wide Operating Range: 4V to 80V, Reverse Protection to –60V, Adjustable
Regulator Output Clamp Voltage
LTC4364 Surge Stopper with Ideal Diode 4V to 80V Operation, –40V Reverse Input, –20V Reverse Output
LTC4366 Floating Surge Stopper 9V to >500V Operation, 8-Pin TSOT and 3mm × 2mm DFN Packages
LTC4361 Overvoltage/Overcurrent Protection Controllers 5.8V Overvoltage Threshold, 85V Absolute Maximum
LTC2909 Triple/Dual Inputs UV/OV Negative Monitor Pin Selectable Input Polarity Allows Negative and OV Monitoring
LTC2912/LTC2913 Single/Dual UV/OV Voltage Monitor Adjustable UV and OV Trip Values, ±1.5% Threshold Accuracy
LTC2914 Quad UV/OV Monitor For Positive and Negative Supplies
LTC2955 Pushbutton On/Off Controller Automatic Turn-On, 1.5V to 36V Input, ±36V PB Input
LT4256 Positive 48V Hot Swap Controller with Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output,
Open-Circuit Detect Up to 80V Supply
LTC4260 Positive High Voltage Hot Swap Controller with Wide Operating Range 8.5V to 80V
ADC and I2C
LTC4352 Ideal MOSFET ORing Diode External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V
LTC4354 Negative Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation
LTC4355 Positive Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation
LT1913 Step-Down Switching Regulator 3.6V to 25V Input, 3.5A Maximum Current, 200kHz to 2.4MHz

Rev. C

22
08/20
www.analog.com
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