A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Send video/audio over HDMI on an FPGA

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RSD: RISC-V Out-of-Order Superscalar Processor

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

A Linux-capable RISC-V multicore for and by the world

Common SystemVerilog components

The root repo for lowRISC project and FPGA demos.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

AMBA AXI VIP

Tile based architecture designed for computing efficiency, scalability and generality

4 stage, in-order, compute RISC-V core based on the CV32E40P

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

An AXI4 crossbar implementation in SystemVerilog

Zcash FPGA acceleration engine

SHA256 in (System-) Verilog / Open Source FPGA Miner

Repository gathering basic modules for CDC purpose

RISCV CPU implementation in SystemVerilog

Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.

SystemVerilog Logger

A synthesizable picmicro-midrange clone for FPGAs

Multi-port BRAM IP for ASIC and FPGA

Chacha20 Implementation in SystemVerilog for FPGA and ASIC