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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 23
Volume 23, Number 1, January 2015
- Krishnendu Chakrabarty
:
Editorial. 1-17 - Yu-Hsuan Lee, Cheng-Wei Pan:
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications. 18-29 - Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Signal Processing With Direct Computations on Compressively Sensed Data. 30-43 - Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund:
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme. 44-53 - Hemasundar Mohan Geddada, Chang-Joon Park, Hyung-Joon Jeon, José Silva-Martínez, Aydin Ilker Karsilayan
Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs. 54-67 - Giovanni Causapruno, Gianvito Urgese
Protein Alignment Systolic Array Throughput Optimization. 68-77 - I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao:
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. 78-87 - Szu-Chi Chung
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. 88-97 - Horng-Yuan Shih, Chun-Fan Chen, Yu-Chuan Chang, Yu-Wei Hu:
An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers. 98-106 - Weifeng Sun, Caixia Han, Miao Yang, Shen Xu, Shengli Lu:
A Ripple Control Dual-Mode Single-Inductor Dual-Output Buck Converter With Fast Transient Response. 107-117 - Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. 118-130 - Mohammad Abdur Rouf, Soontae Kim:
Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline. 131-141 - Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze:
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. 142-155 - Mahdi Nikdast, Jiang Xu, Luan H. K. Duong, Xiaowen Wu, Zhehui Wang
Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint. 156-169 - Zhongqi Li, Amer Qouneh, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li:
Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip. 170-183 - Meng-Hung Shen, Po-Chiun Huang:
A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL. 184-188 - Manuel de la Guia Solaz, Richard Conway:
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing. 189-193 - Wen-rui Zhu, Haigang Yang, Tongqiang Gao, Fei Liu, Tao Yin, Dandan Zhang, Hongfeng Zhang:
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler. 194-197 - Hyung-Joon Jeon, José Silva-Martínez, Sebastian Hoyos:
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. 198-202 - Yuan-Ho Chen:
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability. 203-207 - Himanshu Markandeya, Pedro P. Irazoqui
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection. 208-212 - Mohammed Ziaur Rahman, Lindsay Kleeman
Recursive Approach to the Design of a Parallel Self-Timed Adder. 213-217
Volume 23, Number 2, February 2015
- Jienan Chen, Jianhao Hu, Shuyang Lee, Gerald E. Sobelman:
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems. 221-229 - Chung-Hsien Chang, Bo-Wei Chen, Shi-Huang Chen, Jhing-Fa Wang, Yu-Hao Chiu:
Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution. 230-243 - Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang:
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems. 244-253 - Jeongkyu Hong
Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories. 254-265 - Xuan Wang, Jiang Xu
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. 266-279 - Xiaofei Wang, Qianying Tang, Pulkit Jain, Dong Jiao, Chris H. Kim:
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. 280-291 - James Sebastian Guido, Alexandre Yakovlev
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging. 292-305 - Diogo Brito
Quaternary Logic Lookup Table in Standard CMOS. 306-316 - Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty
Scan Test of Die Logic in 3-D ICs Using TSV Probing. 317-330 - Afsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst
Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector. 331-341 - Aritra Banerjee
Signature Driven Hierarchical Post-Manufacture Tuning of RF Systems for Performance and Power. 342-355 - Kentaro Yoshioka
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. 356-368 - Dean Michael Ancajas, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm. 369-373 - Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations. 374-378 - Minghe Xu, Zhenpeng Bian, Ruohe Yao:
Fast Sign Detection Algorithm for the RNS Moduli Set 2n+1-1, 2n-1, 2n. 379-383 - Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro
Fault Tolerant Parallel Filters Based on Error Correction Codes. 384-387 - Marco Lanuzza
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. 388-391 - Amr M. A. Hussien, Rahul Amin
Energy Aware Mapping for Reconfigurable Wireless MPSoCs. 392-396 - Zao Liu, Sheldon X.-D. Tan, Xin Huang, Hai Wang:
Task Migrations for Distributed Thermal Management Considering Transient Effects. 397-401 - Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
Z-TCAM: An SRAM-based Architecture for TCAM. 402-406 - Christelle Hobeika, Claude Thibeault, Jean-François Boland:
Functional Constraint Extraction From Register Transfer Level for ATPG. 407-412
Volume 23, Number 3, March 2015
- Jung-Hyun Park, Heechai Kang, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung:
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. 413-421 - Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. 422-434 - Martin Omaña, Daniele Rossi
Low-Cost On-Chip Clock Jitter Measurement Scheme. 435-443 - Xuan-Dien Do, Huy-Hieu Nguyen, Seok-Kyun Han, Dong Sam Ha, Sang-Gug Lee:
A Self-Powered High-Efficiency Rectifier With Automatic Resetting of Transducer Capacitance in Piezoelectric Energy Harvesting Systems. 444-453 - Soydan Redif
Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications. 454-465 - Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. 466-479 - Xuexin Liu, Hao Yu
A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits. 480-492 - Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li
Economizing TSV Resources in 3-D Network-on-Chip Design. 493-506 - Dimitrios Rodopoulos, Antonis Papanikolaou, Francky Catthoor, Dimitrios Soudris:
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane. 507-519 - Seunghan Lee, Kyungsu Kang, Chong-Min Kyung:
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache. 520-533 - Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh:
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. 534-543 - Ing-Chao Lin, Yu-Hung Cho, Yi-Ming Yang:
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic. 544-556 - Yung-Hui Chung, Jieh-Tsorng Wu:
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. 557-566 - Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang:
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. 567-574 - Xuexin Liu, Kuangya Zhai, Zao Liu, Kai He, Sheldon X.-D. Tan, Wenjian Yu:
Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms. 575-579 - Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs. 580-583 - Pedro Reviriego, Salvatore Pontarelli
A Synergetic Use of Bloom Filters for Error Detection and Correction. 584-587 - Yong-Hun Kim, Young-Ju Kim, Tae-Ho Lee, Lee-Sup Kim:
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS. 588-592 - Irith Pomeranz:
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set. 593-597 - Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS. 598-602 - Pedro Miguens Matutino
Arithmetic-Based Binary-to-RNS Converter Modulo {2n±k} for jn-bit Dynamic Range. 603-607
Volume 23, Number 4, April 2015
- Supriya Karmakar, John A. Chandy
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs. 609-618 - Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama:
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. 619-630 - Abhishek Ambede
Flexible Low Complexity Uniform and Nonuniform Digital Filter Banks With High Frequency Resolution for Multistandard Radios. 631-641 - Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. 642-653 - Jingtong Hu
Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems. 654-663 - Guoyue Jiang, Zhaolin Li, Fang Wang, Shaojun Wei:
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks. 664-677 - Xiaowen Wu, Jiang Xu, Yaoyao Ye, Xuan Wang, Mahdi Nikdast, Zhehui Wang
An Inter/Intra-Chip Optical Network for Manycore Processors. 678-691 - Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng:
A 65 nm Cryptographic Processor for High Speed Pairing Computation. 692-701 - Moshe Avital, Hadar Dagan, Osnat Keren, Alexander Fish
Randomized Multitopology Logic Against Differential Power Analysis. 702-711 - Hoi Lee, Zhe Hua, Xiwen Zhang:
A Reconfigurable 2×2.5×3×4× SC DC-DC Regulator With Fixed On-Time Control for Transcutaneous Power Transmission. 712-722 - Ruzica Jevtic
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors. 723-730 - Hao Liang
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. 731-742 - Daniele Rossi
Impact of Bias Temperature Instability on Soft Error Susceptibility. 743-751 - Heechai Kang, Jisu Kim, Hanwool Jeong, Younghwi Yang, Seong-Ook Jung:
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. 752-765 - Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen:
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. 766-770 - Bo Zhao, Huazhong Yang:
Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL. 771-775 - Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic:
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL. 776-780 - R. R. Manikandan, Abhishek Kumar
A Digital Frequency Multiplication Technique for Energy Efficient Transmitters. 781-785 - Zhentao Xu, Wei Wang, Ning Ning, Wei Meng Lim, Yang Liu, Qi Yu:
A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors. 786-790 - Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu:
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling. 791-795 - Sagar Venkatesh Gubbi, Bharadwaj Amrutur:
All Digital Energy Sensing for Minimum Energy Tracking. 796-800
Volume 23, Number 5, May 2015
- Debasri Saha, Susmita Sur-Kolay:
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification. 801-809 - Sujoy Sinha Roy, Junfeng Fan, Ingrid Verbauwhede
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms. 810-818 - Yingjie Lao, Keshab K. Parhi
Obfuscating DSP Circuits via High-Level Transformations. 819-830 - Yu Zheng, Xinmu Wang, Swarup Bhunia
SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection. 831-841 - Jamshaid Sarwar Malik, Ahmed Hemani, Jameel Nawaz Malik, Ben Slimane, Nasirud Din Gohar:
Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. 842-855 - Yi-Ming Wang, Shih-Nung Wei:
Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit. 856-868 - Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. 869-878 - Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
Data Remapping for Static NUCA in Degradable Chip Multiprocessors. 879-892 - Gabriel Luca Nazar, Leonardo Pereira Santos
Fine-Grained Fast Field-Programmable Gate Array Scrubbing. 893-904 - Lijun Wu, Huijia Huang, Kaile Su
An I/O Efficient Model Checking Algorithm for Large-Scale Systems. 905-915 - Shankar Thirunakkarasu, Bertan Bakkaloglu
Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL. 916-925 - Luis Henrique de Carvalho Ferreira
A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process. 926-934 - Yuh-Shyan Hwang, Yi-Tsen Ku, An Liu, Chia-Hsuan Chen, Jiann-Jong Chen
A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques. 935-943 - Yun Yin, Baoyong Chi, Zhigang Sun, Xinwang Zhang, Zhihua Wang:
A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS. 944-957 - Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. 958-962 - Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha:
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. 963-967 - Pedro Reviriego, Salvatore Pontarelli
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes. 968-972 - Ze-ke Wang, Xue Liu, Bingsheng He
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. 973-977 - Yong Chen
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links. 978-982 - Ching-Che Chung
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. 983-987 - Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim:
A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13~µm CMOS. 988-992
Volume 23, Number 6, June 2015
- Josep Rius:
Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors. 993-1004 - Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications. 1005-1016 - Ali Mirtar
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management. 1017-1030 - Daniele Rossi
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. 1031-1039 - Salomon Beer, Ran Ginosar:
Eleven Ways to Boost Your Synchronizer. 1040-1049 - Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. 1050-1062 - Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Low-Power Programmable PRPG With Test Compression Capabilities. 1063-1076 - Marcelo Ruaro
Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs. 1077-1088 - Nobutaro Shibata, Yusuke Ohtomo, Mika Nishisaka, Yasuhiro Sato:
An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-𝕍DD CMOS/SIMOX Techniques. 1089-1102 - Byung-Geun Lee:
Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC. 1103-1110 - Mahdi Parvizi, Karim Allidina, Mourad N. El-Gamal:
A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique. 1111-1122 - Domenico Zito, Domenico Pepe
High-Frequency CMOS Active Inductor: Design Methodology and Noise Analysis. 1123-1136 - To-Po Wang, Shih-Yu Wang:
Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO. 1137-1144 - Kiichi Niitsu
A CMOS PWM Transceiver Using Self-Referenced Edge Detection. 1145-1149 - Indranil Hatai
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation. 1150-1154 - Yuh-Shyan Hwang, An Liu, Yi-Tsen Ku, Yuan-Bo Chang, Jiann-Jong Chen
A Fast Transient Response Flying-Capacitor Buck-Boost Converter Utilizing Pseudocurrent Dynamic Acceleration Techniques. 1155-1159 - Ke Chen, Jie Han, Fabrizio Lombardi:
On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ. 1160-1164 - Jiangpeng Li, Kai Zhao, Jun Ma, Tong Zhang:
True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance. 1165-1169 - Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li
Read Performance: The Newest Barrier in Scaled STT-RAM. 1170-1174 - Chia-Ling Lynn Chang, Charles H.-P. Wen
Demystifying Iddq Data With Process Variation for Automatic Chip Classification. 1175-1179 - Srinivasan Narayanamoorthy, Hadi Asghari Moghaddam
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications. 1180-1184
Volume 23, Number 7, July 2015
- Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment. 1185-1195 - Na Gong, Jinhui Wang, Shixiong Jiang, Ramalingam Sridhar:
TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors. 1196-1209 - Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang:
A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning. 1210-1220 - Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha:
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. 1221-1234 - Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. 1235-1244 - Jian Yao, Zuochang Ye, Yan Wang:
An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling. 1245-1253 - Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. 1254-1267 - Gholamreza Shomalnasab, Lihong Zhang:
New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies. 1268-1280 - Tak-Jun Oh, In-Chul Hwang:
A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load. 1281-1286 - Nuno Neves
Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms. 1287-1300 - Taimur Gibran Rabuske
An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset. 1301-1307 - Sravan K. Marella, Sachin S. Sapatnekar
A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations. 1308-1321 - Umamaheswara Rao Tida, Rongbo Yang, Cheng Zhuo, Yiyu Shi:
On the Efficacy of Through-Silicon-Via Inductors. 1322-1334 - Liming Xiu:
Direct Period Synthesis for Achieving Sub-PPM Frequency Resolution Through Time Average Frequency: The Principle, The Experimental Demonstration, and Its Application in Digital Communication. 1335-1344 - Antonio Jose Ginés
Background Digital Calibration of Comparator Offsets in Pipeline ADCs. 1345-1349 - Xiaokun Yang, Jean H. Andrian:
A High-Performance On-Chip Bus (MSBUS) Design and Verification. 1350-1354 - Jia-Ching Wang, Li-Xun Lian, Yan-Yu Lin, Jia Hao Zhao:
VLSI Design for SVM-Based Speaker Verification System. 1355-1359 - Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, Chris H. Kim:
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology. 1360-1364 - Xiaoyang Zeng, Yi Li, Yuejun Zhang
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. 1365-1369 - Hanwool Jeong, Taewon Kim, Taejoong Song, Gyu-Hong Kim, Seong-Ook Jung:
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. 1370-1374 - Jintae Kim, Minjae Lee:
A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization. 1375-1379 - Rajiv V. Joshi, Rouwaida Kanj:
Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction". 1380
Volume 23, Number 8, August 2015
- Matthew A. Morrison, Nagarajan Ranganathan, Jay Ligatti:
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. 1381-1389 - Wenfeng Zhao, Yajun Ha, Massimo Alioto:
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study. 1390-1401 - Qiang Liu, Terrence S. T. Mak, Tao Zhang, Xinyu Niu, Wayne Luk, Alex Yakovlev
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems. 1402-1414 - Nobutaro Shibata, Yoshinori Gotoh:
High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost. 1415-1428 - Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. 1429-1438 - Taewoo Han, Inhyuk Choi, Sungho Kang:
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores. 1439-1447 - Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m). 1448-1458 - Zhuo Wang, Kyong-Ho Lee, Naveen Verma:
Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels. 1459-1470 - Qian Wang
A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification. 1471-1484 - Erfan Azarkhish
A Modular Shared L2 Memory Design for 3-D Integration. 1485-1498 - Brad D. Gaynor, Soha Hassoun:
Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits. 1499-1507 - Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Seung-Han Woo, Seong-Ook Jung:
An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management. 1508-1517 - James Lin
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. 1518-1527 - Horng-Yuan Shih, Sheng-Kai Lin, Po-Shun Liao:
An 80× Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-µm CMOS. 1528-1533 - Archit Joshi:
Period Jitter of Frequency-Locked Loops. 1534-1546 - Domenico Albano, Felice Crupi, Francesca Cucchi, Giuseppe Iannaccone
A Sub-kT/q Voltage Reference Operating at 150 mV. 1547-1551 - Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park:
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. 1552-1556 - Mohammad Kafi Kangi, Mohammad Maymandi-Nejad
A Fully Digital ASK Demodulator With Digital Calibration for Bioimplantable Devices. 1557-1561 - Jie Han, Eugene Leung, Leibo Liu
A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors. 1562-1566 - Yi Zhao, S. Saqib Khursheed, Bashir M. Al-Hashimi:
Online Fault Tolerance Technique for TSV-Based 3-D-IC. 1567-1571 - Trinidad Sanchez-Rodriguez
A 1.2-V 450-μW Gm-C Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor. 1572-1576
Volume 23, Number 9, September 2015
- Bao Liu, Lu Wang:
Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation. 1577-1590 - Ing-Chao Lin, Yi-Ming Yang, Cheng-Chian Lin:
High-Performance Low-Power Carry Speculative Addition With Variable Latency. 1591-1603 - Joosung Yun, Sunggu Lee, Sungjoo Yoo:
Dynamic Wear Leveling for Phase-Change Memories With Endurance Variations. 1604-1615 - Aoxiang Tang, Yang Yang, Chun-Yi Lee
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations. 1616-1627 - Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. 1628-1639 - Mengying Zhao, Alex Orailoglu, Chun Jason Xue
Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning. 1640-1650 - Xian Tang, Wai Tung Ng, Kong-Pang Pun:
A Resistor-Based Sub-1-V CMOS Smart Temperature Sensor for VLSI Thermal Management. 1651-1660 - Vasile Gheorghita Gaitan
CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers. 1661-1674 - Ernesto Sánchez, Matteo Sonza Reorda
On the Functional Test of Branch Prediction Units. 1675-1688 - Eun Ji Kim, Jea Hack Lee
Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors. 1689-1699 - Jianfeng Zhu, Leibo Liu
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. 1700-1709 - Abdalhossein Rezai
High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan-Multibit-Shift Technique. 1710-1719 - Chih-Sheng Hou, Jin-Fu Li:
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy. 1720-1728 - Yanan Sun, Hailong Jiao, Volkan Kursun
A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors. 1729-1739 - Yen-Jen Chang, Tung-Chi Wu:
Master-Slave Match Line Design for Low-Power Content-Addressable Memory. 1740-1749 - Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny:
Multistate Register Based on Resistive RAM. 1750-1759 - Cheng Zhuo, Gustavo R. Wilke, Ritochit Chakraborty, Alaeddin A. Aydiner, Sourav Chakravarty, Wei-Kai Shih:
Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface. 1760-1771 - Sumit Jagdish Darak
Reconfigurable Filter Bank With Complete Control Over Subband Bandwidths for Multistandard Wireless Communication Receivers. 1772-1782 - Jesus Omar Lacruz
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. 1783-1792 - Chu Yu, Mao-Hsu Yen:
Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems. 1793-1800 - San-Fu Wang:
Low-Voltage, Full-Swing Voltage-Controlled Oscillator With Symmetrical Even-Phase Outputs Based on Single-Ended Delay Cells. 1801-1807 - Sheng-Lyang Jang, Sanjeev Jain:
Dual C- and S-Band CMOS VCO Using the Shunt Varactor Switch. 1808-1813 - Songting Li, Jiancheng Li, Xiaochen Gu, Hongyi Wang, Cong Li, Jianfei Wu, Minghua Tang:
Reconfigurable All-Band RF CMOS Transceiver for GPS/GLONASS/Galileo/Beidou With Digitally Assisted Calibration. 1814-1827 - Kyungsu Kang, Luca Benini
Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory. 1828-1841 - Wulong Liu, Yu Wang
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis. 1842-1853 - Zhiliang Qian, Syed Mohsin Abbas
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. 1854-1867 - Sadegh Yazdanshenas, Hossein Asadi
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. 1868-1878 - Amir Reza Baghban Behrouzian, Nasser Masoumi:
Analytical Solutions for Distributed Interconnect Models - Part II: Arbitrary Input Response and Multicoupled Lines. 1879-1888 - Qi Yang, Xiaoting Hu, Zhongping Qin:
Secure Systolic Montgomery Modular Multiplier Over Prime Fields Resilient to Fault-Injection Attacks. 1889-1902 - Qingyu Ou, Fang Luo, Shilei Li, Lu Chen:
Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits. 1903-1913 - Mohammad Taherzadeh-Sani
A 350-MS/s Continuous-Time Delta-Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS. 1914-1919 - Chang-Joon Park, Marvin Onabajo, Hemasundar Mohan Geddada, Aydin Ilker Karsilayan
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators. 1920-1930 - Junlin Chen, Jun-Hong Cui, Lei Wang:
RF Power Management via Energy-Adaptive Modulation for Self-Powered Systems. 1931-1935 - Irith Pomeranz:
Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity. 1936-1940 - Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund:
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz. 1941-1945 - Baker Mohammad
Embedded Memory Interface Logic and Interconnect Testing. 1946-1950 - Peyman Pouyan
Adaptive Proactive Reconfiguration: A Technique for Process-Variability- and Aging-Aware SRAM Cache Design. 1951-1955 - Xian Li, Huicai Zhong, Zhenhui Tang, Cheng Jia:
Reliable Antifuse One-Time-Programmable Scheme With Charge Pump for Postpackage Repair of DRAM. 1956-1960 - Anvesha Amaravati, Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Fully On-Chip PT-Invariant Transconductor. 1961-1964 - Satyabrata Sarangi
Efficient Hardware Implementation of Encoder and Decoder for Golay Code. 1965-1968 - Reza Azarderakhsh, Mehran Mozaffari Kermani
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. 1969-1972
Volume 23, Number 10, October 2015
- Robert Fasthuber, Praveen Raghavan, Liesbet Van der Perre
A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency. 1973-1986 - Ting-Jung Lin
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation. 1987-2000 - Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. 2001-2008 - Christos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick:
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity. 2009-2022 - Sang-Hye Chung, Lee-Sup Kim:
A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS. 2023-2033 - Adam Teman
A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs. 2034-2042 - Jianming Yu, Wei Zhou, Yueming Yang, Xiaodong Zhang, Zhiyi Yu:
Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability. 2043-2053 - Baker S. Mohammad
Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs. 2054-2064 - Chang-Chih Chen, Linda S. Milor
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms. 2065-2076 - Ioannis Savidis, Boris Vaisband, Eby G. Friedman:
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. 2077-2089 - Atef Ibrahim
Systolic Array Architectures for Sunar-Koç Optimal Normal Basis Type II Multiplier. 2090-2102 - Shashikanth Bobba, Giovanni De Micheli
Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture. 2103-2115 - Salih Bayar
PFMAP: Exploitation of Particle Filters for Network-on-Chip Mapping. 2116-2127 - Esmat Kishani Farahani, Reza Sarvari:
Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects. 2128-2134 - Jiayin Li, David B. Dgien, Nathan Altay Hunter, Yirong Zhao, Kartik Mohanram:
Two-Port PCM Architecture for Network Processing. 2135-2148 - Ing-Chao Lin, Jeng-Nian Chiou:
High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies. 2149-2161 - Hsin-Fu Luo, Yi-Jun Liu, Ming-Der Shieh:
Efficient Memory-Addressing Algorithms for FFT Processor Design. 2162-2172 - Xiaolin Chen, Andreas Minwegen, Bilal Syed Hussain, Anupam Chattopadhyay, Gerd Ascheid, Rainer Leupers:
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP. 2173-2186 - Pierre-Emmanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells. 2187-2197 - Stefano Di Carlo
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications. 2198-2208 - Hassan Rabah
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction. 2209-2220 - Sriram Venkateshan, Alap Patel, Kuruvilla Varghese:
Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. 2221-2232 - Marco Vacca, Juanchi Wang, Mariagrazia Graziano, Massimo Ruo Roch
Feedbacks in QCA: A Quantitative Approach. 2233-2243 - Zuochang Ye, Tianshi Wang, Yang Li:
Domain-Alternated Optimization for Passive Macromodeling. 2244-2255 - Cheng-Hung Lin, Chih-Shiang Yu:
Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding. 2256-2267 - Bo Yuan, Keshab K. Parhi
Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision. 2268-2280 - Yu-Cheng Fan, Pin-Kang Huang, Hung-Kuan Liu:
VLSI Design of a Depth Map Estimation Circuit Based on Structured Light Algorithm. 2281-2294 - Chih-Hsiang Peng, Ta-Wen Kuan, Po-Chuan Lin, Jhing-Fa Wang, Guo-Ji Wu:
Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies. 2295-2306 - Yu Wang, Song Yao, Shuai Tao, Xiaoming Chen, Yuchun Ma, Yiyu Shi, Huazhong Yang:
HS3-DPG: Hierarchical Simulation for 3-D P/G Network. 2307-2311 - Hussain A. Alzaher, Mohammad K. Al-Ghamdi:
Implementation of Compact Polyphase Channel-Select Filters for Multistandard Broadcasting. 2312-2316 - Xiao Liang Tan, Pak Kwong Chan, Uday Dasgupta:
A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference. 2317-2321 - Fayez Gebali, Atef Ibrahim
Efficient Scalable Serial Multiplier Over GF(2m) Based on Trinomial. 2322-2326 - Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. 2327-2331 - Luis J. Saiz-Adalid
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. 2332-2336 - Akshay Kumar Maan, Dinesh Sasi Kumar, Sherin Sugathan
Memristive Threshold Logic Circuit Design of Fast Moving Object Detection. 2337-2341 - Jing-Shiun Lin, Yin-Tsung Hwang, Shih-Hao Fang, Po-Han Chu, Ming-Der Shieh:
Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems. 2342-2346 - Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. 2347-2351 - Vikramkumar Pudi, K. Sridharan:
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata. 2352-2356
Volume 23, Number 11, November 2015
- Debesh Bhatta, Nicholas Tzou, Joshua W. Wells, Sen-Wen Hsiao, Abhijit Chatterjee:
Incoherent Undersampling-Based Waveform Reconstruction Using a Time-Domain Zero-Crossing Metric. 2357-2370 - Hokyu Lee, Aurangozeb
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter. 2371-2383 - Muhammad Ahmadi, Won Namgoong:
Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation. 2384-2394 - Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang:
A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters. 2395-2407 - Seyed Mohammad Ali Zeinolabedin
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications. 2408-2416 - Ivan Ukhov, Petru Eles, Zebo Peng:
Temperature-Centric Reliability Analysis and Optimization of Electronic Systems Under Process Variation. 2417-2430 - Yuejian Wu, Sandy Thomson, Han Sun, David Krause, Song Yu, George Kurio:
Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs. 2431-2437 - Ghasem Pasandi, Sied Mehdi Fakhraie:
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations. 2438-2446 - Michail Maniatakos
Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving. 2447-2460 - Salomon Beer, Ran Ginosar:
A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance. 2461-2472 - Bo-Cheng Charles Lai, Kuan-Ting Chen, Ping-Ru Wu:
A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems. 2473-2486 - Ching-Che Chung
A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector. 2487-2496 - Enrique F. Cantó-Navarro
Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units. 2497-2507 - Jun Lin, Zhiyuan Yan:
An Efficient List Decoder Architecture for Polar Codes. 2508-2518 - Ying Teng, Baris Taskin:
ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design. 2519-2530 - Gian Domenico Licciardo
Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images. 2531-2539 - Babak Zamanlooy, Mitra Mirhassani:
CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning. 2540-2551 - Mahdi Nikdast, Jiang Xu, Luan Huu Kinh Duong
Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison. 2552-2565 - Leibo Liu
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures. 2566-2580 - Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu
Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. 2581-2594 - Liuxi Qian, Zhaori Bi, Dian Zhou, Xuan Zeng:
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. 2595-2605 - Jia Wang, Xuanxing Xiong, Xingwu Zheng:
Deterministic Random Walk: A New Preconditioner for Power Grid Analysis. 2606-2616 - Jianlei Yang
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. 2617-2628 - Irith Pomeranz:
Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction. 2629-2638 - Xiaolong Zhang, Huiyun Li, Li Jiang, Qiang Xu:
A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method. 2639-2647 - Mohamed Elshamy, Hassan Mostafa
A Novel Nondestructive Read/Write Circuit for Memristor-Based Memory Arrays. 2648-2656 - Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad:
Variable Resistance Spectrum Assignment in Phase Change Memory Systems. 2657-2670 - Myonglae Chu
A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-µm CMOS Technology. 2671-2675 - Jesus Omar Lacruz
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. 2676-2679 - Dandan Zhang, Hai-Gang Yang, Wen-rui Zhu, Wei Li, Zhihong Huang, Lin Li, Tianyi Li:
A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter. 2680-2684 - Hyun Kim, Chae-Eun Rhee, Hyuk-Jae Lee:
An Effective Combination of Power Scaling for H.264/AVC Compression. 2685-2689 - Alex Pappachen James
Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication. 2690-2694 - Ke Chen, Jie Han, Fabrizio Lombardi:
On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells. 2695-2699 - Zhu Wang, Zonghua Gu
WCET-Aware Energy-Efficient Data Allocation on Scratchpad Memory for Real-Time Embedded Systems. 2700-2704 - David Money Harris:
Sequential Element Timing Parameter Definition Considering Clock Uncertainty. 2705-2708 - Jae Hoon Kim, Wook Kim, Young Hwan Kim:
Efficient Statistical Timing Analysis Using Deterministic Cell Delay Models. 2709-2713 - Xiaobin Yuan, Pawel Owczarczyk, Alan J. Drake, Marshall D. Tiner, David T. Hui, John P. Pennings, Francesco A. Campisano, Richard L. Willaman, Leana M. Cropp, Rudolph D. Dussault:
Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths. 2714-2718 - Chien-Hui Liao, Charles H.-P. Wen
Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization. 2719-2723 - Mehrzad Nejat, Bijan Alizadeh
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations. 2724-2727 - Chao Wang, Yuwei Yan, Xiaoyu Fu:
A High-Throughput Low-Complexity Radix-24-22-23 FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems. 2728-2732 - Yongtae Kim, Yong Zhang, Peng Li:
Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing. 2733-2737 - Roger Yubtzuan Chen, Zong-Yi Yang
CMOS Transimpedance Amplifier for Visible Light Communications. 2738-2742 - Hao Wang, Kai Zhao, Jiangpeng Li, Tong Zhang:
Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance. 2743-2747 - Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung:
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. 2748-2752 - Kung Chi Cinnati Loi, Seok-Bum Ko
Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves. 2753-2756
Volume 23, Number 12, December 2015
- Zhenzhi Wu, Dake Liu:
High-Throughput Trellis Processor for Multistandard FEC Decoding. 2757-2767 - Jinjia Zhou
A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. 2768-2781 - Manash Chanda
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. 2782-2790 - Shao-Ying Yeh, Yuan-Te Liao, Wei-Chi Lai, Terng-Yin Hsu:
Cost-Efficient Frequency-Domain MIMO-OFDM Modem With an SIMD ALU-Based Architecture. 2791-2803 - Mehran Mozaffari Kermani
Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications. 2804-2812 - Peyman Ahmadi, Mohammad Hossein Taghavi, Leonid Belostotski
A 0.13-µm CMOS Current-Mode All-Pass Filter for Multi-GHz Operation. 2813-2818 - Matteo Crotti, Ivan Rech
A 2-GHz Bandwidth, Integrated Transimpedance Amplifier for Single-Photon Timing Applications. 2819-2828 - Hao Wang, Xian Tang, Chiu-sing Choy, Ka Nang Leung
A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End. 2829-2841 - Hsiao-Chin Chen, Ming-Yu Yen, Kuo-Jin Chang:
Searching for Spectrum Holes: A 400-800 MHz Spectrum Sensing System. 2842-2851 - Shao-Wei Chiu, Chun-Chieh Kuo, Yi-Ping Su, Ke-Horng Chen
Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems. 2852-2861 - Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta
Synthesis for Width Minimization in the Single-Electron Transistor Array. 2862-2875 - Yi Xiang, Sudeep Pasricha:
Run-Time Management for Multicore Embedded Systems With Energy Harvesting. 2876-2889 - Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
Efficient and Correct by Construction Assertion-Based Synthesis. 2890-2901 - Chen Hou
Bayesian Prediction-Based Energy-Saving Algorithm for Embedded Intelligent Terminal. 2902-2912 - Ashutosh Mishra
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm. 2913-2921 - Wenpian Paul Zhang, Xingyuan Tong
Noise Modeling and Analysis of SAR ADCs. 2922-2930 - Pooria M. Yaghini, Ashkan Eghbal, Misagh Khayambashi, Nader Bagherzadeh
Coupling Mitigation in 3-D Multiple-Stacked Devices. 2931-2944 - Zhihua Gan, Emre Salman, Milutin Stanacevic:
Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits. 2945-2956 - Salomon Beer, Jerome Cox, Ran Ginosar, Tom Chaney, David M. Zar:
Variability in Multistage Synchronizers. 2957-2969 - Ameneh Golnari, Mahdi Shabany, S. Alireza Nezamalhosseini
Design and Implementation of Time and Frequency Synchronization in LTE. 2970-2982 - Hailang Wang, Emre Salman:
Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating. 2983-2991 - Nima Aghaee
Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs. 2992-3005 - Irith Pomeranz:
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks. 3006-3014 - Ioannis Seitanidis, Anastasios Psarras
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip. 3015-3028 - Sayed Taha Muhammad, Rabab Ezz-Eldin, Magdy A. El-Moursy, Ali A. El-Moursy
Traffic-Based Virtual Channel Activation for Low-Power NoC. 3029-3042 - Matteo Cuppini, Claudio Mucci, Eleonora Franchi Scarselli:
Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis. 3043-3052 - Hang Lu, Binzhang Fu, Ying Wang, Yinhe Han, Guihai Yan, Xiaowei Li
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. 3053-3064 - Xiaosen Liu
A Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for Internet of Things Smart Nodes. 3065-3075 - Shuang Li, Sami Smaili, Yehia Massoud:
Parasitic-Aware Design of Integrated DC-DC Converters With Spiral Inductors. 3076-3084 - Peng Ouyang, Shouyi Yin, Leibo Liu
Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. 3085-3098 - Tariq Alshawi, Abdelouahab Bentrcia
Design and Low-Complexity Implementation of Matrix-Vector Multiplier for Iterative Methods in Communication Systems. 3099-3103 - Yaohua Zhao, Pui-In Mak
Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area. 3104-3108 - Jim Boley, Peter Beshay, Benton H. Calhoun:
Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization. 3109-3113 - Aritra Banerjee
Automatic Test Stimulus Generation for Diagnosis of RF Transceivers Using Model Parameter Estimation. 3114-3118 - Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak
Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques. 3119-3123 - Kang Zhao, Wenbo Shen:
Parallel Stimulus Generation Based on Model Checking for Coherence Protocol Verification. 3124-3128 - Tiantao Lu, Ankur Srivastava
Modeling and Layout Optimization for Tapered TSVs. 3129-3132 - Pasquale Corsonello
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. 3133-3137 - Gang He, Dajiang Zhou, Yunsong Li, Zhixiang Chen, Tianruo Zhang, Satoshi Goto:
High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding. 3138-3142 - Amirreza Alizadeh
On Temperature Dependency of Delay for Local, Intermediate, and Repeater Inserted Global Copper Interconnects. 3143-3147 - Maliang Liu, Zhangming Zhu, Yintang Yang:
A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in 0.18~µm CMOS. 3148-3152
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