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IEEE Journal of Solid-State Circuits, Volume 38
Volume 38, Number 1, January 2003
- Alexander Schild, Hans-Martin Rein, Jens Müllrich, Lars Altenhain, Jürgen Blank, Karl Schrödinger:
High-gain SiGe transimpedance amplifier array for a 12×10 Gb/s parallel optical-fiber link. 4-12 - Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. 13-21 - Tim Piessens
, Michiel Steyaert
Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier. 22-29 - Wenjun Sheng, Bo Xia, Ahmed E. Emira, Chunyu Xin, Ari Yakov Valero-López, Sung Tae Moon, Edgar Sánchez-Sinencio:
A 3-V, 0.35-μm CMOS Bluetooth receiver IC. 30-42 - Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. 43-53 - Chi-Sheng Lin, Bin-Da Liu:
A new successive approximation architecture for low-power low-cost CMOS A/D converter. 54-62 - Christopher D. Salthouse, Rahul Sarpeshkar:
A practical micropower programmable bandpass filter for use in bionic ears. 63-70 - Ugur Çilingiroglu, Adriana Becker-Gomez, Kenton T. Veeder:
An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator. 71-83 - Francisco Serra-Graells
Sub-1-V CMOS proportional-to-absolute temperature references. 84-88 - Dongsheng Ma, Wing-Hung Ki
Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode. 89-100 - Yoshinori Muramatsu, Susumu Kurosawa, Masayuki Furumiya, Hiroaki Ohkubo, Yasutaka Nakashiba:
A signal-processing CMOS image sensor using a simple analog operation. 101-106 - Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami
A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC. 107-113 - Chris Binan Wang, Sonny Ishizuka, Bill Yang Liu:
A 113-dB DSD audio ADC using a density-modulated dithering scheme. 114-119 - Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering. 120-125 - Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
DC-coupled IF stage design for a 900-MHz ISM receiver. 126-134 - Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology. 135-137 - Rami Ahola, Kari Halonen:
A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer. 138-140 - Yuping Toh, John A. McNeill
Single-ended to differential converter for multiple-stage single-ended ring oscillators. 141-145 - Ka Nang Leung
A CMOS voltage reference based on weighted ΔVGS for CMOS low-dropout linear regulators. 146-150 - Gianluca Giustolisi, Gaetano Palumbo, M. Criscione, F. Cutri:
A low-voltage low-power voltage reference based on subthreshold MOSFETs. 151-154 - Igor Arsovski, Trevis Chandler, Ali Sheikholeslami:
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. 155-158 - Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig:
Correction to "A carry-free 54 b x 54 b multiplier using equivalent bit conversion algorithm". 159 - Wolfgang Rülling:
A remark on carry-free binary multiplication. 159-160 - Milos D. Ercegovac, Tomás Lang, Y. Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig:
Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm". 160-161
Volume 38, Number 2, February 2003
- Lawrence Der, Behzad Razavi:
A 2-GHz CMOS image-reject receiver with LMS calibration. 167-175 - Alireza Zolfaghari, Behzad Razavi:
A low-power 2.4-GHz transmitter/receiver CMOS IC. 176-183 - Hao Li
Millimeter-wave VCOs with wide tuning range and low phase noise, fully integrated in a SiGe bipolar production technology. 184-191 - Hideyuki Nosaka
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. 192-197 - Takamoto Watanabe, Shigenori Yamauchi:
An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time. 198-204 - Rola A. Baki, Mourad N. El-Gamal:
A low-power 5-70-MHz seventh-order log-domain filter with programmable boost, group delay, and gain for hard disk drive applications. 205-215 - José Silva-Martínez, Joseph Adut, José Miguel Rocha-Pérez, Moises E. Robinson, Shahriar Rokhsaz:
A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system. 216-225 - Bahram Fotouhi:
An efficient CMOS line driver for 1.544-Mb/s T1 and 2.048-Mb/s E1 applications. 226-236 - Bharath Kumar Thandri, José Silva-Martínez:
A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors. 237-243 - Maziar Tavakoli, Rahul Sarpeshkar:
An offset-canceling low-noise lock-in architecture for capacitive sensing. 244-253 - Chung-Hsun Huang, Jinn-Shyan Wang:
High-performance and power-efficient CMOS comparators. 254-262 - Benoit Provost, Edgar Sánchez-Sinencio:
On-chip ramp generators for mixed-signal BIST and ADC self-test. 263-273 - Ryuichi Hashido, Akihiro Suzuki, Akihiko Iwata, Tatsuki Okamoto
A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method. 274-280 - Eugenio Culurciello, Ralph Etienne-Cummings, Kwabena A. Boahen:
A biomorphic digital image sensor. 281-294 - Ming-Dou Ker, Tung-Yang Chen:
Substrate-triggered ESD protection circuit without extra process modification. 295-302 - Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama:
A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology. 303-311 - Kevin J. Chen
Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices. 312-318 - Amit Agarwal, Hai Li, Kaushik Roy:
A single-Vt low-leakage gated-ground cache for deep submicron. 319-328 - Jung Pill Kim, Woodward Yang, Han-Yuan Tan:
A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme. 329-337 - John P. Keane, Michael Q. Le, Paul J. Hurst:
Analog timing recovery for a noise-predictive decision-feedback equalizer. 338-342 - Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A fast locking and low jitter delay-locked loop using DHDL. 343-346 - Ching-Che Chung
An all-digital phase-locked loop for high-speed clock generation. 347-351 - John W. M. Rogers, David G. Rahn, Calvin Plett:
A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators. 352-356 - Hans Gustat, Frank Herzel:
Integrated FSK demodulator with very high sensitivity. 357-360 - Yongping Fan
On-die termination resistors with analog impedance control for standard CMOS technology. 361-364 - Vishnu Balan:
A low-voltage regulator circuit with self-bias to improve accuracy. 365-368 - Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta:
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture. 369-373
Volume 38, Number 3, March 2003
- Danilo Manstretta
Second-order intermodulation mechanisms in CMOS downconverters. 394-406 - Donhee Ham
Virtual damping and Einstein relation in oscillators. 407-418 - Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu:
Frequency-independent equivalent-circuit model for on-chip spiral inductors. 419-426 - David Cassan, John R. Long:
A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS. 427-435 - John T. Stonick, Gu-Yeon Wei, Jeff L. Sonntag, Daniel Weinlader:
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS. 436-443 - Carlos H. Diaz
Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. 444-449 - Patrick G. Drennan, Colin C. McAndrew:
Understanding MOSFET mismatch for analog design. 450-456 - Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu:
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. 457-463 - Teemu Salo, Saska Lindfors, Tuomas Hollman, Jere A. M. Järvinen, Kari A. I. Halonen:
80-MHz bandpass ΔΣ modulators for multimode digital IF receivers. 464-474 - Matthew R. Miller, Craig S. Petrie:
A multibit sigma-delta ADC for multimode receivers. 475-482 - Koen Uyttenhove, Jan Vandenbussche, Erik Lauwers, Georges G. E. Gielen
Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter. 483-494 - Masahiro Murakawa
An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions. 495-502 - Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda:
A 402-output TFT-LCD driver IC with power control based on the number of colors selected. 503-510 - Hoi Lee, Philip K. T. Mok
Active-feedback frequency-compensation technique for low-power multistage amplifiers. 511-520 - Michele Borgatti, Francesco Lertora, Benoit Forêt, Lorenzo Cali:
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O. 521-529 - Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media embedded processor. 530-540 - Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima:
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. 541-549 - Robert C. Frye, Sharad Kapur, Robert C. Melville:
A 2-GHz quadrature hybrid implemented in CMOS technology. 550-555 - Ranjit Gharpurey, Naveen Yanduru, Francesco Dantoni, Petteri Litmanen, Guglielmo Sirna, Terry Mayhugh Jr., Charles Lin, Irene Yuanying Deng, Paul Fontaine, Fang Lin:
A direct-conversion receiver for the 3G WCDMA standard. 556-560 - Ka Nang Leung
A 2-V 23-μA 5.3-ppm/°C curvature-compensated CMOS bandgap voltage reference. 561-564 - Monte Mar, Bert Sullam, Eric Blom:
An architecture for a configurable mixed-signal device. 565-568 - Ingrid Verbauwhede
Design and performance testing of a 2.29-GB/s Rijndael processor. 569-572
Volume 38, Number 4, April 2003
- Knut Kieschnick, Horst Zimmermann
High-sensitivity BiCMOS OEIC for optical storage systems. 579-584 - Praveen Kallam, Edgar Sánchez-Sinencio, Aydin Ilker Karsilayan
An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter. 585-593 - Jussi Ryynänen
A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA. 594-602 - June-Ming Hsu:
A 0.18-μm CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter. 603-613 - Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan:
Jitter transfer characteristics of delay-locked loops - theories and design techniques. 614-621 - Stanley Schuster, Peter W. Cook:
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. 622-630 - Jae-Yoon Sim, Hongil Yoon, Ki-Chul Chun, Hyun-Seok Lee, Sang-Pyo Hong, Kyu-Chan Lee, Jei-Hwan Yoo, Dong-Il Seo, Soo-In Cho:
A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. 631-640 - Byung-Do Yang, Lee-Sup Kim:
A low-power ROM using charge recycling and charge sharing techniques. 641-653 - Chi-Sheng Lin, Jui-Chuan Chang, Bin-Da Liu:
A low-power precomputation-based fully parallel content-addressable memory. 654-662 - Ahmed Nader Mohieldin
A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector. 663-668 - Choong-Yul Cha, Sang-Gug Lee:
A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. 669-672 - Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu:
A spread-spectrum clock generator with triangular modulation. 673-676 - Chi-Fang Li, Wern-Ho Sheen, Chong-Ren Wang, Yuan-Sun Chu:
A fast multispeed comma-free Reed-Solomon decoder for W-CDMA applications using foldable systolic array architecture. 677-682 - D. George Gata:
Erratum "A 1.1-V 270-μ a mixed-signal hearing aid chip". 683-682 - Pierce Nagle:
Erratum "A wide-band linear amplitude modulator for polar transmitters based on the concept of interleaving delta modulation". 683
Volume 38, Number 5, May 2003
- Shekhar Borkar, Yoshinobu Nakagome:
Guest Editorial. 687 - Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar:
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. 689-695 - Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De:
Forward body bias for microprocessors in 130-nm technology generation and beyond. 696-701 - Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano:
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. 702-708 - Mark A. Anders, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar:
A transition-encoded dynamic bus technique for high-performance interconnects. 709-714 - Shoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima:
A ferroelectric memory-based secure dynamically programmable gate array. 715-725 - Masanori Fujibayashi, Toshiyuki Nozawa, Takahiro Nakayama
A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture. 726-733 - John Hyde, Todd Humes, Chris Diorio, Mike Thomas, Miguel E. Figueroa
A 300-MS/s 14-bit digital-to-analog converter in logic CMOS. 734-740 - Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno:
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. 741-746 - Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos:
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. 747-754 - Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. 755-761 - Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama:
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. 762-768 - Mark Durlam, Peter J. Naji, Asim Omair, Mark Deherrera, John Calder, Jon M. Slaughter, Brad N. Engel, Nicholas D. Rizzo, Greg Grynkewich, Brian Butcher, Clarence Tracy, Ken Smith, Kelly W. Kyler, J. Jack Ren, Jaynal A. Molla, William A. Feil, Rick G. Williams, Saied Tehrani:
A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects. 769-773 - Waleed Khalil, Tsung-Yuan Chang, Xuewen Jiang, Syed R. Naqvi, Babak Nikjou, James Tseng:
A highly integrated analog front-end for 3G. 774-781 - Emad Hegazi
A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS. 782-792 - Armin Deiss, Qiuting Huang:
A low-power 200-MHz receiver for wireless hearing aid devices. 793-804 - Vincent Sin-Luen Cheung, Howard C. Luong
A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers. 805-816 - Hiroshi Komurasaki, Tomohiro Sano, Tetsuya Heima, Kazuya Yamamoto, Hideyuki Wakada, Ikuo Yasui, Masayoshi Ono, Toshitsugu Miwa, Hisayasu Sato, Takahiro Miki, Naoyuki Kato:
A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications. 817-825 - James W. Tschanz, Siva G. Narendra, Raj Nair, Vivek De:
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. 826-829 - Goichi Ono, Masayuki Miyazaki:
Threshold-voltage balance for minimum supply operation [LV CMOS chips]. 830-833 - Richard Chang, Niranjan Talwalkar, C. Patrick Yue
Near speed-of-light signaling over on-chip electrical interconnects. 834-838 - Yibin Ye, Muhammad M. Khellah
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. 839-842
Volume 38, Number 6, June 2003
- Chun-Huat Heng
A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO. 848-854 - Benyong Zhang, Phillip E. Allen, Jeff M. Huard:
A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS. 855-865 - Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez, Sherif H. K. Embabi:
A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier. 866-874 - Arthur Torosyan, Dengwei Fu, Alan N. Willson Jr.:
A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS. 875-887 - Tai-Cheng Lee, Behzad Razavi:
A stabilization technique for phase-locked frequency synthesizers. 888-894 - Salvatore Levantino
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing. 895-904 - Joon Hyung Kim, Ji Hoon Kim, Youn Sub Noh, Chul Soon Park:
An InGaP-GaAs HBT MMIC smart power amplifier for W-CDMA mobile handsets. 905-910 - Sudhir Aggarwal, Abolfazl (Saeed) Khosrowbeygi, Anton Daanen:
A single-stage variable-gain amplifier with 70-dB dynamic range for CDMA2000 transmit applications. 911-917 - Fikret Dulger, Edgar Sánchez-Sinencio, José Silva-Martínez:
A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS. 918-928 - Adriana Becker-Gomez, Ugur Çilingiroglu, José Silva-Martínez:
Compact sub-hertz OTA-C filter design with interface-trap charge pump. 929-934 - Chung-Wook Roh, Hye-Jeong Kim, Sang-Hoon Lee, Myung-Joong Youn:
Multilevel voltage wave-shaping display driver for AC plasma display panel application. 935-947 - Achim Graupner, Jörg Schreiter, Stefan Getzlaff, René Schüffny:
CMOS image sensor with mixed-signal processor array. 948-957 - Reid R. Harrison, Cameron Charles:
A low-power low-noise CMOS amplifier for neural recording applications. 958-965 - Maximilian Sergio, Nicolò Manaresi, Fabio Campi, Roberto Canegallo, Marco Tartagni, Roberto Guerrieri:
A dynamically reconfigurable monolithic CMOS pressure sensor for smart fabric. 966-975 - Cailin Davis, Ivars G. Finvers:
A 14-bit high-temperature ΣΔ modulator in standard CMOS. 976-986 - Hirobumi Watanabe, Shunsuke Ando, Hideyuki Aota, Masanori Dainin, Yong-Jin Chun, Kenji Taniguchi:
CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration. 987-994 - Haigang Feng, Guang Chen, Rouying Zhan, Qiong Wu, Xiaokang Guan, Haolu Xie, Albert Z. H. Wang, R. Gafiteanu:
A mixed-mode ESD protection circuit simulation-design methodology. 995-1006 - Dongsheng Ma, Wing-Hung Ki
A pseudo-CCM/DCM SIMO switching converter with freewheel switching. 1007-1014 - Shwetabh Verma, Hamid R. Rategh, Thomas H. Lee:
A unified model for injection-locked frequency dividers. 1015-1027 - Hyunchol Shin, Zhiwei Xu, M. Frank Chang:
A 1.8-V 6/9-GHz reconfigurable dual-band quadrature LC VCO in SiGe BiCMOS technology. 1028-1032 - Emad Hegazi
Varactor characteristics, oscillator tuning curves, and AM-FM conversion. 1033-1039 - Chia-Hsin Wu, Chih-Chun Tang, Shen-Iuan Liu:
Analysis of on-chip spiral inductors using the distributed capacitance model. 1040-1044 - Henrik Sjöland
A merged CMOS LNA and mixer for a WCDMA receiver. 1045-1050 - Narayan Prasad Ramachandran, Hüseyin Dinç, Aydin I. Karsilayan
A 3.3-V CMOS adaptive analog video line driver with low distortion performance. 1051-1058 - Eric B. Blecker, Thomas M. McDonald, Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis:
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue. 1059-1062 - Nagendra Krishnapura
Micropower low-voltage analog filter in a digital CMOS process. 1063-1067 - Roberto Pelliconi, David Iezzi, Andrea Baroni, Marco Pasotti, Pier Luigi Rolandi:
Power efficient charge pump in deep submicron standard CMOS technology. 1068-1071 - Seiichiro Mizuno
A 256×256 compact CMOS image sensor with on-chip motion detection function. 1072-1075 - Alberto A. Colavita, Andres Cicuttin, F. Fratnik, G. Capello:
SORTCHIP: a VLSI implementation of a hardware algorithm for continuous data sorting. 1076-1079
Volume 38, Number 7, July 2003
- Franz Dielacher
Guest Editorial. 1095-1097 - Michael S. Kappes:
A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications. 1098-1104 - Richard Gaggl
A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-μm CMOS. 1105-1114 - Koen Uyttenhove, Michiel S. J. Steyaert
A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS. 1115-1122 - Michael D. Scott, Bernhard E. Boser, Kristofer S. J. Pister:
An ultralow-energy ADC for Smart Dust. 1123-1129 - Derek K. Shaeffer, Steffen Kudszus:
Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission. 1130-1138 - Judith Maget, Marc Tiebout, Rainer Kraus:
MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS. 1139-1147 - Sander L. J. Gierkink, Salvatore Levantino
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. 1148-1154 - Domine M. W. Leenaerts, Cicero S. Vaucher, Henk Jan Bergveld
A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-μm CMOS. 1155-1162 - Giampiero Montagna, Giuseppe Gramegna, Ivan Bietti, Massimo Franciotta, Andrea Baschirotto
A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio. 1163-1171 - Ahmed N. Mohieldin
A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators. 1172-1181 - Yijun Zhou, Jiren Yuan:
A 10-bit wide-band CMOS direct digital RF amplitude modulator. 1182-1188 - Uroschanit Yodprasit, Christian C. Enz:
A 1.5-V 75-dB dynamic range third-order Gm-C filter integrated in a 0.18-μm standard digital CMOS process. 1189-1197 - Marco Berkhout:
An integrated 200-W class-D audio amplifier. 1198-1206 - Dieter Draxelmayr, Richard Borgschulze:
A self-calibrating Hall sensor IC with direction detection. 1207-1212 - Seong-Jun Song, Sung Min Park, Hoi-Jun Yoo:
A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique. 1213-1219 - Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano:
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications. 1220-1226 - Soon-Kyun Shin, Seok-Min Jung, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim:
A slew-rate controlled output driver using PLL as compensation circuit. 1227-1233 - Engling Yeo, Stephanie Augsburger, W. Rhett Davis, Borivoje Nikolic
A 500-Mb/s soft-output Viterbi decoder. 1234-1241 - Ingemar Söderquist:
Globally updated mesochronous design style. 1242-1249 - Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. 1250-1260 - Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes:
A 0.5-V 1-μW successive approximation ADC. 1261-1265 - Kambiz Kaviani, Ömer Oralkan
A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system. 1266-1270 - Brian P. Otis, Jan M. Rabaey:
A 300-μW 1.9-GHz CMOS oscillator utilizing micromachined resonators. 1271-1274 - Nicola Da Dalt, Christoph Sandner:
A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. 1275-1278 - Carlo Tinella, Jean-Michel Fournier, Didier Belot, Vincent Knopik:
A high-performance CMOS-SOI antenna switch for the 2.5-5-GHz band. 1279-1283 - Mihai A. Margarit, David Shih, Patrick J. Sullivan, Fernando Ortega:
A 5-GHz BiCMOS RFIC front-end for IEEE 802.11a/HiperLAN wireless LAN. 1284-1287 - Fabiano Fruett, Gerard C. M. Meijer, Anton Bakker:
Minimization of the mechanical-stress-induced inaccuracy in bandgap voltage references. 1288-1291 - Andrea Baschirotto
A ±1-g dual-axis linear accelerometer in a standard 0.5-μm CMOS technology for high-sensitivity applications. 1292-1297 - Franco Zappa
Monolithic active-quenching and active-reset circuit for single-photon avalanche detectors. 1298-1301
Volume 38, Number 8, August 2003
- Mark Dawkins, Alison Payne Burdett, Nick Cowley:
A single-chip tuner for DVB-T. 1307-1317 - Tirdad Sowlati, Domine M. W. Leenaerts:
A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier. 1318-1324 - Ryan Lee Bunch, Sanjay Raman
Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs. 1325-1332 - Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, N. Garry Tarr:
Design of wide-band CMOS VCO for multiband wireless LAN applications. 1333-1342 - Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator. 1343-1352 - Bernabé Linares-Barranco
On the design and characterization of femtoampere current-mode circuits. 1353-1363 - Juan M. Carrillo
Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries. 1364-1372 - Robert Rieger
Design of a low-noise preamplifier for nerve cuff electrode recording. 1373-1379 - Ming-Dou Ker, Kuo-Chun Hsu:
Latchup-free ESD protection design with complementary substrate-triggered SCR devices. 1380-1392 - Sohrab Samadian, Ryoji Hayashi, Asad A. Abidi:
Demodulators for a zero-IF Bluetooth receiver. 1393-1396 - Bo Xia, Chunyu Xin, Wenjun Sheng, Ari Yakov Valero-López, Edgar Sánchez-Sinencio:
A GFSK demodulator for low-IF Bluetooth receiver. 1397-1400 - Dong-Young Chang, Un-Ku Moon:
A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique. 1401-1404 - Yunchu Li, Edgar Sánchez-Sinencio:
A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC. 1405-1410 - Lei Wang, Sherif H. K. Embabi:
Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper. 1411-1415 - Paolo Bruschi
A high current drive CMOS output stage with a tunable quiescent current limiting circuit. 1416-1420 - Jinup Lim, Sungwon Noh, Kwangoh Kim, Joongho Choi:
A 3.3-V ISDN U-interface line driver with a new IQ-control circuit. 1421-1424 - Orly Yadid-Pecht, Alexander Belenky:
In-pixel autoexposure CMOS APS. 1425-1428
Volume 38, Number 9, September 2003
- Alexandre Bessemoulin, Rüdiger Quay
A 4-W X-band compact coplanar high-power amplifier MMIC with 18-dB gain and 25% PAE. 1433-1437 - Simon Desgrez, Dominique Langrez, Magali Delmond, Jean-Christophe Cayrou, Jean-Louis Cazaux:
A new MMIC sampling phase detector design for space applications. 1438-1442 - Arvind Raghavan, Sunitha Venkataraman, Bhaskar Banerjee, Youngsuk Suh, Deukhyoun Heo, Joy Laskar:
Direct extraction of an empirical temperature-dependent InGaP/GaAs HBT large-signal model. 1443-1450 - Miguel Urteaga, Dennis W. Scott, Sundararajan Krishnan, Yun Wei, Mattias Dahlström, Zach Griffith, Navin Parthasarathy, Mark J. W. Rodwell:
G-band (140-220-GHz) InP-based HBT amplifiers. 1451-1456 - Valery S. Kaper, Vinayak Tilak, Hyungtak Kim
High-power monolithic AlGaN/GaN HEMT oscillator. 1457-1461 - Reza Tayrani, Mary A. Teshiba, Glenn M. Sakamoto, Q. Chaudhry, R. Alidio, Yoosin Kang, Imad S. Ahmad, Terry C. Cisco, M. Hauhe:
Broad-band SiGe MMICs for phased-array radar applications. 1462-1470 - Alvin J. Joseph, James S. Dunn, Greg G. Freeman, David L. Harame, Douglas Coolbaugh, Robert A. Groves, Kenneth J. Stein, Rich Volant, Seshadri Subbanna, V. S. Marangos, Stephen St. Onge, Ebenezer Eshun, P. Cooper, Jeffrey B. Johnson, Jae-Sung Rieh, Basanth Jagannathan, Vidhya Ramachandran, David Ahlgren, Dawn Wang, X. Wang:
Product applications and technology directions with SiGe BiCMOS. 1471-1478 - Satoshi Masuda, Tsuyoshi Takahashi, Kazukiyo Joshin:
An over-110-GHz InP HEMT flip-chip distributed baseband amplifier with inverted microstrip line structure for optical transmission system. 1479-1484 - Douglas S. McPherson, Florin Pera, Mihai Tazlauanu, Sorin P. Voinigescu:
A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems. 1485-1496 - Andre Hendarman, Emilio A. Sovero, Kevin Witt, Xin Xu:
STS-768 multiplexer with full-rate output data retimer in InP HBT. 1497-1503 - Kimikazu Sano, Koichi Murata, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki:
50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs. 1504-1511 - Joseph S. Weiner, Andreas Leven, Vincent Houtsma, Yves Baeyens, Young-Kai Chen, Peter Paschke, Yang Yang, John Frackoviak, Wei-Jer Sung, Alaric Tate, Roberto Reyes, Rose F. Kopf, Nils Weimann
SiGe differential transimpedance amplifier with 50-GHz bandwidth. 1512-1517 - Charles Q. Wu, Emilio A. Sovero, Bruce Massey:
40-GHz transimpedance amplifier with differential outputs using InP-InGaAs heterojunction bipolar transistors. 1518-1523 - Michael Inerfield, William Skones, Steve Nelson, Daniel Ching, Peter Cheng, Colin Wong:
High dynamic range InP HBT delta-sigma analog-to-digital converters. 1524-1532 - Jaesik Lee, Andreas Leven, Joseph S. Weiner, Yves Baeyens, Yang Yang, Wei-Jer Sung, John Frackoviak, Rose F. Kopf, Young-Kai Chen:
A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology. 1533-1539 - Mehran Mokhtari, Charles H. Fields, Rajesh D. Rajavel, Marko Sokolich, Joseph F. Jensen, William E. Stanchina
100+ GHz static divide-by-2 circuit in InP-DHBT technology. 1540-1544 - Mehran Mokhtari, Charles H. Fields, Rajesh D. Rajavel, Marko Sokolich, Joseph F. Jensen, William E. Stanchina Plett:
A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO. 1547-1554 - Scott K. Reynolds, Brian A. Floyd
A direct-conversion receiver IC for WCDMA mobile systems. 1555-1560 - Sudhir Aggarwal, Anton Daanen, Matthias Locher, Alan L. Landesman, Marc Judson, Fabien Garrigues, Mark Bracey, Haiming Xu, Olivier Charlon, Minzhan Gao:
A highly integrated dual-band triple-mode transmit IC for cellular CDMA2000 applications. 1561-1569 - Duljit S. Malhi, Lawrence E. Larson, Dawn Wang, Cuneyt Demirdag, Victoria Pereira:
SiGe W-CDMA transmitter for mobile terminal application. 1570-1574 - Marco Spirito
Power amplifier PAE and ruggedness optimization by second-harmonic control. 1575-1583 - Jonathan C. Jensen, Lawrence E. Larson:
A 16-GHz ultra-high-speed Si-SiGe HBT comparator. 1584-1589
Volume 38, Number 10, October 2003
- Lindor Henrickson, David Shen, Uno Nellore, Alan Ellis, Joong Oh, Hui Wang, Giovanni Capriglione, Ali Atesoglu, Alice Yang, Peter Wu, Syed Quadri, David Crosbie:
Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-μm CMOS. 1595-1601 - Udo Karthaus, Martin Fischer:
Fully integrated passive UHF RFID transponder IC with 16.7-μW minimum RF input power. 1602-1608 - Sangjin Byun
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. 1609-1618 - Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi
A four-input beam-forming downconverter for adaptive antennas. 1619-1625 - Shenggao Li
A 10-GHz CMOS quadrature LC-VCO for multirate optical applications. 1626-1634 - Jouko Vankka, Johan Sommarek, Jaakko Ketola, Ilari Teikari, Kari A. I. Halonen:
A digital quadrature modulator with on-chip D/A converter. 1635-1642 - Joseph M. C. Wong, Vincent S. L. Cheung, Howard C. Luong
A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-μm CMOS process. 1643-1648 - Yongchul Song, Beomsup Kim:
Low-jitter digital timing recovery techniques for CAP-based VDSL applications. 1649-1656 - Pieter Rombouts, Jeroen De Maeyer, Ludo Weyten:
A 250-kHz 94-dB double-sampling ΣΔ modulation A/D converter with a modified noise transfer function. 1657-1662 - Cheng-Chung Hsu, Jieh-Tsorng Wu:
A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier. 1663-1670 - Michael W. Baker, Rahul Sarpeshkar:
A low-power high-PSRR current-mode microphone preamplifier. 1671-1678 - Stephen C. DeMarco, Wentai Liu, Praveen R. Singh, Gianluca Lazzi, Mark S. Humayun, James D. Weiland
An arbitrary waveform stimulus circuit for visual prostheses using a low-area multibias DAC. 1679-1690 - Ka Nang Leung
A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. 1691-1702 - Young-Don Bae, Seong-Il Park, In-Cheol Park
A single-chip programmable platform based on a multithreaded processor and configurable logic clusters. 1703-1711 - Chua-Chin Wang, Po-Ming Lee, Kuo-Long Chen:
An SRAM design using dual threshold voltage transistors and low-power quenchers. 1712-1720 - TianRui Ying, Wing-Hung Ki
Area-efficient CMOS charge pumps for LCD drivers. 1721-1725 - Seong-Ik Cho, Jung-Hwan Lee, Hong-June Park, Gyu-Ho Lim, Young-Hee Kim:
Two-phase boosted voltage generator for low-voltage DRAMs. 1726-1729 - Mark Lemkin:
A 200-V high-voltage amplifier using a parasitic field-oxide transistor for voltage feedback. 1730-1734 - Kin-Pui Ho, Cheong-Fat Chan, Chiu-Sing Choy, Kong-Pang Pun:
Reversed nested Miller compensation with voltage buffer and nulling resistor. 1735-1738 - Hoi Lee, Ka Nang Leung
A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation. 1739-1744 - Mingdeng Chen, José Silva-Martínez, Shahriar Rokhsaz, Moises E. Robinson:
A 2-Vpp 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning. 1745-1749 - Serhii M. Zhak, Michael W. Baker, Rahul Sarpeshkar:
A low-power wide dynamic range envelope detector. 1750-1753 - Yaowu Mo, Tsunehisa Tanaka, Shigeru Arita, Akira Tsuchitani, Koji Inoue, Yoshihiko Suzuki:
Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming. 1754-1757 - Yijun Zhou, Jiren Yuan:
An 8-bit 100-MHz CMOS linear interpolation DAC. 1758-1761 - Marc Goldfarb, Ed Balboni, John Cavey:
Even harmonic double-balanced active mixer for use in direct conversion receivers. 1762-1766 - Frank Herzel, Gunter Fischer, Hans Gustat:
An integrated CMOS RF synthesizer for 802.11a wireless LAN. 1767-1770 - David D. Hwang, Dengwei Fu, Alan N. Willson Jr.:
A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-μm CMOS. 1771-1775
Volume 38, Number 11, November 2003
- Simon Segars, Ali Sheikholeslami, Stephen Fischer:
Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC]. 1791-1794 - John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas:
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. 1795-1803 - Mozhgan Mansuri, Chih-Kong Ken Yang:
A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation. 1804-1812 - Frank O'Mahony, C. Patrick Yue, Mark A. Horowitz, S. Simon Wong:
A 10-GHz global clock distribution using coupled standing-wave oscillators. 1813-1820 - Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, Deog-Kyoon Jeong:
A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization. 1821-1829 - Daniel Kehrer, Hans-Dieter Wohlmuth, Herbert Knapp, Martin Wurzer, Arpad L. Scholtz:
40-Gb/s 2: 1 multiplexer and 1: 2 demultiplexer in 120-nm standard CMOS. 1830-1837 - James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De:
Dynamic sleep transistor and body bias for active leakage power control of microprocessors. 1838-1845 - Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu:
A 400-MT/s 6.4-GB/s multiprocessor bus interface. 1846-1856 - Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu:
A 2× load/store pipe for a low-power 1-GHz embedded processor. 1857-1865 - Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar:
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. 1866-1875 - Andrea Lodi, Mario Toma, Fabio Campi, Andrea Cappelli, Roberto Canegallo, Roberto Guerrieri:
A VLIW processor with reconfigurable instruction set for embedded applications. 1876-1886 - Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer:
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. 1887-1895 - Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama:
A 1.3-GHz fifth-generation SPARC64 microprocessor. 1896-1905 - Gitae Jeong, Wooyoung Cho, Sujin Ahn, Hongsik Jeong, Gwanhyeob Koh, Youngnam Hwang, Kinam Kim:
A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme. 1906-1910 - Shinichiro Shiratake, Tadashi Miyakawa, Yoshiaki Takeuchi, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Kohei Oikawa, Tohru Ozaki, Iwao Kunishima, Koji Yamakawa, Shigeki Sugimoto, Daisaburo Takashima, Hans-Oliver Joachim, Norbert Rehm, Joerg Wohlfahrt, Nicolas Nagel, Gerhard Beitel, Michael Jacob, Thomas Roehr:
A 32-Mb chain FeRAM with segment/stitch array architecture. 1911-1919 - Mark Johnson, Ali Al-Shamma, Derek Bosch, Matthew Crowley, Michael Farmwald, Luca Fasoli, Alper Ilkbahar, Bendik Kleveland, Thomas H. Lee, Tz-Yi Liu, Quang Nguyen, Roy Scheuerlein, Kenneth So, Tyler Thorp:
512-Mb PROM with a three-dimensional array of diode/antifuse memory cells. 1920-1928 - Daniel Elmhurst, Matthew Goldman:
A 1.8-V 128-Mb 125-MHz multilevel cell flash memory with flexible read while write. 1929-1933 - June Lee, Sung-Soo Lee, Oh-Suk Kwon, Kyeong-Han Lee, Dae-Seok Byeon, In-Young Kim, Kyoung-Hwa Lee, Young-Ho Lim, Byung-Soon Choi, Jong-Sik Lee, Wang-Chul Shin, Jeong-Hyuk Choi, Kang-Deog Suh:
A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications. 1934-1942 - Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun:
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. 1943-1951 - Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi:
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. 1952-1957 - Igor Arsovski, Ali Sheikholeslami:
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories. 1958-1966 - Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto:
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. 1967-1973 - Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier:
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. 1974-1980 - Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa:
A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. 1981-1991 - Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda:
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. 1992-2000 - Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa:
A single-chip 802.11a MAC/PHY with a 32-b RISC processor. 2001-2009 - Vincent C. Gaudet
A 13.3-Mb/s 0.35-μm CMOS analog turbo decoder IC with a configurable interleaver. 2010-2015
Volume 38, Number 12, December 2003
- Lalitkumar Nathawad, Ryohei Urata, Bruce A. Wooley, David A. B. Miller
A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling. 2021-2030 - Byung-Moo Min, Peter Kim, Frederick W. Bowman III, David M. Boisvert, Arlo J. Aude:
A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC. 2031-2039 - Boris Murmann
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. 2040-2050 - Yonghua Cong, Randall L. Geiger:
A 1.5-V 14-bit 100-MS/s self-calibrated DAC. 2051-2060 - YuQing Yang, Amiya Chokhawala, Mark Alexander, John Melanson, Dylan Hester:
A 114-dB 68-mW Chopper-stabilized stereo multibit audio ADC in 5.62 mm2. 2061-2068 - Robert H. M. van Veldhoven:
A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver. 2069-2076 - Alfio Zanchi, Frank (Ching-Yuh) Tsay, Ioannis Papantonopoulos:
Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS. 2077-2086 - Sanjeev Ranganathan, Yannis Tsividi:
Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results. 2087-2093 - Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura:
A CMOS multichannel 10-Gb/s transceiver. 2094-2100 - Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan:
A second-order semidigital clock recovery circuit based on injection locking. 2101-2110 - Bryan Casper, Aaron Martin, James E. Jaussi, Joe Kennedy, Randy Mooney:
An 8-Gb/s simultaneous bidirectional link with on-die waveform capture. 2111-2120 - Jared L. Zerbe, Carl W. Werner
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. 2121-2130 - Hui Wu, José A. Tierno, Petar K. Pepeljugoski, Jeremy Schaub, Sudhir M. Gowda, Jeffrey A. Kash, Ali Hajimiri
Integrated transversal equalizers in high-speed fiber-optic systems. 2131-2137 - Sherif Galal, Behzad Razavi:
10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology. 2138-2146 - Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman:
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. 2147-2154 - Adrian Ong, Saied Benyamin, Jason Cancio, Vincent Condito, Tad Labrie, Qinghung Lee, John Paul Mattia, Derek K. Shaeffer, Arvin Shahani, Xiaomin Si, Hai Tao, Maurice Tarsia, Wayne Wong, Min Xu:
A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1: 16 demultiplexer in SiGe technology. 2155-2168 - Hai Tao, Derek K. Shaeffer, Min Xu, Saied Benyamin, Vincent Condito, Steffen Kudszus, Qinghung Lee, Adrian Ong, Arvin Shahani, Xiaomin Si, Wayne Wong, Maurice Tarsia:
40-43-Gb/s OC-768 16: 1 MUX/CMU chipset with SFI-5 compliance. 2169-2180 - Jri Lee, Behzad Razavi:
A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology. 2181-2190 - Kenneth Maclean, Marco Corsi, Richard K. Hester, James Quarfoot, Peter Melsa, Robert L. Halbach, Carmen Kozak, Tobin Hagan:
A 610-mW zero-overhead class-G full-rate ADSL CO line driver. 2191-2200 - Ara Bicakci, Chun-Sup Kim, Sang-Soo Lee:
A CMOS line driver for ADSL central office applications. 2201-2208 - Arya Behzad, Zhong Ming Shi, Seema Butala Anand, Li Lin, Keith A. Carter, Michael S. Kappes, Tsung-Hsien Lin
A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard. 2209-2220 - Iason Vassiliou, Kostis Vavelidis, Theodore Georgantas, Sofoklis Plevridis, Nikos Haralabidis, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Yiannis Kokolakis, Panagiotis Merakos, Jacques C. Rudell, Akira Yamanaka, Stamatis Bouras, Ilias Bouras:
A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN. 2221-2231 - Pengfei Zhang, Thai Nguyen, Christopher Lam, Douglas Gambetta, Theerachet Soorapanth, Baohong Cheng, Siegfried Hart, Isaac Sever, Taoufik Bourdi, Andrew (KhongMeng) Tham, Behzad Razavi:
A 5-GHz direct-conversion CMOS transceiver. 2232-2238 - Jürgen Rogin, Ilian Kouchev, Gabriel Brenna, David Tschopp, Qiuting Huang:
A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-μm CMOS. 2239-2248 - Eric Duvivier, Gianni Puccio, Stefano Cipriani, Lorenzo Carpineto, Paolo Cusinato, Biagio Bisanti, Fabrice Galant, Frédéric Chalet, Francesco Coppola, Sever Cercelaru, Nathalie Vallespin, Jean-Christophe Jiguet, Gugliemo Sirna:
A fully integrated zero-IF transceiver for GSM-GPRS quad-band application. 2249-2257 - Pilsoon Choi, Hyung Chul Park, Sohyeong Kim, Sungchung Park, Ilku Nam, Tae Wook Kim, Seokjong Park, Sangho Shin, Myeung Su Kim, Kyucheol Kang, Yeonwoo Ku, Hyokjae Choi, Sook Min Park, Kwyro Lee:
An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz. 2258-2268 - Joel L. Dawson, Thomas H. Lee:
Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system. 2269-2279 - Wim Claes, Michel De Cooman, Willy Sansen, Robert Puers
A 136-μW/channel autonomous strain-gauge datalogger. 2280-2287 - Ovidiu Vermesan, Knut H. Riisnæs, Laurent Le Pailleur, Jon B. Nysæther, Mark Bauge, Helge Rustad, Sigmund Clausen, Lars-Cyril Julin Blystad, Hanne Grindvoll, Rune Pedersen, Robert Pezzani, David Kaire:
A 500-dpi AC capacitive hybrid flip-chip CMOS ASIC/sensor module for fingerprint, navigation, and pointer detection with on-chip data processing. 2288-2296 - Nicolò Manaresi, Aldo Romani, Gianni Medoro, Luigi Altomare, Andrea Leonardi, Marco Tartagni, Roberto Guerrieri:
A CMOS chip for individual cell manipulation and detection. 2297-2305 - Björn Eversmann, Martin Jenkner, Franz Hofmann, Christian Paulus, Ralf Brederlow
A 128 × 128 CMOS biosensor array for extracellular recording of neural activity. 2306-2317 - Daniel Saias, Philippe Robert
An above IC MEMS RF switch. 2318-2324 - Pierre-François Rüedi, Pascal Heim, François Kaess, Eric Grenet, Friedrich Heitger, Pierre-Yves Burgi
A 128 × 128 pixel 120-dB dynamic-range vision-sensor chip for image contrast and orientation extraction. 2325-2333 - Sherif Galal, Behzad Razavi:
Broadband ESD protection circuits in CMOS technology. 2334-2340 - S. Nielsen, J. C. Yen, N. K. Srivastava, J. E. Rogers, M. G. Case, R. Thiagarajah:
A fully integrated 43.2-Gb/s clock and data recovery and 1: 4 demux IC in InP HBT technology. 2341-2346
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