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ISCAS 2015: Lisbon, Portugal
- 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015. IEEE 2015, ISBN 978-1-4799-8391-9
A0L-A: Plenary
- Behzad Razavi:
The future of radios. 1-8
A1L-A: Special Session: Device-Circuit-System Integration Using Emerging Memory
- Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici:
Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. 9-12 - Tetsuo Endoh:
Nonvolatile logic and memory devices based on spintronics. 13-16 - Hai Li
, Beiye Liu, Xiaoxiao Liu
The applications of memristor devices in next-generation cortical processor designs. 17-20 - Jing Li
Enabling phase-change memory for data-centric computing: Technology, circuitand system. 21-24
A1L-B: Special Session: Embedded Security and Trustable Integrated Circuits, Systems and Infrastructures
- Li Zhang, Chip-Hong Chang
Public key protocol for usage-based licensing of FPGA IP cores. 25-28 - Mohammad-Mahdi Bidmeshki, Yiorgos Makris
VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation. 29-32 - Teng Xu, Miodrag Potkonjak:
Stable and secure delay-based physical unclonable functions using device aging. 33-36 - Jerry Backer, Sk Subidh Ali
A secure design-for-test infrastructure for lifetime security of SoCs. 37-40
A1L-C: VLSI Datapath and Arithmetic Circuits
- Rahul Parhi
Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR). 41-44 - Vincent Camus
Energy-efficient inexact speculative adder with high performance and accuracy control. 45-48 - Junghoon Oh, Mineo Kaneko:
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis. 49-52 - Thian Fatt Tay, Chip-Hong Chang
A new unified modular adder/subtractor for arbitrary moduli. 53-56
A1L-D: Biomedical Signal Processing
- Celia Shahnaz
Seizure detection exploiting EMD-wavelet analysis of EEG signals. 57-60 - Li Zhang, Ho-Chun Wu, Shing-Chow Chan:
A novel algorithm for time-varying gene regulatory networks identification with biological state change detection. 61-64 - Yumeng Gao, Zhiping Lin, Tongtong Zhang, Nan Liu
Effects of two new features of approximate entropy and sample entropy on cardiac arrest prediction. 65-68 - Amit Acharyya
An accurate clustering algorithm for fast protein-profiling using SCICA on MALDI-TOF. 69-72
A1L-E: Cryptography and Security for Communications Systems
- Haibo Yu, Guoqiang Bai:
An efficient method for integer factorization. 73-76 - Weiqiang Liu, Yifei Yu, Chenghua Wang, Yijun Cui, Máire O'Neill:
RO PUF design in FPGAs with new comparison strategies. 77-80 - André Luiz Pereira de França, Ricardo P. Jasinski, Paulo Cemin, Volnei A. Pedroni, Altair Olivo Santin
The energy cost of network security: A hardware vs. software comparison. 81-84 - Philip Hodgers, Neil Hanley, Máire O'Neill:
Pre-processing power traces to defeat random clocking countermeasures. 85-88
A1L-F: Energy Harvesting
- Jiayi Wang, Yongan Zheng, Shi Wang, Maoqiang Liu, Huailin Liao:
Human body channel energy harvesting scheme with -22.5 dBm sensitivity 25.87% efficiency threshold-compensated rectifier. 89-92 - Xing Li, Chi-Ying Tsui
UHF energy harvesting system using reconfigurable rectifier for wireless sensor network. 93-96 - Yang Yang, Xiang Xie, Guolin Li, Yadong Huang, Zhihua Wang:
A combined transmitting coil design for high efficiency WPT of endoscopic capsule. 97-100 - Shuenn-Yuh Lee, Tzung-Min Tsai, Wei-Chih Lai, Soon-Jyh Chang, Stony Tai:
A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system. 101-104
A1L-G: Modelling and Layout Techniques
- Manuel Porcel de Soto, José M. de la Rosa
Simulation-based comparison of CNT-FETs and G-FETs from a circuit designer's perspective. 105-108 - Cheng-Po Chen, Reza Ghandi:
Designing silicon carbide NMOS integrated circuits for wide temperature operation. 109-112 - Steven Bielby, Gordon W. Roberts:
An embedded probabilistic extraction unit for on-chip jitter measurements. 113-116 - Fábio Passos
Physical vs. surrogate models of passive RF devices. 117-120
A1L-H: Visual Signal Processing, Modeling and Enhancement
- Hamidreza Sadreazami, M. Omair Ahmad, M. N. Shanmukha Swamy:
Despeckling of synthetic aperture radar images in the contourlet domain using the alpha-stable distribution. 121-124 - Ke Gu, Shiqi Wang
Screen image quality assessment incorporating structural degradation measurement. 125-128 - Jing Mu, Ruiqin Xiong, Xiaopeng Fan, Siwei Ma:
Compression artifact reduction for low bit-rate images based on non-local similarity and across-resolution coherence. 129-132 - Chong Wang, Zhouchi Lin, Shing-Chow Chan:
Depth map restoration and upsampling for kinect v2 based on IR-depth consistency and joint adaptive kernel regression. 133-136
A1L-J: Circuit Theory I
- Ding Nie, Bertrand M. Hochwald:
Bandwidth bounds for matching coupled loads. 137-140 - Igor M. Filanovsky
Enhancing amplifiers/filters bandwidth by transfer function zeroes. 141-144 - Cristian E. Onete
Building hamiltonian networks using the cycles laplacian of the underlying graph. 145-148 - Mehrdad A. Ghanad, Catherine Dehollain, Michael M. Green:
Noise analysis for time-domain circuits. 149-152
A1L-K: Oscillators and PLLs I
- Amany El-Gouhary
A quadrature oscillator for LTE/LTE-A standards with an improved quadrature-mode stability. 153-156 - Mahsa Shoaran
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. 157-160 - Juan Pablo Caram, Jeff Galloway, J. Stevenson Kenney:
Harmonic ring oscillator time-to-digital converter. 161-164 - Fan Yang, Runhua Wang, Xiaozhe Liu, Junhua Liu, Huailin Liao:
A high frequency resolution digitally controlled oscillator with differential tapped inductor. 165-168
A1L-L: CAD for Circuits, Devices and Interconnect
- Amir Zjajo, Carlo Galuzzi, Rene van Leuken:
Stochastic noise analysis of neural interface front end. 169-172 - Jeremy Schlachter, Vincent Camus
Automatic generation of inexact digital circuits by gate-level pruning. 173-176 - Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Fast buffer delay estimation considering time-dependent dielectric breakdown. 177-180
A1L-M: Nano-Electronics I
- Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Improved logic synthesis for memristive stateful logic using multi-memristor implication. 181-184 - Qingjiang Li, Hui Xu, Ali Khiat, Zhaolin Sun, Themistoklis Prodromakis
Impact of active areas on electrical characteristics of TiO2 based solid-state memristors. 185-188 - Alexantrou Serb
Limitations and precision requirements for read-out of passive, linear, selectorless RRAM arrays. 189-192 - Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. 193-196
A2P-N: Power and Energy Circuits and Systems
- Carlo Famoso, Mario Di Guardo, Luigi Fortuna, Mattia Frasca, Salvatore Graziani
A system-of-systems based equipment for thermo-mechanical testing of advanced high power modules. 197-200 - Moataz Abdelfattah, Brian Dupaix, Syed R. Naqvi, Waleed Khalil:
A fully-integrated switched capacitor voltage regulator for near-threshold applications. 201-204 - Yidi Zeng, Harald Schrom, Rolf Ernst:
An approach for physical topology exploration in wired bus networks. 205-208 - Nicola Bertoni
Ripple-based power-line communication in switching DC-DC converters exploiting switching frequency modulation. 209-212
A2P-P: DC-DC converters
- Andreas Berger, Matteo Agostinelli, Robert Priewasser, Stefano Marsili, Mario Huemer:
Unified digital sliding mode control with inductor current ripple reconstruction for DC-DC converters. 213-216 - Chiang Liang Kok
A switched capacitor deadtime controller for DC-DC buck converter. 217-220 - Nicola Bertoni
A first implementation of a semi-analytically designed class-E resonant DC-DC converter. 221-224 - Yanqi Zheng, Marco Ho
A fixed-frequency auto-buck-boost SIMO DC-DC converter with duty-cycle redistribution and duty-predicted current control. 225-228 - Agasthya Ayachit, Alberto Reatti, Marian K. Kazimierczuk:
Small-signal modeling of the PWM boost DC-DC converter at boundary-conduction mode by circuit averaging technique. 229-232
A2P-Q: Circuits and Systems for Solar and Wind Energy and Energy Harvesting
- Abhik Das, Yuan Gao
An output feedback-based start-up technique with automatic disabling for battery-less energy harvesters. 233-236 - Yifeng Cai, Yiannos Manoli:
System design of a time-controlled broadband piezoelectric energy harvesting interface circuit. 237-240 - Kota Kato, Hirotaka Koizumi:
A study on effect of blocking and bypass diodes on partial shaded PV string with compensating circuit using voltage equalizer. 241-244 - Xiaozhong Liao, Hang Sun, Zhen Li
Impedance modeling of DFIG-wind turbine system. 245-248
A2P-R: Amplifiers and Comparators
- Prakash Harikumar, J. Jacob Wikner
Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS. 249-252 - María de Rodanas Valero Bernal
Class AB two stage and folded cascode OpAmps based on a squaring circuit. 253-256 - Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih:
A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS. 257-260 - Ana Correia
Design of a robust general-purpose low-offset comparator based on IGZO thin-film transistors. 261-264 - Luis Gerardo de la Fraga, Esteban Tlelo-Cuautle
Optimizing an amplifier by a many-objective algorithm based on R2 indicator. 265-268
A2P-S: Analog Filters II
- Fayrouz Haddad, Wenceslas Rahajandraibe
Design of an optimal layout RF passive polyphase filter for large image rejection. 269-272 - Ali Nikoofard, Siavash Kananian, Baktash Behmanesh
Analysis of imperfections in N-phase high-Q band-pass filters. 273-276 - José María Algueta-Miguel, Carlos Aristoteles De la Cruz-Blas
A 760μW 4th order butterworth FGMOS Gm-C filter with enhanced linearity. 277-280 - Dimitra Psychogiou, Dimitrios Peroulis
Analog signal-interference narrow-band bandpass filters with hybrid transmission-line/SAW-resonator transversal filtering sections. 281-284 - Pedram Payandehnia, Ali Fazli Yeknami, Xin Meng, Chao Yang, Gabor C. Temes:
A passive CMOS low-pass filter for high speed and high SNDR applications. 285-288
A2P-T: Successive Approximation ADCs II
- Monireh Eslami, Mohammad Taherzadeh-Sani
A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS. 289-292 - Yu-Wei Cheng, Kea-Tiong Tang:
A 0.5-V 1.28-MS/s 10-bit SAR ADC with switching detect logic. 293-296 - Domenico Albano, Marco Grassi
A low power 12-Bit ENOB SAR ADC for silicon drift X and gamma ray detector read-out. 297-300 - Jin-Yi Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo, Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin, Chih-Cheng Hsieh:
An 8-bit column-shared SAR ADC for CMOS image sensor applications. 301-304
A2P-U: Sigma-Delta Modulators II
- Mahmoud Sadollahi
Two-stage ΔΣ ADC with noise-coupled VCO-based quantizer. 305-308 - Spencer Leuenberger, Un-Ku Moon:
A single OpAmp 2nd-Order ΔΣ ADC with a double integrating quantizer. 309-312 - Lishan Lv, Qiang Li:
300mV 50kHz 75.9dB SNDR CT ΔΣ Modulator with Inverter-based Feedforward OTAs. 313-316 - Changsok Han, Nima Maghari:
Continuous time delta-sigma modulator with an embedded passive low pass filter. 317-320 - Changsok Han, Taewook Kim, Nima Maghari:
Sturdy-MASH delta-sigma modulator with noise-shaped integrating quantizer and dual-DAC DWA. 321-324 - Rudolf Ritter, Matthias Lorenz, Maurits Ortmanns:
Anti-aliasing filter improvement in continuous-time feedback sigma-delta modulators. 325-328 - Chongjun Ding, Yiannos Manoli, Matthias Keller:
Approaches to mitigating the impact of DAC mismatch on the performance of continuous-time delta-sigma modulators. 329-332
A2P-V: Interface Circuits II
- Yang Wang, Weixin Gai:
A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. 333-336 - Meng Zhao, Wengao Lu, Zhongjian Chen, Tingting Zhang, Feng Wu, Yacong Zhang, Dahe Liu:
A low-noise switched-capacitor interface for a capacitive micro-accelerometer. 337-340 - Jincai Liu, Weixin Gai, Liangxiao Tang:
A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis. 341-344 - Xiaopeng Zhong, Bo Wang
A reconfigurable time-domain comparator for multi-sensing applications. 349-352
A2P-W: Sensory Systems
- J. Illade-Quinteiro, Víctor M. Brea
Dark current optimization of 4-transistor pixel topologies in standard CMOS technologies for time-of-flight sensors. 353-356 - Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura:
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. 357-360 - Nicola Massari
A time-based technique for a resistive detector. 361-364 - Cristina Azcona, Belén Calvo, Nicolás Medrano, Santiago Celma, Cecilia Gimeno:
A 1.2-V 1.35-μW all MOS temperature sensor for wireless sensor networks. 365-368 - Imad Benacer
A novel stereovision algorithm for obstacles detection based on U-V-disparity approach. 369-372
A3L-A: Special Session: Device-Circuit-System Integration Using Emerging Memory - Part-II
- Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang:
Design of threshold logic gates using emerging devices. 373-376 - Yinyin Lin, Rui Yuan, Xiaoyong Xue, B. A. Chen:
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. 377-380 - Yue Zhang, Chao Zhang, Jacques-Olivier Klein
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system. 381-384 - Kai-Shin Li, Ming-Taou Lee, Min-Cheng Chen, Cho-Lun Hsu, J. M. Lu, C. H. Lin, C. C. Chen, B. W. Wu, Y. F. Hou, C. Yi. Lin, Y. J. Chen, T. Y. Lai, M. Y. Li, I. Yang, C. S. Wu, Fu-Liang Yang, W. K. Yeh:
Study of sub-5 nm RRAM, tunneling selector and selector less device. 385-388
A3L-B: Special Session: Cellular Neural/Nonlinear Networks in the 21st Century
- Vanessa Senger, Ronald Tetzlaff
Cellular nonlinear network-based signal prediction in epilepsy: Method comparison. 397-400 - Ákos Zarándy, Csaba Rekeczky, Péter Szolgay, Leon O. Chua:
Overview of CNN research: 25 years history and the current trends. 401-404 - Jörg D. Wichard, Maciej J. Ogorzalek
CNN in drug design - Recent developments. 405-408
A3L-C: SOC, NOC, and Multicore Design Issues
- Zhenqi Wei, Peilin Liu, Rongdi Sun, Rendong Ying:
TAB barrier: Hybrid barrier synchronization for NoC-based processors. 409-412 - Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. 413-416 - Navonil Chatterjee
Fault tolerant mesh based Network-on-Chip architecture. 417-420 - Francisco F. S. Barreto, Alexandre M. Amory
Fault recovery protocol for distributed memory MPSoCs. 421-424 - Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
A shared polyhedral cache for 3D wide-I/O multi-core computing platforms. 425-428
A3L-D: Statistical Signal Processing
- Mahdi Parchami, Wei-Ping Zhu, Benoît Champagne:
A new algorithm for noise PSD matrix estimation in multi-microphone speech enhancement based on recursive smoothing. 429-432 - Jiuwen Cao, Zhiping Lin:
Performance bound of multiple hypotheses classification in compressed sensing. 433-436 - Bijit Kumar Das, Mrityunjoy Chakraborty, Jerónimo Arenas-García
Sparse distributed learning via heterogeneous diffusion adaptive networks. 437-440 - Zhiping Lin, Yau Wong, Raimund J. Ober
Limit of the accuracy of parameter estimation for two molecules moving in close proximity. 441-444 - Marzieh Amini
A new map estimator for wavelet domain image denoising using vector-based hidden Markov model. 445-448
A3L-E: Circuits and Systems for Communications I
- Xinwang Zhang, Yichuang Sun, Zhihua Wang, Baoyong Chi:
A 0.5-30GHz wideband differential CMOS T/R switch with independent bias and leakage cancellation techniques. 449-452 - Mika Pulkkinen, Lasse Aaltonen, Kari Halonen:
SPI interface, mux-based synchronizer and DSP unit for a MEMS-based accelerometer. 453-456 - Manas Kumar Hati
Efficient design technique for pulse swallow based fractional-N frequency divider. 457-460 - Naga Rajesh, Shanthi Pavan:
Programmable analog pulse shaping for ultra-wideband applications. 461-464 - Alessandra Pipino
Bluetooth low energy receiver system design. 465-468
A3L-F: CMOS Lab-on-Chip
- José Luis Merino, Onur Kazanc, Nicolas Brunner, Vincent Schlageter, Michel Demierre, Catherine Dehollain:
Low power receiver for magnetic digestive motility tracking pill. 469-472 - Hossein Pourmodheji, Ebrahim Ghafar-Zadeh, Sebastian Magierowski:
Active nuclear magnetic resonance probe: A new multidiciplinary approach toward highly sensitive biomolecoular spectroscopy. 473-476 - Khandaker A. Al Mamun, Nicole McFarlane:
A CMOS potentiostatic glucose monitoring system for VACNF amperometric biosensors. 477-480 - Nicolas Moser
A novel pH-to-time ISFET pixel architecture with offset compensation. 481-484 - Haitao Li, Sam Boling, Andrew J. Mason:
Power efficient instrumentation with 100 fA-sensitivity and 164 dB-dynamic range for wearable chronoamperometric gas sensor arrays. 485-488
A3L-G: Regulators & References I
- Edward K. F. Lee:
A low voltage CMOS differential/floating bandgap voltage reference circuit. 489-492 - André Luiz Aita, Jorge V. de la Cruz, Rizwan Bashirullah:
A 0.45V CMOS relaxation oscillator with ±2.5% frequency stability from -55°C to 125°C. 493-496 - Oscar E. Mattia, Hamilton Klimach, Sergio Bampi
0.7 V supply self-biased nanoWatt MOS-only threshold voltage monitor. 497-500 - Jize Jiang, Wei Shu, Joseph Sylvester Chang, Jingyuan Liu:
A novel subthreshold voltage reference featuring 17ppm/°C TC within -40°C to 125°C and 75dB PSRR. 501-504 - Arjun Ramaswami Palaniappan, Dominic Maurath, Felix Kalathiparambil, Liter Siek
A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. 505-508
A3L-H: HEVC, Standard Video Coding
- Miaohui Wang, King Ngi Ngan, Hongliang Li, Huanqiang Zeng:
Improved block level adaptive quantization for high efficiency video coding. 509-512 - Christian Herglotz, Elisabeth Walencik, André Kaup
Estimating the HEVC decoding energy using the decoder processing time. 513-516 - Longfei Gao, Shengfu Dong, Wenmin Wang, Ronggang Wang, Wen Gao:
Fast intra mode decision algorithm based on refinement in HEVC. 517-520 - Kai Zhang, Jicheng An, Xianguo Zhang, Han Huang
Symmetric intra block copy in video coding. 521-524 - Li Li, Houqiang Li, Zhuoyi Lv, Haitao Yang:
An affine motion compensation framework for high efficiency video coding. 525-528
A3L-J: Circuit Theory II
- Paul G. A. Jespers, Boris Murmann
Calculation of MOSFET distortion using the transconductance-to-current ratio (gm/ID). 529-532 - Nikolay V. Kuznetsov
Limitations of the classical phase-locked loop analysis. 533-536 - Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia, Jyun-Jie Huang:
Simulating delta-sigma analog-to-digital converters with the Op-Amp nonlinearity using the Newton's method. 537-540 - Sameed Hameed
Frequency-domain analysis of a mixer-first receiver using conversion matrices. 541-544
A3L-K: Oscillators and PLLs II
- Amer Samarah, Anthony Chan Carusone
Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition. 545-548 - Susan M. Schober, John Choma Jr.:
A 1.25mW 0.8-28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS. 549-552 - Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen:
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. 553-556 - Shuei Morishita, Shinji Shimizu, Takao Kihara, Tsutomu Yoshimura:
Subharmonically injection-locked PLL with variable pulse-width injections. 557-560 - Sergio Callegari, Federico Bizzarri
Optimal quantization noise management in wideband fractional-N PLLs. 561-564
A3L-L: Other Topics in Neural Systems
- Bilal Mirza, Zhiping Lin, Jiuwen Cao, Xiaoping Lai:
Voting based weighted online sequential extreme learning machine for imbalance multi-class classification. 565-568 - Xiaobing Nie, Wei Xing Zheng, Jinhu Lu
Stability analysis of multiple equilibria for recurrent neural networks with discontinuous Mexican-hat-type activation function. 569-572 - Etienne Dumesnil, Frederic Nabki
RF-LNA circuit synthesis using an array of artificial neural networks with constrained inputs. 573-576 - Hugues Wouafo, Cyrille Chavet
Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. 577-580 - Jafar Shamsi
Hyperbolic tangent passive resistive-type neuron. 581-584
A3L-M: Nano-Electronics II
- Qing Dong, Kaiyuan Yang
Racetrack converter: A low power and compact data converter using racetrack spintronic devices. 585-588 - Nicolas Locatelli, Damir Vodenicarevic, Weisheng Zhao, Jacques-Olivier Klein
Vortex-based spin transfer oscillator compact model for IC design. 589-592 - Zheng Li, Bonan Yan, Lun Yang, Weisheng Zhao, Yiran Chen, Hai Li
A new self-reference sensing scheme for TLC MRAM. 593-596 - Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel:
Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. 597-600 - Vita Pi-Ho Hu
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. 601-604
A4L-B: Special Session: Efficient Circuits and Systems for HEVC and its 3D Encoding Extension
- Wei Cheng, Yibo Fan, YanHeng Lu, Yize Jin, Xiaoyang Zeng:
A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application. 605-608 - Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
An independent bandwidth reduction device for HEVC VLSI video system. 609-612 - Jörg Henkel, Muhammad Usman Karim Khan, Muhammad Shafique
Energy-efficient multimedia systems for high efficiency video coding. 613-616 - Jinjia Zhou
A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio. 617-620 - Mário Saldanha, Gustavo Sanchez
Complexity reduction for the 3D-HEVC depth maps coding. 621-624
A4L-C: VLSI Testing and Testability
- Ayiao Cui, Tingting Yu, Mengyang Li, Gang Qu:
A scan design method based on two complementary connection styles to minimize test power. 625-628 - Aijiao Cui, Tingting Yu, Gang Qu, Mengyang Li:
An improved scan design for minimization of test power under routing constraint. 629-632 - Ali Dianat, Ali Attaran, Rashid Rashidzadeh:
Test method for capacitive MEMS devices utilizing pierce oscillator. 633-636 - Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay, Bijit Kumar Das:
A hardware based low temperature solution for VLSI testing using decompressor side masking. 637-640 - Tingting Yu, Aijiao Cui, Mengyang Li, André Ivanov:
A new decompressor with ordered parallel scan design for reduction of test data and test time. 641-644
A4L-D: Low Power Communication Devices
- Iman Kianpour, Bilal Hussain
A low-power multi-tanh OTA with very low harmonic distortion. 645-649 - A. R. Aravinth Kumar, Shiv Govind Singh, Ashudeb Dutta:
Low power reconfigurable multi-mode LNA utilizing subthreshold bias and low-Q inductors. 650-653 - Amir Amirabadi
Highly linear wide-band differential LNA using active feedback as post distortion. 654-657 - Waqas Ahmad, Mohammed Abdulaziz, Markus Törmänen, Henrik Sjöland
CMOS adaptive TIA with embedded single-ended to differential conversion for analog optical links. 658-661 - Yiyu Shen, Woogeun Rhee
A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters. 662-665
A4L-J: Sensor Interface Circuits I
- Olivier Leman, Antonios Nikas, Haiyan Zhou, Jorge-Luis Lagos, Bakul Jitendra Vinchhi, Johann Hauer, Guillaume Jourdan
A versatile analog front-end for sensors based on piezoresistive silicon nanowire detection. 666-669 - Luya Zhang
A 15-bit two-step pixel-level ADC for 17μm-pitch low-power and high-dynamic-range IRFPA. 670-671 - Hai Chu, Wengao Lu, M. X. Liu, Meng Zhao, X. L. Li, Dahe Liu, L. Y. Zhang, Zhongjian Chen, Yacong Zhang:
A low-noise interface for MEMS vibration gyroscope based on a novel power-efficient C/V conversion structure. 674-677 - Daniel DeDorigo
Q-enhancement of a low-power gm-C bandpass filter for closed-loop sensor readout applications. 678-681 - Farah Fahim, Vala Fathipouri, Grzegorz Deptuch
Pixellated readout IC: Analysis for single photon infrared detector for fast time of arrival applications. 682-685
A4L-K: Wireless Power Transfer
- Tomoharu Nagashima, Xiuqin Wei, Elisenda Bou, Eduard Alarcón, Hiroo Sekiya
Analytical design for resonant inductive coupling wireless power transfer system with class-E inverter and class-DE rectifier. 686-689 - Elisenda Bou, Raymond Sedwick
Relay effects in multiple-node Resonant Inductive Coupling Wireless Power Transfer systems. 690-693 - Elisenda Bou, Raymond Sedwick
Scalability analysis of SIMO non-radiative resonant wireless power transfer systems based on circuit models. 694-697 - Xingyi Shi, Aaron N. Parks, Benjamin H. Waters, Joshua R. Smith:
Co-optimization of efficiency and load modulation data rate in a wireless power transfer system. 698-701 - Jean-Paul M. G. Linnartz
Multiple antenna rectifiers for radio frequency energy scavenging in wireless sensors. 702-705
A4L-L: Event-Based Sensors and Processors
- Hua-Sheng, Konstantin Nikolic:
Machine vision using combined frame-based and event-based vision sensor. 706-709 - Roshan Gopalakrishnan, Arindam Basu
Triplet spike time dependent plasticity in a floating-gate synapse. 710-713 - Amitava Banerjee, Sougata Kar, Subhrajit Roy, Aritra Bhaduri, Arindam Basu
A current-mode spiking neural classifier with lumped dendritic nonlinearity. 714-717 - Cheng-Han Li, Christian Brandli, Raphael Berner, Hongjie Liu, Minhao Yang
Design of an RGBW color VGA rolling and global shutter dynamic and active-pixel vision sensor. 718-721 - Hongjie Liu, Christian Brandli, Cheng-Han Li, Shih-Chii Liu, Tobi Delbrück:
Design of a spatiotemporal correlation filter for event-based sensors. 722-725
A4L-M: Object Recognition and Search
- Zhibing Xie, Yun Tie, Ling Guan:
A new audiovisual emotion recognition system using entropy-estimation-based multimodal information fusion. 726-729 - Kim-Hui Yap
Hybrid feature-based wallpaper visual search. 730-733 - Wen Zhang, Kim-Hui Yap
Feature weighting in visual product recognition. 734-737 - Pin Yi Tsai, Yarsun Hsu, Ching-Te Chiu, Tsai-Te Chu:
Accelerating AdaBoost algorithm using GPU for multi-object recognition. 738-741 - Sungpill Choi, Seongwook Park, Gyeonghoon Kim, Hoi-Jun Yoo:
A 124.9fps memory-efficient hand segmentation processor for hand gesture in mobile devices. 742-745
A5P-N: Circuits for Biomedical Applications II
- Nourhan Bayasi, Temesghen Tekeste, Hani H. Saleh
A 65-nm low power ECG feature extraction system. 746-749 - Sherif Ahmed Saleh Mohamed, Yiannos Manoli:
Design of low-power and low-phase noise VCO in standard 0.13μm CMOS. 750-753 - Enyi Yao, Arindam Basu
A 1 V, compact, current-mode neural spike detector with detection probability estimator in 65 nm CMOS. 754-757 - Mustafa Kilic, Alexandre Schmid
An implantable high-voltage cortical stimulator for post-stroke rehabilitation enhancement with high-current driving capacity. 758-761 - Jinghui Liu, Songping Mai, Chun Zhang, Zhihua Wang:
A high-voltage, energy-efficient, 4-electrode output stage for implantable neural stimulator. 762-765
A5P-P: Integrated Biomedical Systems
- Dwaipayan Biswas
Real-time arm movement recognition using FPGA. 766-769 - Hongjie Zhu, Tian Qiu, Milin Zhang, Andrew G. Richardson
Design of a low power impulse-radio ultra-wide band wireless electrogoniometer. 770-773 - Abhishek Srivastava
A novel FM/FSK based receiver front-end for MedRadio spectrum in 401-406 MHz band. 774-777 - Ravi Shrestha
Adaptive illumination in wireless capsule endoscopy system. 778-781 - Biyi Fang, Tao Feng, Mi Zhang, Shantanu Chakrabartty:
Feasibility of B-mode diagnostic ultrasonic energy transfer and telemetry to a cm2 sized deep-tissue implant. 782-785 - Shaojie Su, Jiyang Gao, Hong Chen, Zhihua Wang:
Design of a computer-aided visual system for Total Hip Replacement surgery. 786-789 - Fazal Noor
Distinguishing medical drugs from a large set of side effects using a distributed genetic algorithm on a PC cluster. 790-793
A5P-Q: Algorithms for Biomedical and Lifescience Applications
- Seyed Mohammad Ali Zeinolabedin
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. 794-797 - Gwo Giun Chris Lee, Zuo-Jheng Huang, Chih-Yuan Chen, Chun-Fu Chen:
Implementation of Gabor feature extraction algorithm for electrocardiogram on FPGA. 798-801 - Gabriel Gagnon-Turcotte, Charles-Olivier Dufresne Camaro, Benoit Gosselin
Comparison of low-power biopotential processors for on-the-fly spike detection. 802-805 - Salim Lahmiri, Mounir Boukadoum:
Physiological signal denoising with variational mode decomposition and weighted reconstruction after DWT thresholding. 806-809
A5P-R: VLSI for Signal Processing
- Paraskevas E. Argyropoulos, Hanoch Lev-Ari:
Digital spur mitigation in high-speed block-parallel digital filter realizations. 810-813 - Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark:
Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. 814-817 - Patrick Nsengiyumva, Qiaoyan Yu:
Investigation of single-event upsets in dynamic logic based flip-flops. 818-821 - Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula:
Fast and robust differential flipflops and their extension to multi-input threshold gates. 822-825
A5P-S: VLSI for Data Conversion and Coding
- Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Partial sums computation in polar codes decoding. 826-829 - Héctor Pettenghi
RNS reverse converters based on the new Chinese Remainder Theorem I. 830-833 - Cheng-Rung Tsai, Ming-Chun Hsiao, Wen-Chung Shen, An-Yeu Andy Wu
A 1.96mm2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols. 834-837 - Yajuan He, Ziji Zhang
A fast and energy efficient binary-to-pseudo CSD converter. 838-841 - Dieison Silveira
A real-time architecture for reference frame compression for high definition video coders. 842-845
A5P-T: Nonlinear Circuits and Systems II
- Daisaburo Yoshioka, Yuta Dainobu:
Some properties of sequences generated by Chebyshev polynomials modulo 2k. 846-849 - Bupesh Pandita:
Delay calibration circuit for delay lines. 850-853 - Mamta Yadav, Krishnaiyan Thulasiraman:
Network science meets circuit theory: Kirchhoff index of a graph and the power of node-to-datum resistance matrix. 854-857 - Dongsheng Yu, Ciyan Zheng, Herbert H. C. Iu, Tyrone Fernando
A memristive astable multivibrator based on 555 timer. 858-861 - Karl Freiberger, Martin Wolkerstorfer
Digital predistorter identification based on constrained multi-objective optimization of WLAN standard performance metrics. 862-865 - Josep M. Olm, Domingo Biel:
Exact inversion with a boost DC/AC power converter. 866-869 - Gilles Millerioux, Jérémy Parriaux:
Discrete time-varying delayed systems for secure communication. 870-873
A5P-U: Oscillators and PLLs III
- Xuezhen Wang, Russell E. Radke, Jay E. Ackerman, Michael Baker:
Multimode crystal oscillator for power management unit with digitally controlled AGC loop in 0.18μm CMOS technology. 874-877 - Ehsan Ali, Wenceslas Rahajandraibe
Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling. 878-881 - M. Shahriar Jahan, Tan Yang, Junjie Lu, Jeremy Holleman:
A 167 μW 915 MHz gain-boosted LC VCO. 882-885 - Ping-Yi Wang, Te-Lin Wu, Ming-Yu Chen, Yun-Chun Shen, Yin-Cheng Chang, Da-Chiang Chang, Shawn S. H. Hsu:
A low phase-noise class-C VCO using novel 8-shaped transformer. 886-889 - Song Jia, Shilin Yan, Yuan Wang
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. 890-893 - Xiaoyong Li, Woogeun Rhee
A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path. 894-897
A5P-V: Complex Networks Analysis and Applications II
- Zhihai Rong, Zhi-Xi Wu, Chi Kong Tse
Community structure promotes the emergence of persistence behavior in social networks. 898-901 - Jingyuan Zhan, Xiang Li
Asynchronous consensus of second-order multi-agent systems with aperiodic sampled-data. 902-905 - Jianbo Wang, Xiang Li
Inferring spatial transmission of epidemics in networked metapopulations. 906-909 - Kosuke Oi, Yoko Uwate, Yoshifumi Nishio
Synchronization and clustering in coupled parametrically excited oscillators with small mismatch. 910-913
A6L-B: Special Session: Emergent Applications of Advanced Nonlinear Theory in Smart Grids
- Lin-Yu Lu, Chia-Chi Chu
Consensus-based distributed droop control of synchronverters for isolated micro-grids. 914-917 - Hsiao-Dong Chiang, Tao Wang:
On the number of system separations in power system. 918-921 - Hsiao-Dong Chiang, Tao Wang:
On the continuation-path uniqueness of homotopy enhanced power flow method for general distribution networks with distributed generators. 922-925 - Daniel S. Siqueira, Luís F. C. Alberto, Newton G. Bretas
Generalized energy functions for a class of lossy networking preserving power system models. 926-929 - Chika O. Nwankpa, Juan C. Jiménez, Sachi Jayasuriya:
Observability of network-delayed multi-converter power systems. 930-933
A6L-C: FPGA Based Circuits and Systems
- Chongyan Gu, Máire O'Neill:
Ultra-compact and robust FPGA-based PUF identification generator. 934-937 - Yutaro Ishigaki
An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor. 938-941 - Renyuan Zhang, Mineo Kaneko:
A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism. 942-945 - Basel Halak
Area efficient configurable physical unclonable functions for FPGAs identification. 946-949 - Yuteng Zhou, Zhilu Chen, Xinming Huang:
A pipeline architecture for traffic sign classification on an FPGA. 950-953
A6L-D: DSP Implementation
- Hongxu Yin
Novel real-time system design for floating-point sub-Nyquist multi-coset signal blind reconstruction. 954-957 - Jiajia Chen, Jiatao Ding:
New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT. 958-961 - Xin Lou, Ya Jun Yu:
Area-time efficient realization of multiple constant multiplication. 962-965 - Xin Lou, Pramod Kumar Meher, Ya Jun Yu:
Fine-grained pipelining for multiple constant multiplications. 966-969 - Amey M. Kulkarni, Tinoosh Mohsenin:
Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core. 970-973
A6L-E: SDR/Cognitive Radio Circuits and Systems
- Hoda Abdelsalam, Emad Hegazi, Hassan Mostafa
A tunable multi-band/multi-standard receiver front-end supporting LTE. 974-977 - Kai Shao, Juuso Alhava, Juha Yli-Kaakinen
Fast-convolution implementation of filter bank multicarrier waveform processing. 978-981 - Ahmed K. F. Khattab, Magdy A. Bayoumi:
An overview of IEEE standardization efforts for cognitive radio networks. 982-985 - Saket Srivastava
Real-time blind spectrum sensing using USRP. 986-989 - Baohong Liu, Feiyan Fan, Hai Zhang, Cuiping Zeng:
A wideband down conversion mixer with dual cross-coupled loops for software defined radio. 990-993
A6L-F: Circuits and Systems for Signal Estimation and Learning
- Yih-Chun Cheng, Pei-Yun Tsai:
Low-complexity compressed sensing with variable orthogonal multi-matching pursuit and partially known support for ECG signals. 994-997 - Temesghen Tekeste, Nourhan Bayasi, Hani H. Saleh
Adaptive ECG interval extraction. 998-1001 - Yuqing Dong, W. Kenneth Jenkins:
Theoretical analysis of sequential adaptive processing for fetal electrocardiograms. 1002-1005 - Mohamad Kachuee
Cuff-less high-accuracy calibration-free blood pressure estimation using pulse transit time. 1006-1009 - Tao Xiong, Jie Zhang, Yuanming Suo, Dung N. Tran, Ralph Etienne-Cummings, Sang Chin, Trac D. Tran:
An unsupervised dictionary learning algorithm for neural recordings. 1010-1013
A6L-G: Data Converters I
- Sha Tao, Jiazuo Chi, Ana Rusu
Design considerations for pipelined continuous-time incremental Sigma-Delta ADCs. 1014-1017 - Tao He, Yi Zhang, Xin Meng, Gabor C. Temes, Chia-Hung Chen:
A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface. 1018-1021 - Fang-Ting Chou, Zong-Yi Chen, Hsing-Chien Chu, Chung-Chih Hung:
A novel 12-bit current-steering DAC with two reference currents. 1022-1025 - Jianan Liu, Xueqing Li, Qi Wei, Huazhong Yang:
A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist. 1026-1029 - You Li, Degang Chen:
A novel 20-bit R-2R DAC structure based on ordered element matching. 1030-1033
A6L-H: Visual Tracking and Image Analytics
- Xi-Guang Wei, Shuai Zhang, Shing-Chow Chan:
A novel visual object tracking algorithm using multiple spatial context models and Bayesian Kalman filter. 1034-1037 - Zhong Liu
Multi-view articulated human body tracking with textured deformable mesh model. 1038-1041 - Khosro Bahrami, Alex C. Kot:
Image splicing localization based on blur type inconsistency. 1042-1045 - Xiang Zhang, Shiqi Wang
Towards accurate visual information estimation with Entropy of Primitive. 1046-1049 - Hamidreza Sadreazami, M. Omair Ahmad, M. N. Shanmukha Swamy:
Optimum multiplicative watermark detector in contourlet domain using the normal inverse Gaussian distribution. 1050-1053
A6L-J: Sensor Interface Circuits II
- Suho Son, Shiwon Jeon, Seol Namgung, Jieun Yoo, Minkyu Song:
A one-shot digital correlated double sampling with a differential difference amplifier for a high speed CMOS image sensor. 1054-1057 - Hugo Daniel Hernández
Configurable low noise readout front-end for gaseous detectors in 130nm CMOS technology. 1058-1061 - Jungryoul Choi, Jungwoo Lee, Sangyun Han, Sungwook Kim, Soonwon Hong, Joongho Choi:
A readout circuit with novel zero-g offset calibration for tri-axes capacitive MEMS accelerometer. 1062-1065 - Yen-Ting Wang, Chen Zhao, Degang Chen, Randall L. Geiger:
Direct temperature to digital converters with low supply sensitivity for power/thermal management. 1066-1069 - Qianqian Wang, Randall L. Geiger, Degang Chen:
A programmable temperature trigger circuit. 1070-1073
A6L-K: Circuits & Systems for Energy Harvesting
- Antônio Carlos M. de Queiroz:
Analysis of the operation of a regenerative electrostatic energy harvester. 1074-1077 - Dawei Li, Seda Ogrenci Memik, Lawrence J. Henschen:
On-chip integration of thermoelectric energy harvesting in 3D ICs. 1078-1081 - David Cavalheiro, Francesc Moll
Pespectives of TFET devices in ultra-low power charge pumps for thermo-electric energy sources. 1082-1085 - Jarno Salomaa
Power management system for ultra-low power energy harvesting applications. 1086-1089 - Adrian Enriquez Aguayo, Oliver Paul, Tzeno Galchev:
Integrated synchronous electric charge extraction system for piezoelectric energy harvesters. 1090-1093
A6L-L: Imagers
- Arnaud Peizerat, Fadoua Guezzi Messaoud, Michele Benetti, Antoine Dupret, Remi Jalby, Leonardo Bruno de Sá, William Guicquero
A 3T or 4T pixel compatible DR extension technique suitable for 3D-IC imagers: A 800×512 and 5μm pixel pitch 2D demonstrator. 1094-1097 - Hang Yu, Vigil Varghese, Xinyuan Qian, Menghan Guo, Shoushun Chen, Kay Soon Low
An 8-stage time delay integration CMOS image sensor with on-chip polarization pixels. 1098-1101 - Ion Vornicu
On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique. 1102-1105 - Missael Garcia, Shengkui Gao, Christopher Edmiston, Timothy York, Viktor Gruev:
A 1300 × 800, 700 mW, 30 fps spectral polarization imager. 1106-1109 - Andrew Berkovich, Timir Datta-Chaudhuri
A scalable 20 ×20 fully asynchronous SPAD-based imaging sensor with AER readout. 1110-1113
A6L-M: HEVC Algorithms and Implementations
- Guilherme Corrêa, Pedro A. Amado Assunção
Encoding time control system for HEVC based on Rate-Distortion-Complexity analysis. 1114-1117 - Yaoyao Guo, Bin Li, Songlin Sun, Jizheng Xu:
Rate control for screen content coding in HEVC. 1118-1121 - Falei Luo, Siwei Ma, Juncheng Ma, Honggang Qi, Li Su, Wen Gao:
Multiple layer parallel motion estimation on GPU for High Efficiency Video Coding (HEVC). 1122-1125 - Jian-Liang Lin, Yi-Wen Chen, Jicheng An, Kai Zhang, Yu-Wen Huang
Advanced motion information prediction and inheritance in 3D-HEVC. 1126-1129 - Yi-Wen Chen, Jian-Liang Lin, Yu-Wen Huang
Single depth intra coding mode in 3D-HEVC. 1130-1133
B1L-A: Special Session: Memristor-based Cellular Nanoscale Networks: Theory, Design, and Applications
- Son Ngoc Truong, SangHak Shin, JeaSang Song, Hyun-Sun Mo, Fernando Corinto, Kyeong-Sik Min:
Memristor-based cellular nanoscale networks: Theory, circuits, and applications. 1134-1137 - Alon Ascoli, Ronald Tetzlaff
Stability analysis supports memristor circuit design. 1138-1141 - Hyuncheol Choi, Ram Kaji Budhathoki
Linear programming of voltage-controlled memristors with an anti-serial memristor circuit. 1142-1145 - Panayiotis S. Georgiou, Itir Koymen, Emmanuel M. Drakakis:
Noise properties of ideal memristors. 1146-1149 - Le Zheng, Sangho Shin, Sung-Mo Steve Kang:
Memristor-based synapses and neurons for neuromorphic computing. 1150-1153
B1L-B: Special Session: Electronics Design, Assembly and Reliability for High Temperature Applications
- Lucian-Vasile Stoica, Valentyn Solomko, Thorsten Baumheinrich, Renato Del Regno, Reece Beigh, I. White
Design of a frequency signal conditioning unit applied to rotating systems in high temperature aero engine control. 1154-1157 - S. Riches, Colin Johnston
Electronics design, assembly and reliability for high temperature applications. 1158-1161 - Holger Kappert, Norbert Kordas, Stefan Dreiner, Uwe Paschen, Rainer Kokozinski
High temperature SOI CMOS technology and circuit realization for applications up to 300°C. 1162-1165 - David Shaddock, Liang Yin
High temperature electronics packaging: An overview of substrates for high temperature. 1166-1169 - Liang Yin
Electronic packaging of SiC MOSFET-based devices for reliable high temperature operation. 1170-1173
B1L-C: ASIC & Specialized VLSI Circuits
- Xingyu Liu, Shikai Li, Kuan Fang, Yufei Ni, Zonghui Li, Yangdong Deng:
RadixBoost: A hardware acceleration structure for scalable radix sort on graphic processors. 1174-1177 - Vinh T. Tran, Nagaraj Channarayapatna Shivaramaiah, Oliver Diessel
A programmable multi-GNSS baseband receiver. 1178-1181 - Bo Wang, Leibo Liu
A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing. 1182-1185 - Basant K. Mohanty
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. 1186-1189 - Ediz Cetin
Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets. 1190-1193
B1L-D: Digital Video Processing
- B. K. Shreyamsha Kumar
Structural local DCT sparse appearance model for visual tracking. 1194-1197 - Wei-Cheng Wang
Trajectory kinematics descriptor for trajectory clustering in surveillance videos. 1198-1201 - Renan U. Ferreira
Clustering of matched features and gradient matching for mixed-resolution video super-resolution. 1202-1205 - Luheng Jia, Chi-Ying Tsui
A fast variable block size motion estimation algorithm with refined search range for a two-layer data reuse scheme. 1206-1209 - Ho Sub Lee, Sung In Cho, Gyu Jin Bae, Young Hwan Kim, Hi-Seok Kim:
Foreground-based depth map generation for 2D-to-3D conversion. 1210-1213
B1L-E: Low Power and Wearable Communication Devices
- Shih-En Chen, Chin-Lung Yang, Kuang-Wei Cheng:
A 4.5 μW 2.4 GHz wake-up receiver based on complementary current-reuse RF detector. 1214-1217 - Yosuke Ishikawa, Sang-yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna. 1218-1221 - Vincent Lenoir, Didier Lattard, Ahmed Amine Jerraya:
An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs. 1222-1225 - Marco Silva Pereira
An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. 1226-1229 - Jaeeun Jang, Yongsu Lee, Hyunwoo Cho, Hoi-Jun Yoo:
A 0.54-mW duty controlled RSSI with current reusing technique for human body communication. 1230-1233
B1L-F: Circuits for Biomedical Applications
- Jung-Chen Chung, Wei-Ming Chen, Chung-Yu Wu:
An 8-channel power-efficient time-constant-enhanced analog front-end amplifier for neural signal acquisition. 1234-1237 - Edward K. F. Lee:
A 45V 10-b electrode monitoring analog-to-digital converter. 1238-1241 - Lei Wang, Chun-Huat Heng, Yong Lian
A sub GHz mostly digital BPSK IR UWB transceiver. 1242-1245 - Sheng-En Lin, Shi-Hao Ou, Robert Rieger
Dual-channel pulse-width-modulation ASIC for isolated bio-signal recording front-end. 1246-1249 - Nazanin Neshatvar
An integrated CMOS current driver using nonlinear feedback for bioimpedance applications. 1250-1253
B1L-G: Data Converters II
- Yuki Okada, Takashi Oshima
17-MS/s 9-bit cyclic ADC with gain-assisted MDAC and attenuation-based calibration. 1254-1257 - Eric Gutierrez
Spectral analysis of multibit VCO-ADCs and PFM-ADCs with sinusoidal inputs. 1258-1261 - Abdullah El-Bayoumi
A new highly-linear highly-sensitive differential voltage-to-time converter circuit in CMOS 65nm technology. 1262-1265 - Hourieh Attarzadeh, Sung Kyu Lim
Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study. 1266-1269 - Yue Xu, Ayman Shabra:
A flash-TDC hybrid ADC architecture. 1270-1273
B1L-H: Advanced Image/Video Coding
- Xinfeng Zhang, Yabin Zhang, Weisi Lin, Siwei Ma, Wen Gao:
An inter-image redundancy measure for image set compression. 1274-1277 - Eduarda Monteiro, Mateus Grellert
Rate-distortion and energy performance of HEVC and H.264/AVC encoders: A comparative analysis. 1278-1281 - Yun-Fu Liu, Jing-Ming Guo, Zong-Jhe Wu, Hua Lee:
Near-aperiodic dot-diffused block truncation coding. 1282-1285 - Viet Anh Nguyen, Minh N. Do
Efficient coding unit size selection for HEVC downsizing transcoding. 1286-1289 - Kazunori Uruma, Katsumi Konishi, Tomohiro Takahashi
Color image coding based on the colorization algorithm using multiple resolution images. 1290-1293
B1L-J: Wireless Circuits I
- Somayeh Abdollahvand, Luís Bica Oliveira
A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques. 1294-1297 - Kenneth Maland, Kristian Gjertsen Kjelgård
CMOS distributed amplifiers for UWB radar. 1298-1301 - Samer B. Idres, Mohamed El-Nozahi, Hani Fikry Ragai
A noise cancelling envelope detector for low power wireless sensor applications. 1302-1305 - Waqas Ahmad, Leijun Xu, Markus Törmänen, Henrik Sjöland
A fully integrated 26 dBm linearized RF power amplifier in 65nm CMOS technology. 1306-1309 - Jingjing Dong, Hanjun Jiang, Zhaoyang Weng, Jingyi Zheng, Chun Zhang, Zhihua Wang:
A fast AGC method for multimode zero-IF/sliding-IF WPAN/BAN receivers. 1310-1313
B1L-K: Nonlinear Circuits and Systems I
- Enkhbayasgalan Gantsog, Alyssa B. Apsel, Frank Lane:
A quantized pulse coupled oscillator for slow clocking of peer-to-peer networks. 1314-1317 - A. Brenes, Jérôme Juillard, Laurent Bourgois, F. Vinci dos Santos:
Parameter estimation from nonlinear frequency response of MEMS resonators. 1318-1319 - Panagiotis Giounanlis
Modelling of the dynamical behaviour of floating electrode MEMS. 1322-1325 - Matteo Biggio, Flavio Stellino, Mauro Parodi, Marco Storace:
A low-complexity circuit model of hysteresis. 1326-1329 - Chihiro Ikuta, Yoko Uwate, Yoshifumi Nishio
Multi-layer perceptron with pulse glial chain having oscillatory excitation threshold. 1330-1333
B1L-L: Cellular Nanoscale Networks
- Ari Paasio
Local asymmetric propagation stopper circuit for asynchronous binary wave computing. 1334-1337 - Anne Siemon, Stephan Menzel, Anupam Chattopadhyay, Rainer Waser
In-memory adder functionality in 1S1R arrays. 1338-1341 - Jussi H. Poikonen, Eero Lehtonen
Implementation of nondeterministic finite automata in an autoassociative CAM circuit. 1342-1345 - Declan Walsh, Piotr Dudek:
An event-driven massively parallel fine-grained processor array. 1346-1349 - Mika Laiho
A 512×512-cell associative CAM/Willshaw memory with vector arithmetic. 1350-1353
B1L-M: Integrated Power Circuits and Charge Pumps
- Toru Tanzawa
An analytical model of multi-sine AC-DC voltage multiplier. 1354-1357 - Toru Tanzawa
A comprehensive optimization methodology for designing charge pump voltage multipliers. 1358-1361 - Mohammad Abu Khater, Dimitrios Peroulis
Variable-output charge-pump for piezoelectric and electrostatic tunable RF filters. 1362-1365 - Te-Fu Yang, Ru-Yu Huang, Yi-Ping Su, Balakumar, Ke-Horng Chen
Implantable biomedical device supplying by a 28nm CMOS self-calibration DC-DC buck converter with 97% output voltage accuracy. 1366-1369 - Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang:
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. 1370-1373
B2P-N: Multicore and 3D IC Design Issues
- Arthur Francisco Lorenzon, Márcia C. Cera, Antonio Carlos Schneider Beck:
On the influence of static power consumption in multicore embedded systems. 1374-1377 - Melika Payvand, Advait Madhavan, Miguel Angel Lastras-Montaño, Amirali Ghofrani, Justin Rofeh, Kwang-Ting Cheng
A configurable CMOS memory platform for 3D-integrated memristors. 1378-1381 - Akihisa Yamada, Yan Qian, Masayuki Yamaguchi, Hiroshi Honjoh, Takahiro Morishita, Shunsuke Nagasawa, Shinji Shinjo, Masayuki Miyamoto:
A multi-core architecture of digital back-end for large mutual capacitance touch sensing systems. 1382-1385 - Chien-Hsuan Yen, Chung-Ho Chen, Kuan-Chung Chen:
A memory-efficient NoC system for OpenCL many-core platform. 1386-1389
B2P-P: Interconnects, Clock, Noise Immunity and ESD Protection Session
- Hyunho Baek, William R. Eisenstadt
Design and techniques for on-die power integrity noise measurement system with digital output. 1390-1393 - Yuequan Liu, Yuan Wang
180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. 1394-1397 - Hany Ahmed Fahmy, Ping-Yao Lin, Riadul Islam, Matthew R. Guthaus:
Switched capacitor quasi-adiabatic clocks. 1398-1401 - Benjamin M. LaCara, Ping-Yao Lin, Matthew R. Guthaus:
Multi-frequency resonant clocks. 1402-1405 - Ping-Yao Lin, Hany Ahmed Fahmy, Riadul Islam, Matthew R. Guthaus:
LC resonant clock resource minimization using compensation capacitance. 1406-1409
B2P-Q: Memory Circuits and Architectures III
- Le Zhang, Chip-Hong Chang
Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes. 1410-1413 - Ahmed T. Elthakeb, Thomas Haine, Denis Flandre
Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. 1414-1417 - Noha Shaarawy, Maged Ghoneima, Ahmed G. Radwan
2T2M memristor-based memory cell for higher stability RRAM modules. 1418-1421 - Ali Azarian
Reducing misses to external memory accesses in task-level pipelining. 1422-1425 - Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. 1426-1429
B2P-R: VLSI Datapath, Arithmetic, and Array Circuits
- Jeng-Shyang Pan
Efficient subquadratic parallel multiplier based on modified SPB of GF(2m). 1430-1433 - M. Tarek Ibn Ziad
Finite element emulation-based solver for electromagnetic computations. 1434-1437 - Mustafa Khairallah
New polynomial basis versatile multiplier over GF(2m) for low-power on-chip crypto-systems. 1438-1441 - Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Enhanced level shifter for multi-voltage operation. 1442-1445
B2P-S: VLSI Systems, Architectures and Applications
- Daniel S. Guimarães Jr., Julia Casarin Puget, Ricardo Augusto da Luz Reis
A mixed cells physical design approach. 1446-1449 - Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee:
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. 1450-1453 - Alberto Celin, Andrea Gerosa
Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs. 1454-1457 - Jie Gu, Jieda Li:
Exploration of self-healing circuits for timing resilient design using emerging memristor devices. 1458-1461 - Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino:
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. 1462-1465 - Pascal Nsame, Guy Bois, Yvon Savaria:
Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. 1466-1469
B2P-T: Circuits and Systems for Communications II
- Yasmin Halawani, Baker Mohammad
Memory impact on the lifetime of a Wireless Sensor Node using a Semi-Markov model. 1470-1473
B2P-U: Circuits and Systems for Communications III
- Shenghao Liu, Ke Li, Peter Wilson:
A temperature independent driver for Mach-Zehnder modulators. 1474-1477 - Stefan Trampitsch, Gerhard Knoblinger, Mario Huemer:
Switched state-space model for a switched-capacitor power amplifier. 1478-1481 - Cuili Yang, Zhongyan Fan, Wallace Kit-Sang Tang
Routing design for transmission capacity maximization in complex networks. 1482-1485 - Mouna Ben Mabrouk, Guillaume Ferré, Éric Grivel, Nathalie Deltimple:
A new baseband post-distortion technique for power amplifiers in OFDM-based cognitive radio systems. 1486-1489 - Yizhe Hu
A modeling approach for mixed-mode FMCW synthesizer allowing frequency error analysis. 1490-1493 - Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emanuel M. Popovici, Predrag Ivanis
Efficient realization of probabilistic gradient descent bit flipping decoders. 1494-1497
B2P-V: MIMO Communications Systems II
- Bei Yin, Michael Wu, Joseph R. Cavallaro
VLSI design of large-scale soft-output MIMO detection using conjugate gradients. 1498-1501 - Hemanth Prabhu, Fredrik Rusek, Joachim Neves Rodrigues, Ove Edfors
High throughput constant envelope pre-coder for massive MIMO systems. 1502-1505 - Borislav Milevsky, Myriam Ariaudo, Jean-Luc Gautier, Inbar Fijalkow:
A simplified frequency synthesizer architecture thanks to interference cancellation. 1506-1509 - Oystein Bjorndal, Svein-Erik Hamran, Tor Sverre Lande
UWB waveform generator for digital CMOS radar. 1510-1513
B2P-W: Neural Networks and Systems
- Baris Karakaya, Ramazan Yeniceri
Wave computer core using fixed-point arithmetic. 1514-1517 - Zeynab Mirzadeh, Jean-François Boland, Yvon Savaria:
Modeling the faulty behaviour of digital designs using a feed forward neural network approach. 1518-1521 - Jacopo Secco, Fernando Corinto:
Memristor-based cellular nonlinear networks with belief propagation inspired algorithm. 1522-1525 - Joseph Santarcangelo, Xiao-Ping (Steven) Zhang:
Kernel-based mixture of experts models for linear regression. 1526-1529
B3L-A: Special Session: Exploring Emerging Memories for Energy Efficient Systems
- Lun Yang, Yuanqing Cheng, Yuhao Wang, Hao Yu, Weisheng Zhao, Aida Todri-Sanial
A body-biasing of readout circuit for STT-RAM with improved thermal reliability. 1530-1533 - Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
A case of precision-tunable STT-RAM memory design for approximate neural network. 1534-1537 - Deming Zhang, Lang Zeng, Yuanzhuo Qu, Youguang Zhang, Mengxing Wang, Weisheng Zhao, Tianqi Tang, Yu Wang:
Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning. 1538-1541 - D. Pala, Giovanni Causapruno, Marco Vacca, Fabrizio Riente
Logic-in-Memory architecture made real. 1542-1545
B3L-B: Special Session: Complexity in the Design of Systems-on-a-Chip
- Elena Blokhina
Understanding complexity in multiphysics systems-on-a-chip: Modern approaches for design. 1546-1549 - Edith Beigné
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. 1550-1553 - Hao Zou, Yasser Moursy, Ramy Iskander, Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese:
Substrate noise modeling with dedicated CAD framework for smart power ICs. 1554-1557 - Robert Sobot:
Practical considerations in VLSI IC design flow with respect to tool limitations. 1558-1561
B3L-C: Fault Tolerance and Error Correction in VLSI Circuits
- Vinicius Fochi
An integrated method for implementing online fault detection in NoC-based MPSoCs. 1562-1565 - Qiang Liu, Haie Li:
A hierarchical IP protection approach for hard IP cores. 1566-1569 - Eduardo Wächter, Nicolas Ventroux, Fernando Gehm Moraes
A context saving fault tolerant approach for a shared memory many-core architecture. 1570-1573 - Srinivasa Shashank Nuthakki
Test set customization for improved fault diagnosis without sacrificing coverage. 1574-1577 - Anthi Anastasiou, Yiorgos Tsiatouhas
On the reuse of existing error tolerance circuitry for low power scan testing. 1578-1581 - Zhenbo Lu
Image deblocking via group sparsity optimization. 1582-1585
B3L-D: Digital Image Processing
- Soo-Chang Pei, Yu-Zhe Hsiao:
Spatial Affine transformations of images by using fractional shift fourier transform. 1586-1589 - Jie Chen
Heavy haze removal in a learning framework. 1590-1593 - Yuming Li, Lai-Man Po
No-reference image quality assessment using shearlet transform and stacked autoencoders. 1594-1597
Kong B3L-E: Wireline Communications II
- Travis Bartley, Shuji Tanaka, Yutaka Nonomura, Takahiro Nakayama
Delay window blind oversampling clock and data recovery algorithm with wide tracking range. 1598-1601 - Kyung-Sub Son, Kyongsu Lee
On-chip jitter tolerance measurement technique for CDR circuits. 1602-1605 - Khosrov Dabbagh-Sadeghipour, Paul D. Townsend
Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS. 1606-1609 - Minseo Kim
A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE. 1610-1613 - Woo-Rham Bae
A low-power pulse position modulation transceiver. 1614-1617
B3L-F: CMOS Imagers and Bio applications
- Judyta Tillak, Jerald Yoo
A 23μW digitally controlled pMUT interface circuit for Doppler ultrasound Imaging. 1618-1621 - Shengkui Gao, Suman Mondal
A compact NIR fluorescence imaging system with goggle display for intraoperative guidance. 1622-1625 - Panayiota Demosthenous
A fluorescence based endoscopic microcancer detection capsule. 1626-1629 - Hesong Xu, Matteo Perenzoni, Nicola Massari
A CMOS analog SiPM front-end for positron emission tomography application. 1630-1633 - Lai-Man Po
Frame adaptive ROI for photoplethysmography signal extraction from fingertip video captured by smartphone. 1634-1637 - Allen Waters, Jerry Leung, Manideep Gande, Un-Ku Moon:
A ΔΣ ADC using an LSB-first SAR quantizer. 1638-1641
B3L-G: Data Converters III
- Yin Sun, Victor Adrian, Joseph S. Chang:
Design of a variable-delay window ADC for switched-mode DC-DC converters. 1642-1645 - Alberto Demarziani, Edoardo Bonizzoni, Franco Maloberti, Alessandro D'Amato:
Design of a low power time to digital converter for flow metering applications. 1646-1649 - Junjie Kong, Liter Siek
A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology. 1650-1653 - Jerry Leung, Allen Waters, Un-Ku Moon:
Selectable starting bit SAR ADC. 1654-1657
B3L-H: High Efficiency Video Coding/Communication and Image Processing
- Ming Yang, Jianfei Cai
Adaptive configuration of cloud video transcoding. 1658-1661 - Marko Viitanen
Kvazaar HEVC encoder for efficient intra coding. 1662-1665 - Lien-En Hung, Hsu-Feng Hsiao:
QoS-driven optimization for video streaming using layer-aligned multipriority rateless codes. 1666-1669 - Sheng Shi
Image compressive sensing using overlapped block projection and reconstruction. 1670-1673 - Qiang Song, Ruiqin Xiong, Siwei Ma, Xiaopeng Fan, Wen Gao:
High accuracy sub-pixel image registration under noisy condition. 1674-1677
B3L-J: Wireless Circuits II
- Jiayi Wang, Yongan Zheng, Fan Yang, Fan Tian, Huailin Liao:
A wide band CMOS radio frequency RMS power detector with 42-dB dynamic range. 1678-1681 - Nilan Udayanga, Arjuna Madanayake
Tunable multiband RF CMOS active filter arrays. 1682-1685 - Vladimir Kopta, Raghavasimhan Thirunarayanan, Franz-Xaver Pengg, Erwan Le Roux, Christian C. Enz:
A 2.4-GHz low complexity polar transmitter using dynamic biasing for IEEE 802.15.6. 1686-1689 - Tero Koivisto:
An injection-locked oscillator-multiplier circuitry suitable for MB-OFDM clock generation. 1690-1693 - Omar El-Aassar, Mohamed El-Nozahi, Hani Fikry Ragai
Loss mechanisms and switching performance analysis for efficient mm-Waves Class-E PAs. 1694-1697
B3L-K: Chaos, Bifurcation and Nonlinear Phenomena
- Zbigniew Galias
Detection of all low-period windows for the logistic map. 1698-1700 - Alessandro Colombo
Numerically efficient robustness test for nonlinear circuit models. 1702-1705 - Peter Harte, Eoghan O'Riordan, Elena Blokhina
Universal nonlinear phenomena in a class of electronic oscillators. 1706-1709 - Yining Li, Zhen Li
Bifurcation study of three-phase inverter system with interacting loads. 1710-1713 - Harald Enzinger, Karl Freiberger, Christian Vogel:
Analysis of even-order terms in memoryless and quasi-memoryless polynomial baseband models. 1714-1717
B3L-L: Sensory Systems and Processing
- Alessandro Pezzotta, G. Corradi, G. Croci, Marcello De Matteis
GEMINI: A triple-GEM detector read-out mixed-signal ASIC in 180nm CMOS. 1718-1721 - Gabriel Mujica, Alejandro Garcia, Javier Gordillo, Jorge Portilla, Teresa Riesgo:
A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems. 1722-1725 - Nuwan Ganganath
Distributed anti-flocking control for mobile surveillance systems. 1726-1729 - Mohamed Afifi, Michael Maurer, Thorsten Hehn, Armin Taschwer, Yiannos Manoli:
An automatic tuning technique for background frequency calibration in gyroscope interfaces based on high order bandpass Delta-Sigma modulators. 1730-1733 - Diederik Paul Moeys, Tobias Delbrück, Shih-Chii Liu:
Current-mode automated quality control cochlear resonator for bird identity tagging. 1734-1737
B3L-M: High Efficiency Converters and Drive Circuits
- Sebastian Höppner, Stefan Hänzsche, Stefan Scholze, René Schüffny:
An all-digital PWM generator with 62.5ps resolution in 28nm CMOS technology. 1738-1741 - Tobias Funk, Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht
A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching. 1742-1745 - Hsin Chen, Chi-Wei Chen, Hsueh-Yi Hsieh, Ke-Horng Chen
Self-adjustable feed-forward control and auto-tracking off-time control techniques for 95% accuracy and 95% efficiency AC-DC non-isolated LED driver. 1746-1749 - Ziang Chen, Yat-To Wong, Tak-Sang Yim, Wing-Hung Ki
A 12A 50V half-bridge gate driver for enhancement-mode GaN HEMTs with digital dead-time correction. 1750-1753 - Tsung-Hsun Tsai, Ke-Horng Chen
99% High accuracy knee voltage detection for primary-side control in flyback converter. 1754-1757
B4L-B: Special Session: Wireless Bio-Electronic Interfaces for in-Vivo Studies
- Gabriel Gagnon-Turcotte, Charles-Olivier Dufresne Camaro, Alireza Avakh Kisomi, Reza Ameli, Benoit Gosselin
A wireless multichannel optogenetic headstage with on-the-fly spike detection. 1758-1761 - Ghazal Nabovati, Ebrahim Ghafar-Zadeh, Mohamad Sawan:
A 64 pixel ISFET-based biosensor for extracellular pH gradient monitoring. 1762-1765 - Shahab Shahdoost, Pedram Mohseni:
An FPGA platform for generation of stimulus triggering based on intracortical spike activity in brain-machine-body interface (BMBI) applications. 1766-1769 - Byunghun Lee, Maysam Ghovanloo, Dukju Ahn:
Towards a three-phase time-multiplexed planar power transmission to distributed implants. 1770-1773 - Sandro Carrara, Camilla Baj-Rossi, Sara Seyedeh Ghoreishizadeh, Stefano Riario, Grégoire Surrel, Francesca Stradolini, Cristina Boero, Giovanni De Micheli
Full system for translational studies of personalized medicine with free-moving mice. 1774-1777
B4L-C: VLSI for Communication and Signal Processing
- Yusong Hu, Ching-Chuen Jong
Memory-efficient discrete wavelet transform architecture based on wordlength optimization. 1778-1781 - Hui-Sung Jeong, Tae-Hwan Kim:
An efficient processor for joint barrel distortion correction and color demosaicking. 1782-1785 - Chih-Chung Fang, I-Wen Chen, Tian-Sheuan Chang
A hardware-efficient deblocking filter design for HEVC. 1786-1789 - Jinmook Lee, Seongwook Park, Injoon Hong, Hoi-Jun Yoo:
A 3.13nJ/sample energy-efficient speech extraction processor for robust speech recognition in mobile head-mounted display systems. 1790-1793 - Arash Ardakani, Mahdi Shabany:
An efficient max-log MAP algorithm for VLSI implementation of turbo decoders. 1794-1797
B4L-D: Education in Circuits and Systems
- Ioannis Vourkas
XbarSim: An educational simulation tool for memristive crossbar-based circuits. 1798-1801 - Sergio Callegari, Federico Bizzarri
Teaching ΔΣ modulators with PyDSM and scientific Python. 1802-1805 - Vedat Tavsanoglu:
A systematic approach to the time-domain computation of the impulse response and post-initial conditions of causal LTI systems at the origin. 1806-1809 - Yanjie Gu, Guoyong Shi:
An interactive program for automatic network function generation with insights. 1810-1813
B4L-J: Analog Signal Processing Circuits
- Alonso Morgado, Rocío del Río, José M. de la Rosa:
Energy efficient transconductor for widely programmable analog circuits and systems. 1814-1817 - Cecilia Gimeno, Erick Guerrero, Carlos Sánchez-Azqueta
1-V continuous-time linear equalizer for up to 2 Gb/s over 50-m SI-POF. 1818-1821 - Mohamed Atef
A second-order noise-shaping time-to-digital converter using switched-ring oscillator. 1822-1825 - Soheil Ziabakhsh, Ghyslain Gagnon
Wide linear range voltage-controlled delay unit for time-mode signal processing. 1826-1829 - Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim:
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. 1830-1833
B4L-K: Digital VLSI Circuits
- Volnei A. Pedroni:
XOR-decomposition principle and its use to build a glitch-free maximum-speed arbitrary binary waveform generator and deglitcher. 1834-1837 - Christina Galani, Andreas Tsormpatzoglou, Panagiotis Chaourani, Ioannis Messaris, Spiros Nikolaidis
A study for replacing CMOS gates by equivalent inverters. 1838-1841 - Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
MIL-STD-1553+: Integrated remote terminal and bus controller at 100-Mb/s data rate. 1842-1845 - Erica Tena-Sánchez
DPA vulnerability analysis on Trivium stream cipher using an optimized power model. 1846-1849 - Andrea Bonetti, Adam Teman
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. 1850-1853
B4L-L: Innovations in System Simulation, Testing and Verification
- Qianqian Ha, Yannick Maret, Juan Sebastian Rodriguez Estupinan, Alain Vachoux:
VHDL-AMS virtual prototyping of a generator circuit breaker ablation monitoring system. 1854-1857 - Aymeric Privat, Lawrence T. Clark:
Simple and accurate single event charge collection macro modeling for circuit simulation. 1858-1861 - Cunxi Yu, Walter Brown, Maciej J. Ciesielski:
Verification of arithmetic datapath designs using word-level approach - A case study. 1862-1865 - Khaled A. Helal, Sameh Attia
Comparative review of NoCs in the context of ASICs and FPGAs. 1866-1869 - Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Dynamic nets-to-TSVs assignment in 3D floorplanning. 1870-1873
B4L-M: Circuits & Systems for Power Systems
- David Welch, Jennifer Blain Christen
MEMS optical position sensor for sun tracking. 1874-1878 - Fábio Diniz Rossi
Modeling power consumption for DVFS policies. 1879-1882 - Tiffany L. Lakins, Chika O. Nwankpa:
Measurement location analysis for information embedded power systems. 1883-1886 - Daniel K. Molzahn, Sina S. Baghsorkhi, Ian A. Hiskens:
Semidefinite relaxations of equivalent optimal power flow problems: An illustrative example. 1887-1890 - Nicholas S. Coleman, Karen Nan Miu:
A study of time window selection for electric power distribution system analysis. 1891-1894
B6P-N: Live Demos
- Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Jungle Chi-Hsiang Wu:
A wireless panoramic endoscope system design and implementation for minimally invasive surgery. 1895 - Matteo Stoppa, Danilo Demarchi
Live demonstration: An ultra-low power PFM IR-UWB system for short-range audio streaming. 1896 - Guillaume Seguin-Godin, Frédéric Mailhot, Jean Rouat:
Live demonstration: Efficient event-driven approach using synchrony processing for hardware spiking neural networks. 1897 - Pedro Miguel Cruz
Live demonstration: Mixed-signal network analysis characterization and modeling platform. 1898 - Manuel Suarez, Víctor M. Brea
Live demonstration: Gaussian pyramid extraction with a CMOS vision sensor. 1899 - Sonia Vargas-Sierra, Gustavo Liñán Cembrano
Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression. 1900 - Evangelos Stromatias, Daniel Neil, Francesco Galluppi
Live demonstration: Handwritten digit recognition using spiking deep belief networks on SpiNNaker. 1901 - Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. 1902 - Garrick Orchard
Live demonstration: Real-time event-driven object recognition on SpiNNaker. 1903 - Kai-Yin Fok, Chi-Tsun Cheng
Live demonstration: A HMM-based real-time sign language recognition system with multiple depth sensors. 1904 - Chirag Shetty, Sri Nitchith, Rishabh Rawat, S. R. Nandakumar
Live demonstration: Spiking neural circuit based navigation inspired by C. elegans thermotaxis. 1905 - Diogo Miguel Caetano, Moisés Piedade
Live demonstration: A CMOS ASIC for precise reading of a Magnetoresistive sensor array for NDT. 1906 - Antonio Rios-Navarro
Live demonstration: Real-time motor rotation frequency detection by spike-based visual and auditory AER sensory integration for FPGA. 1907 - Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid
Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware. 1908 - Ioannis Vourkas
Live demonstration: XbarSim: An educational simulation tool for memristive crossbar-based circuits. 1909 - Shengkui Gao, Suman Mondal, Nan Zhu, Rongguang Liang, Samuel Achilefu
Live demonstration: A compact NIR fluorescence imaging system design with goggle display for intraoperative guidance. 1910 - Missael Garcia, Shengkui Gao, Christopher Edmiston, Timothy York, Viktor Gruev:
Live demonstration: A 1300 × 800, 700 mW, 30 fps spectral polarization imager. 1911 - Irina Spulber, Y.-M. Chen, Enrica Papi, Salzitsa Anastasova-Ivanova, Jeroen Bergmann
Live demonstration: Wearable electronics for a smart garment aiding rehabilitation. 1912
C1L-A: Emerging Device and Circuit Technologies I
- Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). 1913-1916 - Atin Mukherjee
New triple-transistor based defect-tolerant systems for reliable digital architectures. 1917-1920 - Farnood Merrikh-Bayat, Xinjie Guo, H. A. Ommani, N. Do, Konstantin K. Likharev, Dmitri B. Strukov
Redesigning commercial floating-gate memory for analog computing applications. 1921-1924 - Gregor Sievers, Johannes Ax
Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI. 1925-1928 - Muhammad Sanaullah
Multilayer molybdenum disulfide (MoS2) based tunnel transistor. 1929-1932
C1L-B: Special Session: Advances in Analog CAD Tools
- Ivick Guerra-Gómez, Esteban Tlelo-Cuautle
OCBA in the yield optimization of analog integrated circuits by evolutionary algorithms. 1933-1936 - Hugo Serra
Automatic design of high-order SC filter circuits. 1937-1940 - Manuel Velasco-Jimenez, Rafael Castro-López
Design space exploration using hierarchical composition of performance models. 1941-1944 - Ricardo Martins
Extraction and application of wiring symmetry rules to route analog multiport terminals. 1945-1948 - Ailin Zhang, Guoyong Shi:
A symbolic SC integrator model for fast time-response simulation. 1949-1952 - Khaled Salah
Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV. 1953-1956
C1L-C: 3D Integrated Circuits
- Abdul Hamid Bin Yousuf, Nahid M. Hossain, Masud H. Chowdhury:
Performance analysis of through silicon via (TSV) and through glass via (TGV) for different materials. 1957-1960 - Debora Matos, Max Prass, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin:
Performance evaluation of hierarchical NoC topologies for stacked 3D ICs. 1961-1964 - Shiwei Fang
Low swing TSV signaling using novel level shifters with single supply voltage. 1965-1968 - Sumeet S. Kumar, Amir Zjajo, Rene van Leuken:
Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits. 1969-1972
C1L-D: Special Session: Parallel Processor Array Architectures and their Applications for Complex Problems
- Ákos Zarándy, Máté Németh, Borbala Jani Matyasne Pencz, Zoltán Nagy, Tamás Zsedrovits
Cellular sensor-processor array based visual collision warning sensor. 1973-1976 - Endre László, Zoltán Nagy, Michael B. Giles
Analysis of parallel processor architectures for the solution of the Black-Scholes PDE. 1977-1980 - András Kiss, Zoltán Nagy, Péter Szolgay, György Csaba
Emulating massively parallel non-Boolean operators on FPGA. 1981-1984 - Tero Säntti, Jonne K. Poikonen, Olli Lahdenoja, Mika Laiho
Online seam tracking for laser welding with a vision chip and FPGA enabled camera system. 1985-1988 - Jesus Omar Lacruz
A 630 Mbps non-binary LDPC decoder for FPGA. 1989-1992
C1L-E: Circuits for Error Correcting Codes
- Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg
On metric sorting for successive cancellation list decoding of polar codes. 1993-1996 - Hoyoung Tang, Gihoon Jung, Jongsun Park
A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. 1997-2000 - Mohammad Shahrad
TTCN: A new approach for low-power split-row LDPC decoders. 2001-2004 - Po-Hsiang Hsiung, Chung-An Shen, Huan-Chun Wang:
The joint detect and decoding approach for MIMO systems with turbo codes. 2005-2008
C1L-F: Special Session: Design of Secure and Side Channel Resistant Cryptographic Processors
- Ricardo Chaves
Challenges in designing trustworthy cryptographic co-processors. 2009-2012 - Baris Ege, Kostas Papagiannopoulos, Lejla Batina, Stjepan Picek:
Improving DPA resistance of S-boxes: How far can we go? 2013-2016 - Bohan Yang
On-the-fly tests for non-ideal true random number generators. 2017-2020 - Shivam Bhasin, Francesco Regazzoni
A survey on hardware trojan detection techniques. 2021-2024 - Apostolos P. Fournaris, Ioannis Zafeirakis, Christos Koulamas
Designing efficient elliptic Curve Diffie-Hellman accelerators for embedded systems. 2025-2028
C1L-G: Sigma-Delta Modulators I
- Yao Liu, Edoardo Bonizzoni, Franco Maloberti:
A single Op-Amp 0+2 sigma-delta modulator. 2029-2032 - Yang Xu, Spencer Leuenberger, Un-Ku Moon:
Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers. 2033-2036 - Somayeh Abdollahvand, Nuno Paulino
A current-mode VCO-based amplifier-less 2nd-order ΔΣ modulator with over 85dB SNDR. 2037-2040 - Swetha S. George, Yu Song, Zeljko Ignjatovic:
A 94-dB SFDR multi-bit audio-band delta-sigma converter with DAC nonlinearity suppression. 2041-2044 - Xin Meng, Yi Zhang, Tao He, Pedram Payandehnia, Gabor C. Temes:
A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays. 2045-2048
C1L-H: Intelligent Visual Signal Processing and Systems Design
- Tsung-Han Tsai, Chih-Hao Chang:
Design for an intelligent surveillance system based on system-on-a-programmable-chip platform. 2049-2052 - Imad Benacer
Hardware design and FPGA implementation for road plane extraction based on V-disparity approach. 2053-2056 - Yi Li, Fei Qiao, Qi Wei, Huazhong Yang:
Physical computing circuit with no clock to establish Gaussian pyramid of SIFT algorithm. 2057-2060 - Julien N. P. Martel, Miguel Chau, Piotr Dudek, Matthew Cook:
Toward joint approximate inference of visual quantities on cellular processor arrays. 2061-2064 - Ning Zheng
Two-dimensional discriminant multi-manifolds locality preserving projection for facial expression recognition. 2065-2068
C1L-J: Amplifiers I
- Ricardo Povoa
A voltage-combiners-biased amplifier with enhanced gain and speed using current starving. 2069-2072 - Shi Bu, Hing Wa Tse, Ka Nang Leung
Gain and slew rate enhancement for amplifiers through current starving and feeding. 2073-2076 - Xu Zhang, Chongli Cai, Degang Chen, Gregory Blum:
Cascode and transconductance with capacitances feedback compensation for multistage amplifiers driving no load and 1nF capacitive load. 2077-2080 - Stepan Sutula, Michele Dei
Class-AB single-stage OpAmp for low-power switched-capacitor circuits. 2081-2084 - Imon Mondal, Nagendra Krishnapura
Gain enhanced high frequency OTA with on-chip tuned negative conductance load. 2085-2088
C1L-K: Modeling, Dynamics, and Control of Power Converters I
- Abdelali El Aroudi, Weiguo Lu, Mohammed S. Al-Numay
Subharmonic instability boundary in DC-AC H-bridge inverters with double edge PWM. 2089-2092 - Xun Liu, Cheng Huang
Dynamic performance analysis of 3-level integrated buck converters. 2093-2096 - Koichi Furukawa, Taro Takiguchi, Ryuga Hosoki, Hirotaka Koizumi:
A high step-up DC-DC converter using transformer with intrinsic voltage-doubler. 2097-2100 - Yafei Hu, Adrian Ioinovici:
Simple switched-capacitor-boost converter with large DC gain and low voltage stress on switches. 2101-2104 - Carlos Ferreira, Beatriz Vieira Borges:
New phase shift modulator for resonant converters. 2105-2108
C1L-L: Sensors
- Poki Chen, Yi-Jiang Hu, Jian-Cheng Liou, Bo-Chang Ren:
A 486k S/s CMOS time-domain smart temperature sensor with -0.85°C/0.78°C voltage-calibrated error. 2109-2112 - Francisco O. O. Gomes, Luciano de Paula, Joao C. S. Santos, Laurent Courcelle, Daniel Piovani, Filipe Viera, Felipe M. Henes, Marcelo Lubaszewski:
A low-power RFID enabled temperature sensor for cold chain management. 2113-2116 - Mohamed Metwally, Nicholai L'Esperance, Tian Xia:
Ground penetrating radar utilizing compressive sampling and OFDM techniques. 2117-2120 - Mingquan Yuan
Sensing by growing antennas: A novel approach for designing passive RFID based biosensors. 2121-2124 - Joseph A. Schmitz, Mahir Kabeer Gharzai, Sina Balkir, Michael W. Hoffman, Daniel J. White, Nathan Schemm:
A programmable vision chip with pixel-neighborhood level parallel processing. 2125-2128
C1L-M: Innovations in Logic & Physical Synthesis
- Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. 2129-2132 - Boris Vaisband, Eby G. Friedman:
3-D floorplanning algorithm to minimize thermal interactions. 2133-2136 - Xuan Dong, Lihong Zhang:
Lithography-friendly analog layout migration. 2137-2140 - Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama
Effective two-dimensional pattern generation for self-aligned double patterning. 2141-2144 - Nusrat Jahan Lisa, Hafiz Md. Hasan Babu:
A compact representation of a quantum controlled ternary barrel shifter. 2145-2148
C2P-N: Signal and Image Processing
- Hamidreza Sadreazami, M. Omair Ahmad, M. N. Shanmukha Swamy:
Image denoising utilizing the scale-dependency in the contourlet domain. 2149-2152 - Han Chen, Wei-Ping Zhu
Real-Valued ESPRIT for two-dimensional DOA estimation of noncircular signals for acoustic vector sensor array. 2153-2156 - Youshen Xia, Wei Xing Zheng:
On unbiased identification of autoregressive signals with noisy measurements. 2157-2160 - Jun-Jie Huang, Wan-Chi Siu:
Practical application of random forests for super-resolution imaging. 2161-2164 - Qiaohong Li, Yuming Fang, Weisi Lin, Daniel Thalmann:
Gradient-weighted structural similarity for image quality assessments. 2165-2168
C2P-P: DSP Application
- Thomas P. Weldon
Performance of digital discrete-time implementations of non-Foster circuit elements. 2169-2172 - Gabriel S. da Silva, Augusto F. R. Queiroz, Eduardo R. de Lima, Cesar G. Chaves
A novel fine frequency estimation serial architecture applied in satellite communications. 2173-2176 - Walter D. Leon-Salas:
Encoding compressive sensing measurements with Golomb-Rice codes. 2177-2180 - Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen:
Hardware implementation of all digital calibration for undersampling TIADCs. 2181-2184 - Huapeng Wu:
Efficient radix conversions for classes of radices. 2185-2188 - Dali Wang, Ying Bai, Ali Zilouchian:
Quantization error calculation of various realizations of 2-D separable-in-denominator recursive filters. 2189-2192
C2P-Q: Digital Filters
- Takao Hinamoto, Akimitsu Doi, Wu-Sheng Lu:
Weighted pole and zero sensitivity minimization for state-space digital filters. 2193-2196 - Takashi Yoshida, Yosuke Sugiura, Naoyuki Aikawa:
A general expression of the low-pass maximally flat FIR digital differentiators. 2197-2200 - Dinesh Kumar Chobey, Yong Ching Lim:
A piloted notch time-frequency information based variable step-size algorithm. 2201-2204 - Oscar Gustafsson
Decimation filters for high-speed delta-sigma modulators with passband constraints: General versus CIC-based FIR filters. 2205-2208
C2P-R: Communication Circuits
- Anup Jyoti Deka, Venkatesh Prasanna:
A 1Gbps-10 Gbps multi-standard auto-calibrated all digital phase interpolator in 14nm CMOS. 2209-2212 - Li Xu
Inductorless linearization of low-power active mixers. 2213-2216 - Ying Guo, Ling Shen, Fan Yang, Yongan Zheng, Long Chen, Xing Zhang, Huailin Liao:
A 0.5-2 GHz high frequency selectivity RF front-end with series N-path filter. 2217-2220
C2P-S: Analog Circuits I
- Xu Zhang, Degang Chen:
An integrated circuit solution of thermal noise thermometer with cascaded pre-amplifier and 6-bit resolution analog-to-digital converter. 2221-2224 - Cristina Azcona, Belén Calvo, Nicolás Medrano, Santiago Celma, Cecilia Gimeno:
A wide-range dual-modulus prescaler using a novel SCL biasing technique. 2225-2228 - Bo Jiang, Tian Xia:
A quad-mode DCO for multi-standard communication application. 2229-2232 - Fernando Cardes
A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. 2233-2236 - Antonio A. D'Amico, Angelo Nagari, Piero Malcovati
An FSK modulator at 23.2 MHz with ±0.9% accuracy for the USB power delivery standard. 2237-2240
C2P-T: Analog Circuits II
- S. Rasool Hosseini, Mehdi Saberi, Reza Lotfi:
An energy-efficient level shifter for low-power applications. 2241-2244 - Charalambos M. Andreou, Alessandro Paccagnella
A subthreshold, low-power, RHBD reference circuit, for earth observation and communication satellites. 2245-2248 - Yue Hu, Spencer Leuenberger, Yang Xu, Un-Ku Moon:
Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement. 2249-2252 - Taewook Kim, Jun Liu, Nima Maghari:
High-speed and high-linearity ring oscillator based pulse width modulator. 2253-2256 - Ya Wang, Fule Li, Chunying Xue, Zhihua Wang:
Charge-compensation-based reference technique for switched-capacitor ADCs. 2257-2260
C2P-U: Analog Circuits Testing and Verification II
- Vladimir Mashkovtsev, Ali Attaran, Rashid Rashidzadeh:
DLL based test solution for interposers in 2.5-D ICs. 2261-2264 - Li Xu, Degang Chen:
Accurate spectral testing of analog-to-digital converters with frequency drift using phase correction and averaging. 2265-2268 - David Guilherme, João Pereira, Nuno Horta
Thermal-aware floorplanning and layout generation of MOSFET power stages. 2269-2272 - Mehran Bakhshiani, Pedram Mohseni:
Voltage-based wideband measurement of transmission characteristics using an integrated receiver IC. 2273-2276 - Li Xu, Degang Chen:
A low cost jitter estimation and ADC spectral testing method. 2277-2280
C2P-V: Calibration Techniques
- Hussein Adel, Marc Sabut, Marie-Minerve Louërat:
1.1-V 200 MS/s 12-bit digitally calibrated pipeline ADC in 40 nm CMOS. 2281-2284 - Yu-Chuan Lin, Hen-Wai Tsao
A high-speed high-accuracy voltage-to-time-difference converter for time domain analog-to-digital converters. 2285-2288 - Bindi Wang, Yao-Hong Liu
A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. 2289-2292 - Jingjing Hu, Hans Hegt, Arthur H. M. van Roermund, Sotir Ouzounov:
Bitstream switching rate based calibration of delta-sigma modulators. 2293-2296 - Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek
A digital time skew calibration technique for time-interleaved ADCs. 2297-2300
C2P-W: Nano-Electronics IV
- Zhibo Wang, Yongpan Liu, Yinan Sun, Yang Li, Daming Zhang, Huazhong Yang:
An energy-efficient heterogeneous dual-core processor for Internet of Things. 2301-2304 - Turbo Majumder, Manan Suri
NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission. 2305-2308
C3L-A: Emerging Device and Circuit Technologies II
- Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analysis of subthreshold swing in multichannel tunneling carbon nanotube field effect transistor (MT-CNTFET). 2309-2312 - Kien Trinh Quang
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance. 2313-2316 - Sami Smaili, Shuang Li, Yehia Massoud:
A design methodology for minimizing power loss in integrated DC-DC converter with spiral inductors. 2317-2320 - Loai G. Salem
A footprint-constrained efficiency roadmap for on-chip switched-capacitor DC-DC converters. 2321-2324 - Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. 2325-2328
C3L-B: Special Session: Fractors and Fractional Order Systems
- Avishek Adhikary
Realization of a carbon nanotube based electrochemical fractor. 2329-2332 - Pawel Ziubinski, Dominik Sierociuk
Fractional order noise identification with application to temperature sensor data. 2333-2336 - Georgia Tsirimokou, Costas Psychalinos
Digitally programmed fractional-order Chebyshev filters realizations using current-mirrors. 2337-2340 - Gary Bohannan, Brenda Knauber:
A physical experimental study of the fractional harmonic oscillator. 2341-2344
C3L-C: Low-Power Logic & Architectures
- Volnei A. Pedroni:
Introducing deglitched-feedback plus convergent encoding for straight hardware implementation of asynchronous finite state machines. 2345-2348 - Wenfeng Zhao, Yajun Ha, Massimo Alioto:
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. 2349-2352 - Yan Li, Xiaoqian Li, Jianhao Hu, Sheng Yang:
Area-sharing cyclic structure MRF cirucits design in ultra-low supply voltage. 2353-2356 - Qiubo Chen, Hengyu Zhao, Hongbin Sun, Nanning Zheng:
Exploiting bit-depth scaling for quality-scalable energy efficient display processing. 2357-2360 - Alicia Klinefelter, Joseph F. Ryan, James W. Tschanz, Benton H. Calhoun:
Error-energy analysis of hardware logarithmic approximation methods for low power applications. 2361-2364
C3L-D: Special Session: Recent Advances in Multidimensional Systems and Signal Processing
- Arjuna Madanayake
Recent advances in multidimensional systems and signal processing: An overview. 2365-2368 - Shi Yan, Lijun Sun
2-D zero-phase IIR notch filters design based on state-space representation of 2-D frequency transformation. 2369-2370 - Alfred Fettweis, Sankar Basu:
Modelling of multidimensional (MD) heat diffusion via the Kirchhoff paradigm. 2373-2376 - Jörg Velten, Anton Kummert, Alexandros Gavriilidis, Fritz Boschen:
2-D signal theoretic investigation of background elimination in visual tomographic reconstruction for safety and enabling health applications. 2377-2380 - Chamira U. S. Edussooriya, Leonard T. Bruton, Panajotis Agathoklis:
A 5-D IIR depth-velocity filter for enhancing objects moving on linear-trajectories in light field videos. 2381-2384
C3L-E: Communications Circuits
- László Szilágyi, Guido Belfiore, Ronny Henker, Frank Ellinger:
A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS. 2385-2388 - Kwanseo Park
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. 2389-2392 - Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen:
A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. 2393-2396 - Jerry Han, Michael M. Green:
A 2 × 50-Gb/s receiver with adaptive channel loss equalization and far-end crosstalk cancellation. 2397-2400 - Jun Luo, Lei Zhang, Wei Zhu, Li Zhang, Yan Wang, Zhiping Yu:
A 64dB gain 60GHz receiver with 7.1dB noise figure for 802.11ad applications in 90nm CMOS. 2401-2404
C3L-F: Special Session: Real-Time Event-Based Sensor Processing
- Teresa Serrano-Gotarredona
ConvNets experiments on SpiNNaker. 2405-2408 - Tobi Delbrück
Human vs. computer slot car racing using an event and frame-based DAVIS vision sensor. 2409-2412 - Garrick Orchard
Real-time event-driven spiking neural network object recognition on the SpiNNaker platform. 2413-2416 - Alejandro Linares-Barranco
A USB3.0 FPGA event-based filtering and tracking framework for dynamic vision sensors. 2417-2420 - Philipp Klein
Scene stitching with event-driven sensors on a robot head platform. 2421-2424
C3L-G: Successive Approximation ADCs
- Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, Chun-Jen Chen:
A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems. 2425-2428 - Sung-En Hsieh, Cheng-Kang Ho, Chih-Cheng Hsieh:
A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter. 2429-2432 - Dante Gabriel Muratore
A split transconductor high-speed SAR ADC. 2433-2436 - Ye Xu, Pieter Harpe, Trond Ytterdal:
A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area. 2437-2440 - Sami Ur Rehman, Ayman Shabra:
Reference-less SAR ADC for on-chip thermal monitoring in CMOS. 2441-2444
C3L-H: Special Session: Cross -Layer Technology and Design Solutions for Resilience
- Gerhard Rzepa, Wolfgang Goes, Ben Kaczer, Tibor Grasser:
Characterization and modeling of reliability issues in nanoscale devices. 2445-2448 - A. Asenov, Jie Ding, Dave Reid, Plamen Asenov, Salvatore M. Amoroso, Fikru Adamu-Lema, Louis Gerrer:
Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits. 2449-2452 - Runsheng Wang, Yu Cao
Impact of temporal transistor variations on circuit reliability. 2453-2456 - Fabian Oboril, Mojtaba Ebrahimi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Cross-layer resilient system design flow. 2457-2460
C3L-J: Amplifiers II
- María de Rodanas Valero Bernal
Constant gm rail-to-rail CMOS OpAmp with only one differential pair and switched level shifters. 2461-2464 - Kai Ho Mak, Marco Ho
Design considerations of STCB OTA in CMOS 65nm with large capacitive loads. 2465-2468 - Hiroki Sato, Shigetaka Takagi:
Low-voltage amplifier with improved linearity using triode region MOSFET. 2469-2472 - Moaaz Ahmed
An improved recycling folded cascode amplifier with gain boosting and phase margin enhancement. 2473-2476 - Juergen Roeber, Andreas Baenisch, Georg Fischer
A low noise amplifier chain for digital satellite radio applications. 2477-2480
C3L-K: Modeling, Dynamics and Control of Power Converters II
- Yidi Yang, Weiguo Lu, Herbert H. C. Iu, Tyrone Fernando
Stabilization of fast-scale instabilities in PCM boost PFC converter with dynamic slope compensation. 2481-2484 - Nicola Bertoni
A new semi-analytic approach for class-E resonant DC-DC converter design. 2485-2488 - Abdelali El Aroudi, Germain Garcia, Danièle Fournier, Mohammed S. Al-Numay
Bifurcation behavior in a two-loop DC-DC quadratic boost converter. 2489-2492 - Junkai Zhao, Herbert H. C. Iu, Tyrone Fernando
Design of a non-isolated single-switch three-port DC-DC converter for standalone PV-battery power system. 2493-2496 - Bu-Wei Chen, Le-Ren Chang-Chien
Digitally controlled low cross-regulation single-inductor dual-output (SIDO) buck converter. 2497-2500
C3L-L: Neural Networks Circuits and Systems
- Robin Danilo, Hooman Jarollahi, Vincent Gripon, Philippe Coussy, Laura Conde-Canencia, Warren J. Gross:
Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. 2501-2504 - Mingu Kang, Eric P. Kim, Min-Sun Keel, Naresh R. Shanbhag:
Energy-efficient and high throughput sparse distributed memory architecture. 2505-2508 - Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu
Neural approximating architecture targeting multiple application domains. 2509-2512 - Liang Zhou
A continuous-time varactor-based temperature compensation circuit for floating-gate multipliers and inner-product circuits. 2513-2516 - Hiroomi Hikawa:
Winner-take-all neural network with digital frequency-locked loop. 2517-2520
C3L-M: Algorithms and Architectures for 3D Media Processing
- Sih-Sian Wu, Hong-Hui Chen, Chen-Han Tsai, Liang-Gee Chen
Memory efficient architecture for belief propagation based disparity estimation. 2521-2524 - Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid
Real-time free viewpoint synthesis using three-camera disparity estimation hardware. 2525-2528 - Wenxin Yu, Liang Yu, Weichen Wang, Jiu Xu:
Frame compatible format fast encoder with stereo matching. 2529-2532 - Yeong-Kang Lai, Yu-Chieh Chung:
An efficient and high quality rasterization algorithm and architecture in 3D graphics systems. 2537-2540
C4L-A: Memory Circuits and Architectures I
- Byung-Jun Jang, Chan-Ho Lee, Sung-Hun Sim, Kyu-Won Choi, Do-Hun Byun, Yeon-Ho Jung, Ki-Man Park, Dong-Yeon Heo, Gyu-Hong Kim, Joon-Sung Yang:
Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield. 2541-2544 - Radisav Cojbasic, Yusuf Leblebici:
Design of high-temperature SRAM for reliable operation beyond 250°C. 2545-2548 - Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee:
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. 2549-2552 - Anh-Tuan Do, Kiat Seng Yeo
A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation. 2553-2556 - Hiroshi Uchigaito, Seiji Miura, Takumi Nito:
A control scheme for eliminating garbage collection during highspeed analysis of big-graph data stored in NAND flash memory. 2557-2560
C4L-B: Special Session: Digitally Intensive Frequency Synthesizers for All-Digital Transmitters in the Nano
- Paul P. Sotiriadis
Spurs-free single-bit-output frequency synthesizers for fully-digital RF transmitters. 2561-2564 - Peng Chen
Fractional spur suppression in all-digital phase-locked loops. 2565-2568 - Ioannis L. Syllaios, Henrik T. Jensen:
DPLL with hybrid ΔΣ phase/frequency detector. 2569-2572 - Raghavasimhan Thirunarayanan, David Ruffieux, Christian C. Enz:
Enabling highly energy efficient WSN through PLL-free, fast wakeup radios. 2573-2576 - Michael Peter Kennedy, Hongjia Mo, Zhida Li, Guosheng Hu, Paolo Scognamiglio, Ettore Napoli:
The noise and spur delusion in fractional-N frequency synthesizer design. 2577-2580
C4L-C: Low Power Circuits I
- Tzu-Yun Wang, Li-Han Liu, Min-Rui Lai, Sheng-Yu Peng:
Linearity efficiency factor and power-efficient operational transconductance amplifier in subthreshold operation. 2581-2584 - Hong-Son Vu
A 6.42 mW low-power feed-forward FxLMS ANC VLSI design for in-ear headphones. 2585-2588 - Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. 2589-2592 - Ran Xiao, Chunhong Chen:
Power optimization design for probabilistic logic circuits. 2593-2595 - Christopher Lawrence Ayala
Ultra-low-energy adiabatic dynamic logic circuits using nanoelectromechanical switches. 2596-2599
C4L-D: Digital Filter Banks and Transforms
- David B. H. Tay, Zhiping Lin:
Graph QMF with flatness constraints. 2600-2603 - Liang Tao, Hon Keung Kwan
Multi-window real-valued discrete Gabor transform for long and infinite sequences. 2604-2607 - Leonardo Gomes Baltar, Israa Slim, Josef A. Nossek
Efficient filter bank multicarrier realizations for 5G. 2608-2611 - Juuso Alhava, Markku Renfors
Integer-to-integer complex extended lapped transform. 2612-2615 - Ziad Gias, Md. Mehedi Hasan, Khan A. Wahid:
Multi-beamforming with uniform linear array and algebraic integer quantization based DCT. 2616-2619
C4L-F: Wearable Circuits and Systems
- Wala Saadeh
A hybrid OFDM body coupled communication transceiver for binaural hearing aids in 65nm CMOS. 2620-2623 - Guocheng Huang
A 1.3μW 0.7μVRMS chopper current-reuse instrumentation amplifier for EEG applications. 2624-2627 - Oskar Andersson
A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS. 2628-2631 - Jingna Mao, Bo Zhao, Yong Lian
A 5-tissue-layer lumped-element based HBC circuit model compatible to IEEE802.15.6. 2632-2635 - Wei-Hsin Wang, Pau-Choo Chung, Guo Liang Yang, Chien-Wen Lin, Yu-Liang Hsu, Ming-Chyi Pai:
An inertial sensor based balance and gait analysis system. 2636-2639
C4L-G: Tools for Analog Design
- Jani K. Jarvenhaara, Nikolay T. Tchamov, Igor M. Filanovsky
Determining potentially unstable operating points using time-varying root-locus. 2640-2643 - Hanbin Hu
Topological symbolic simplification for analog design. 2644-2647 - Fanshu Jiao, Alex Doboli:
A low-voltage, low-power amplifier created by reasoning-based, systematic topology synthesis. 2648-2651 - Gönenç Berkol, Engin Afacan, Günhan Dündar
A novel yield aware multi-objective analog circuit optimization tool. 2652-2655
C4L-J: Analog Filtering I
- Antonio A. D'Amico, Marcello De Matteis
A 4th-order low-power diode-C-based filter with 12dBm-IIP3 at the cut-off frequency. 2656-2659 - Ahmad RezazadehReyhani, Chetan Jayanthmurthy, Bill Gillman, Jeffrey S. Walling
An analog adaptive notch filter based on the noise cancellation principle. 2660-2663 - Vasileios G. Ntinas
LC filters with enhanced memristive damping. 2664-2667 - Norbert Herencsar
Pole frequency and pass-band gain tunable novel fully-differential current-mode all-pass filter. 2668-2671 - Igor M. Filanovsky
Design of wide-band amplifiers/filters using Lommel polynomials. 2672-2675
C4L-K: Complex Networks Analysis and Applications I
- Huiyun Liu, Yongxiang Xia:
Optimal resource allocation under TCP Reno and Vegas in complex communication networks. 2676-2679 - Kexin Liu, Henghui Zhu, Jinhu Lu, Maciej J. Ogorzalek
Cooperative Design of Networked Observers for Stabilizing LTI Plants. 2680-2683 - Xi Zhang, Chi K. Tse
Assessment of Robustness of Power Systems from the Perspective of Complex Networks. 2684-2687 - Pietro De Lellis
Topological bifurcations in networks of proximity Kuramoto oscillators. 2688-2691 - Nuwan Ganganath
Cluster-based informed agents selection for flocking with a virtual leader. 2692-2695
C4L-L: Neuromorphic and Spiking Neural Systems
- Guillaume Seguin-Godin, Frédéric Mailhot, Jean Rouat:
Efficient event-driven approach using synchrony processing for hardware spiking neural networks. 2696-2699 - Junxiu Liu, Jim Harkin
Case study: Bio-inspired self-adaptive strategy for spike-based PID controller. 2700-2703 - Srinjoy Das, Bruno Umbria Pedroni, Paul Merolla, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Dharmendra S. Modha, Gert Cauwenberghs
Gibbs sampling with low-power spiking digital neurons. 2704-2707 - Federico Corradi
Decision making and perceptual bistability in spike-based neuromorphic VLSI systems. 2708-2711 - Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar:
Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications. 2712-2715
C4L-M: Nano-Electronics III
- Mario Iannazzo, Valerio Lo Muzzo, Saul Rodriguez
Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models. 2716-2719 - Yanan Sun, Volkan Kursun
Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed. 2720-2723 - Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Low cost and energy, thermal noise driven, probability modulated random number generator. 2724-2727 - André Lange
Towards probabilistic analog behavioral modeling. 2728-2731 - B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak:
Fault-aware configurable logic block for reliable reconfigurable FPGAs. 2732-2735
C5P-N: Media Coding and Processing
- Yuxiang Shen, Xiaolin Wu:
Down-sampling based embedded compression in video systems. 2736-2739 - Junhui Hou
Reordering-based transform for compressing human motion capture data. 2740-2743 - Leo Yu Zhang
Joint quantization and diffusion for compressed sensing measurements of natural images. 2744-2747 - Minhao Tang, Jiangtao Wen:
An efficient HEVC to H.264/AVC transcoding system. 2748-2751 - Linjia Hu, Saeid Nooshabadi, Majid Ahmadi:
Massively parallel KD-tree construction and nearest neighbor search algorithms. 2752-2755 - Zhongpai Gao
Adapting hierarchical ALS algorithms for temporal psychovisual modulation. 2756-2759 - Chun-Wei Chen, Ching-Heng Su, Der-Wei Yang, Jonas Wang, Chia-Cheng Lo, Ming-Der Shieh:
High-quality texture compression using adaptive color grouping and selection algorithm. 2760-2763 - Shaoge Guo, Yaowei Wang, Yonghong Tian, Peiyin Xing, Wen Gao:
Quality-progressive coding for high bit-rate background frames on surveillance videos. 2764-2767
C5P-P: 3D Visual Signal Coding and Advanced Video Coding
- Junhui Hou
A linear dependent rate-quantization model for scalable video enhancement layer encoding. 2768-2771 - Haoming Chen, Yu-Sheng Chen, Ming-Ting Sun, Ankur Saxena, Madhukar Budagavi:
Improvements on Intra Block Copy in natural content video coding. 2772-2775 - Li Chen, Miska M. Hannuksela, Houqiang Li:
Disparity-compensated inter-layer motion prediction using standardized HEVC extensions. 2776-2779 - Zhouye Gu, Jianhua Zheng, Nam Ling, Philipp Zhang:
Fast segment-wise DC coding for 3D video compression. 2780-2783
C5P-Q: HEVC and Standard Video Coding
- Xufeng Li, Ronggang Wang, Xiaole Cui, Wenmin Wang:
Context-adaptive fast motion estimation of HEVC. 2784-2787 - Li Li, Houqiang Li:
λ Domain based optimal bit allocation for scalable high efficiency video coding. 2788-2791 - Tae-Sun Kim, Myung Hoon Sunwoo, Jin-Gyun Chung:
Hierarchical fast mode decision algorithm for intra prediction in HEVC. 2792-2795
C5P-R: Efficient Visual Signal Analysis and Identification
- Yazhong Zhang, Jinjian Wu, Guangming Shi, Xuemei Xie
Reduced-reference image quality assessment based on entropy differences in DCT domain. 2796-2799 - Min-Jen Tsai, Chien-Lun Hsu, Jin-Sheng Yin, Imam Yuadi:
Japanese character based printed source identification. 2800-2803 - Li-Chih Chen, Jun-Wei Hsieh, Hui-Fen Chiang, Tsung-Hsien Tsai:
Real-time vehicle color identification using symmetrical SURFs and chromatic strength. 2804-2807 - Marc-Andre Carbonneau
Real-time visual play-break detection in sport events using a context descriptor. 2808-2811
C5P-S: Visual Signal Processing and Modeling
- Meng Yang, Ce Zhu, Xuguang Lan, Nanning Zheng:
Parameter-free view synthesis distortion model with application to depth video coding. 2812-2815 - Ke Gu, Guangtao Zhai, Shiqi Wang
A general histogram modification framework for efficient contrast enhancement. 2816-2819 - Shuolin Di, Zhebin Zhang, Shiqi Wang
Image guided label map propagation in video sequences. 2820-2823 - G. Diaz-Arango, Arturo Sarmiento-Reyes
Path optimization for terrestrial robots using Homotopy Path Planning Method. 2824-2827
C5P-T: Visual Signal Processing and Communications
- Tiago Dias
High performance IP core for HEVC quantization. 2828-2831 - Giorgio Lopez, Ettore Napoli, Domenico Meglio, Antonio G. M. Strollo:
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. 2832-2835 - Marek Parfieniuk
Using the CS decomposition to compute the 8-point DCT. 2836-2839
C5P-U: Millimeter-Wave & Optical Communications Circuits
- Jun Luo, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu:
A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications. 2840-2543 - Mahmoud Sawaby, Ahmed Nader Mohieldin
Design and optimization of a 94GHz rotary traveling wave oscillator for mm-wave applications. 2844-2847 - Sudipta Chakraborty
A wideband transformer-coupled frequency quadrupler using an asymmetrical balun in 0.25μm SiGe for backhaul communication. 2848-2851
C5P-V: Wireline Communications I
- Kuan-I Wu, Szu-Yao Hung, Shuo-Hong Hung, Charlie Chung-Ping Chen:
A fast-settling high linearity auto gain control for broadband OFDM-based PLC system. 2852-2855 - Sungwoo Kim, Sungchun Jang, Jun-Eun Park
A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. 2856-2859 - Christopher J. Lukas
A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems. 2860-2863 - Jun-Eun Park
20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS. 2864-2867 - Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye:
Minimum jitter adaptive decision feedback equalizer for 4PAM serial links. 2868-2871
C5P-W: CANDE (Computer-Aided Network Design) Posters
- Rupesh Raj Karn, Ibrahim Abe M. Elfadel
Multicore power proxies using least-angle regression. 2872-2875 - Raimund Ubar
Combinational fault simulation in sequential circuits. 2876-2879 - Florin Balasa, Noha Abuaesh, Cristian V. Gingu, Hongwei Zhu:
Optimization of memory banking in embedded multidimensional signal processing applications. 2880-2883 - Levent Aksoy
Approximation of multiple constant multiplications using minimum look-up tables on FPGA. 2884-2887 - Kan Xu, Eby G. Friedman:
Inductive coupling effects in large TSV arrays. 2888-2891
C6L-A: Memory Circuits and Architectures II
- Kiyoo Itoh, Khaja Ahmad Shaik, Amara Amara:
0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell. 2892-2895 - Nahid M. Hossain, Jitendra Koppu, Masud H. Chowdhury:
Analysis of radiation effect on the threshold voltage of flash memory device. 2896-2899 - Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark:
Delay and power tradeoffs for static and dynamic register files. 2900-2903 - Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. 2904-2907 - Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham
Parallel pipelining configurable multi-port memory controller for multimedia applications. 2908-2911
C6L-B: Special Session: Carbon-Based Circuits and Systems
- Saul Rodriguez
Overview of carbon-based circuits and systems. 2912-2915 - Maruthi N. Yogeesh, Saungeun Park, Deji Akinwande:
Graphene based GHz flexible nanoelectronics and radio receiver systems (Invited). 2916-2919 - Sébastien Fregonese, Jorgue Daniel Aguirre Morales, Magali De Matos, Cristell Maneux
Graphene FET evaluation for RF and mmWave circuit applications. 2920-2923 - Georges G. E. Gielen, Jelle Van Rethy, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Time-based sensor interface circuits in carbon nanotube technology. 2924-2927 - José G. Delgado-Frias, Zhe Zhang, Michael A. Turi:
Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance. 2928-2931
C6L-C: Low Power Circuits II
- Hong Zhu, Volkan Kursun
2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents. 2932-2935 - Hooman Farkhani, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi
STT-RAM write energy consumption reduction by differential write termination method. 2936-2939 - Mohammed Alamgir, Iftekhar Ibne Basith, Tareq Muhammad Supon, Rashid Rashidzadeh:
Improved bus-shift coding for low-power I/O. 2940-2943 - Rizwan A. Ashraf
Reactive rejuvenation of CMOS logic paths using self-activating voltage domains. 2944-2947 - Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa:
A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs. 2948-2951
C6L-D: FIR and IIR Digital Filters
- Wu-Sheng Lu, Takao Hinamoto:
Optimal design of composite digital filters using convex-concave procedure. 2952-2955 - Takao Hinamoto, Akimitsu Doi, Wu-Sheng Lu:
Optimal error feedback and realization for roundoff noise minimization in linear discrete-time systems with full-order state observer feedback. 2956-2959 - Weiao Ding, Jiajia Chen:
Design of low complexity programmable FIR filters using multiplexers array optimization. 2960-2963 - Wen Bin Ye, Xin Lou, Ya Jun Yu:
Design of high-speed multiplierless linear-phase FIR filters. 2964-2967 - Aimin Jiang
IIR filter design with novel stability condition. 2968-2971
C6L-E: MIMO Communication Systems
- Werner Haselmayr, Georg Möstl, Stefan Seeber, Andreas Springer
Hardware implementation of the SUMIS detector using high-level synthesis. 2972-2975 - Shahriar Shahabuddin, Janne Janhunen, Zaheer Khan, Markku J. Juntti
A customized lattice reduction multiprocessor for MIMO detection. 2976-2979 - Chi-Mao Chen, Chih-Hsiang Lin, Pei-Yun Tsai:
Multi-mode sorted QR decomposition for 4×4 and 8×8 single-user/multi-user MIMO precoding. 2980-2983 - Isael Diaz, Siyu Tan, Yun Miao, Leif R. Wilhelmsson, Ove Edfors
A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS. 2984-2987 - Chun-Lin Ko, Chun-Hsing Li, Chien-Nan Kuo, Ming-Ching Kuo, Da-Chiang Chang:
A 8-mW 77-GHz band CMOS LNA by using reduced simultaneous noise and impedance matching technique. 2988-2991
C6L-F: Neural Recording Circuits and Systems
- Xu Liu, Lei Yao, Peng Li, Mei Yan, Shih-Cheng Yen, Hao Yu, Minkyu Je, Yong Ping Xu:
A 16-channel 24-V 1.8-mA power efficiency enhanced neural/muscular stimulator with exponentially decaying stimulation current. 2992-2995 - Xilin Liu
Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit. 2996-2999 - Konstantinos Faliagkas, Lieuwe B. Leene, Timothy G. Constandinou
A novel neural recording system utilising continuous time energy based compression. 3000-3003 - Yi Chen, Enyi Yao, Arindam Basu
A 128 channel 290 GMACs/W machine learning based co-processor for intention decoding in brain machine interfaces. 3004-3007 - Majid Zamani, Andreas Demosthenous
Power optimization of neural frontend interfaces. 3008-3011
C6L-G: Analog Circuits Testing and Verification I
- Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Koichi Tanno, Akihiro Yamada:
Subblock-level matching layout for analog block-pair and its manufacturability evaluation. 3012-3015 - Yan Duan, Tao Chen
High-constancy offset generator robust to CDAC nonlinearity for SEIR-based ADC BIST. 3016-3019 - Chongli Cai, Degang Chen:
Performance enhancement induced Trojan states in op-amps, their detection and removal. 3020-3023 - Xu Zhang, Chongli Cai, Hao Meng, Siva Sudani, Randall L. Geiger, Degang Chen:
A calibration technique for SAR analog-to-digital converter based on INL testing with quantization bits and redundant bit. 3024-3027 - Sandeep Krishnan, Shanthi Pavan:
A 10 Gbps eye opening monitor in 65nm CMOS. 3028-3031
C6L-H: Special Session: Emerging Channel Decoder Design Techniques for Communication and Memory Systems
- Chuan Zhang, Junmei Yang, Xiaohu You, Shugong Xu
Pipelined implementations of polar encoder and feed-back part for SC polar decoder. 3032-3035 - Bo Yuan, Keshab K. Parhi
Successive cancellation decoding of polar codes using stochastic computing. 3040-3043 - Di Wu, Yun Chen, Qichen Zhang, Li-Rong Zheng, Xiaoyang Zeng, Yeong-Luh Ueng
Latency-optimized stochastic LDPC decoder for high-throughput applications. 3044-3047
C6L-J: Frequency Synthesizers and Oscillators
- Yung-Chung Lo, Negar Rashidi, Yin-Huan Hwang, José Silva-Martínez:
A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications. 3048-3051 - Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power. 3052-3055 - Roman Sotner
Quadrature oscillator solution suitable with arbitrary and electronically adjustable phase shift. 3056-3059 - Carlos Sánchez-Azqueta
A 1.7-GHz wide-band CMOS LC-VCO with 7-Bit coarse control. 3060-3063 - Ling Yuan, Qiang Zhang, Yin Shi:
A 2GHz direct digital frequency synthesizer based on multi-channel structure. 3064-3067
C6L-K: Analysis and Control of Nonlinear Circuits and Systems
- Yunliang Wei, Wei Xing Zheng:
An efficient method for control of continuous-time systems subject to input saturation and external disturbance. 3068-3071 - Shihong Ding, Wei Xing Zheng:
Some results on design of second-order sliding mode controller for nonlinear systems. 3072-3075 - Wenjun Xiong, Wei Xing Zheng:
A new approach to finite-time tracking of coupled continuous networks. 3076-3079 - Michele Bonnin, Fabio L. Traversa, Fernando Corinto
Phase and amplitude dynamics of noisy oscillators described by Itô stochastic differential equations. 3080-3083 - Vera Smirnova, Anton V. Proskurnikov
Cycle slipping in nonlinear circuits under periodic nonlinearities and time delays. 3084-3087
A3L-A: Special Session: Device-Circuit-System Integration Using Emerging Memory Part-II
- Barbara De Salvo, Elisa Vianello, Olivier Thomas, Fabien Clermidy, Olivier Bichler, Christian Gamrat, Luca Perniola:
Emerging resistive memories for low power embedded applications and neuromorphic systems. 3088-3091
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