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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 37
Volume 37, Number 1, January 2018
- Rajesh K. Gupta:
Editorial. 1-2 - Saraju P. Mohanty
, Michael Hübner, Chun Jason Xue, Xin Li
Guest Editorial Circuit and System Design Automation for Internet of Things. 3-6 - Tosiron Adegbija
Microprocessor Optimizations for the Internet of Things: A Survey. 7-20 - Jian-Jun Han
Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization Bound. 21-34 - Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Jincheng Yu, Junbin Wang, Song Yao, Song Han, Yu Wang
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA. 35-47 - Renzo Andri
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration. 48-60 - Jonathan Beaumont
High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds. 61-74 - Shaoming Chen, Lu Peng
qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses. 75-87 - Juan Wang, Zhi Hong, Yuhan Zhang, Yier Jin
Enabling Security-Enhanced Attestation With Intel SGX for Remote Terminal and IoT. 88-96 - Cédric Marchand
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. 97-109 - S. Dinesh Kumar, Himanshu Thapliyal
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices. 110-122 - Hui Geng
On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach. 123-132 - Andrea Cirigliano
Toward Smart Building Design Automation: Extensible CAD Framework for Indoor Localization Systems Deployment. 133-145 - Yilei Li
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications. 146-158 - Weiwei Shi
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags. 159-167 - Congming Gao, Liang Shi
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives. 168-181 - Abhoy Kole
A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit. 182-192 - Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille:
Design of Application-Specific Architectures for Networked Labs-on-Chips. 193-202 - Wenmian Hua
Exact Timing Analysis for Asynchronous Systems. 203-216 - Xiaotao Jia
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. 217-230 - Derong Liu
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. 231-244 - Taehee Lee, David Z. Pan, Joon-Sung Yang
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. 245-256 - Dara Rahmati
Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS. 257-269
Volume 37, Number 2, February 2018
- Jaya Dofe, Qiaoyan Yu
Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation. 273-285 - Li Du
A Single Layer 3-D Touch Sensing System for Mobile Devices Application. 286-296 - Tobias Schwarzer
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. 297-310 - Lei Xie
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar. 311-323 - A. N. Nagamani
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits. 324-336 - Insik Yoon
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays. 337-349 - Hao Liang
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. 350-363 - Zhonghai Lu
xMAS-Based QoS Analysis Methodology. 364-377 - Michele Lora
Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms. 378-391 - Grace Li Zhang
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. 392-405 - Stephan Held, Dirk Müller, Daniel Rotter
Global Routing With Timing Constraints. 406-419 - Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. 420-430 - Shouyi Yin
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. 431-444 - Byunghoon Lee
Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning. 445-457 - Kyuseung Han, Jae-Jin Lee, Jinho Lee
TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. 458-471 - Bo Mao
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism. 472-484 - Tong-Yu Hsieh
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications. 485-498 - Arunkumar Vijayan
Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores. 499-511 - Sumayya Shiraz, Osman Hasan
A Library for Combinational Circuit Verification Using the HOL Theorem Prover. 512-516
Volume 37, Number 3, March 2018
- Ons Lahiouel
Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques. 517-530 - Yishi Yang, Hengliang Zhu
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. 531-544 - Yoon Seok Yang
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. 545-558 - Jae Hoon Lee, Min Soo Kim, Tae Hee Han
Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip. 559-572 - Yang Liu
Combating Coordinated Pricing Cyberattack and Energy Theft in Smart Home Cyber-Physical Systems. 573-586 - Debajyoti Bera
Detection and Diagnosis of Single Faults in Quantum Circuits. 587-600 - Zipeng Li
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip. 601-614 - Wajid Hassan Minhass, Jeffrey McDaniel
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip. 615-628 - Dries Vercruyce
How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance. 629-642 - Marco Donato
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. 643-656 - Yixiao Ding
Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration. 657-668 - Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. 669-681 - Travis Boraten
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures. 682-695 - Mehran Mozaffari Kermani
Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures. 696-704 - Yanchen Long
Composable Worst-Case Delay Bound Analysis Using Network Calculus. 705-709 - Konrad Möller
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. 710-714
Volume 37, Number 4, April 2018
- Tao-Chun Yu, Shao-Yun Fang
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. 717-728 - Xiaowei Xu
Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics. 729-741 - Anirban Sengupta
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis. 742-755 - Cheng Ji
An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache. 756-769 - Hengliang Zhu
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. 770-781 - Leibo Liu
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. 782-795 - Raouf Senhadji-Navarro
High-Performance Architecture for Binary-Tree-Based Finite State Machines. 796-805 - Mohammadreza Soltaniyeh, Ismail Kadayif
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs. 806-819 - Morteza Gholipour
Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors. 820-831 - Mohamed Baker Alawieh
Identifying Wafer-Level Systematic Failure Patterns via Unsupervised Learning. 832-844 - Sheng-En David Lin, Dae Hyun Kim
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs. 845-854 - Sorin Dobre, Andrew B. Kahng, Jiajia Li
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. 855-868 - Wuxi Li
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. 869-882 - Vasileios Tenentes
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs. 883-895 - Jiajia Chen
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications. 896-900 - Anita Aghaie, Mehran Mozaffari Kermani
Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA. 901-905 - Jaeil Lim, Hyunggoy Oh, Heetae Kim, Sungho Kang
Thermal Aware Test Scheduling for NTV Circuit. 906-910
Volume 37, Number 5, May 2018
- Szymon Szczesny
HDL-Based Synthesis System With Debugger for Current-Mode FPAA. 915-926 - Jin Miao
SD-PUF: Spliced Digital Physical Unclonable Function. 927-940 - Mengquan Li
Chip Temperature Optimization for Dark Silicon Many-Core Systems. 941-953 - Timo Feld
Exact Interference of Tasks With Variable Rate-Dependent Behavior. 954-967 - Zipeng Li
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. 968-981 - Giuseppe Tagliavini
Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. 982-995 - Alwin Zulehner
One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic. 996-1008 - Lixue Xia
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. 1009-1022 - Augusto Neutzling
A Simple and Effective Heuristic Method for Threshold Logic Identification. 1023-1036 - Mohammad Nazmus Sakib, Rakibul Hassan, Satyendra N. Biswas
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation. 1037-1049 - Mohamed Hassan
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. 1050-1063 - Arunkumar Vijayan
Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress. 1064-1075 - Amin Vali, Nicola Nicolici
Bit-Flip Detection-Driven Selection of Trace Signals. 1076-1089 - Chih-Hao Wang
On Probability of Detection Lossless Concurrent Error Detection Based on Implications. 1090-1103 - Yansong Gao
PUF-FSM: A Controlled Strong PUF. 1104-1108 - Tao Li, Qiang Liu
A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation. 1109-1113
Volume 37, Number 6, June 2018
- Jack Tang
Secure Randomized Checkpointing for Digital Microfluidic Biochips. 1119-1132 - Chung-Han Chou
Sensor-Based Time Speculation in the Presence of Timing Variability. 1133-1142 - Olga Krestinskaya
Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition. 1143-1156 - Qin Wang
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. 1157-1170 - Leibo Liu
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. 1171-1184 - Infall Syafalni
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM. 1185-1196 - Hsin-Ho Huang
Area Optimization of Timing Resilient Designs Using Resynthesis. 1197-1210 - Zhibin Yu
QIG: Quantifying the Importance and Interaction of GPGPU Architecture Parameters. 1211-1224 - Xiaoqing Xu
Subresolution Assist Feature Generation With Supervised Data Learning. 1225-1236 - Yibo Lin
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. 1237-1250 - Jian Kuang
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning. 1251-1264 - Ying Wang
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. 1265-1277 - Irith Pomeranz
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points. 1278-1287 - Yang Xue
Improving Diagnostic Resolution of Failing ICs Through Learning. 1288-1297 - Ryan Berryhill
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability. 1298-1311 - Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn
Automatic Selection of Process Corner Simulations for Faster Design Verification. 1312-1316
Volume 37, Number 7, July 2018
- Sandeep Chatterjee
Power Grid Electromigration Checking Using Physics-Based Models. 1317-1330 - Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim
CNFET-Based High Throughput SIMD Architecture. 1331-1344 - Daniele Rossi
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. 1345-1357 - Pengfei Qiu
Control Flow Integrity Based on Lightweight Encryption Architecture. 1358-1369 - Xiaoming Chen, Qiaoyi Liu, Song Yao, Jia Wang, Qiang Xu
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis. 1370-1383 - Minhui Zou, Xiaotong Cui
Potential Trigger Detection for Hardware Trojans. 1384-1395 - Sarath Mohanachandran Nair
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. 1396-1407 - Lin Liu, Hui Huang, Shiyan Hu:
Lorenz Chaotic System-Based Carbon Nanotube Physical Unclonable Functions. 1408-1421 - Saeideh Shirinzadeh
Logic Synthesis for RRAM-Based In-Memory Computing. 1422-1435 - Xiaoping Wang
A Novel Design for Memristor-Based Multiplexer Via NOT-Material Implication. 1436-1444 - Alper Demir
Numerical Analysis of Multidomain Systems: Coupled Nonlinear PDEs and DAEs With Noise. 1445-1458 - Alex Kahng, Andrew B. Kahng, Hyein Lee
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. 1459-1472 - Hayoung Lee
Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis. 1473-1482 - Xiaofeng Tang, Aiqiang Xu
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits. 1483-1493 - Irith Pomeranz
An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines. 1494-1504 - Xiaoping Wang
A Compact Scheme of Reading and Writing for Memristor-Based Multivalued Memory. 1505-1509 - Jea Woo Park
Litho-Aware Machine Learning for Hotspot Detection. 1510-1514
Volume 37, Number 8, August 2018
- Armin Alaghi
The Promise and Challenge of Stochastic Computing. 1515-1531 - Arman Iranfar
TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip. 1532-1545 - Jinhua Cui
DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. 1546-1559 - Yun Liang
Optimizing Cache Bypassing and Warp Scheduling for GPUs. 1560-1573 - Yibo Lin
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. 1574-1587 - Tsun-Ming Tseng
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips. 1588-1601 - Mohammad Ansari
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits. 1602-1613 - Inki Hong, Dae Hyun Kim
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits. 1614-1626 - Domenik Helms
Leakage Models for High-Level Power Estimation. 1627-1639 - M. Amimul Ehsan
A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC. 1640-1653 - Jin-Tai Yan
On-Chip Optical Channel Routing for Signal Loss Minimization. 1654-1666 - Ali Pahlevan
Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers. 1667-1680 - Muhammad Adil Ansari
Time-Multiplexed 1687-Network for Test Cost Reduction. 1681-1691 - Pramod Subramanyan
Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. 1692-1705 - Dekui Wang
A Runtime Optimization Approach for FPGA Routing. 1706-1710 - Wenjian Yu
Floating Random Walk-Based Capacitance Simulation Considering General Floating Metals. 1711-1715
Volume 37, Number 9, September 2018
- Baolei Mao
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design. 1719-1732 - Tongquan Wei
Cost-Constrained QoS Optimization for Approximate Computation Real-Time Tasks in Heterogeneous MPSoCs. 1733-1746 - Mungyu Son, Junwhan Ahn, Sungjoo Yoo
Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices. 1747-1759 - Ishan G. Thakkar
DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance. 1760-1773 - Zoha Pajouhi
Image Edge Detection Based on Swarm Intelligence Using Memristive Networks. 1774-1787 - Shaahin Angizi
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption. 1788-1801 - Junyi Liu
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. 1802-1815 - Ahmed S. Hussein
Reliable Hybrid Small-Signal Modeling of GaN HEMTs Based on Particle-Swarm-Optimization. 1816-1824 - Jinwook Jung
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. 1825-1838 - Eric Cheng
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). 1839-1852 - Ankit More, Vasil Pano
Vertical Arbitration-Free 3-D NoCs. 1853-1866 - Xiaoxiao Wang
Secure Scan and Test Using Obfuscation Throughout Supply Chain. 1867-1880 - Irith Pomeranz
Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads. 1881-1892 - Zissis Poulos
Failure Triage in RTL Regression Verification. 1893-1906 - Cunxi Yu
Fast Algebraic Rewriting Based on And-Inverter Graphs. 1907-1911 - Muhammad Adil Ansari, Jihun Jung, Dooyoung Kim, Sungju Park:
Erratum to "Time-Multiplexed-Network for Test Cost Reduction". 1912
Volume 37, Number 10, October 2018
- Fanshu Jiao, Hao Li, Alex Doboli:
Modeling and Extraction of Causal Information in Analog Circuits. 1915-1928 - Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, Xuan Zeng:
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. 1929-1942 - Hao Li, Xiaowei Liu, Fanshu Jiao, Alex Doboli, Simona Doboli
InnovA: A Cognitive Architecture for Computational Innovation Through Robust Divergence and Its Application for Analog Circuit Design. 1943-1956 - Jinhua Cui
ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs. 1957-1970 - Ying Wang, Huawei Li, Xiaowei Li
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. 1971-1984 - Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge:
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. 1985-1998 - Gholamreza Shomalnasab, Lihong Zhang:
Density-Uniformity-Aware Analog Layout Retargeting. 1999-2012 - Yuhan Zhou, Robert D. Nevels, Weiping Shi:
Capacitance Extraction With Provably Good Absorbing Boundary Conditions. 2013-2021 - Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. 2022-2035 - Jian Kuang, Evangeline F. Y. Young, Bei Yu:
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. 2036-2049 - Maxime Pelcat, Alexandre Mercat, Karol Desnos, Luca Maggiani, Yanzhou Liu, Julien Heulot, Jean-François Nezan, Wassim Hamidouche, Daniel Ménard, Shuvra S. Bhattacharyya:
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice. 2050-2063 - Zhuo Chen, Dimitrios Stamoulis, Diana Marculescu
Profit: Priority and Power/Performance Optimization for Many-Core Systems. 2064-2075 - Haoran Li
Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors. 2076-2086 - Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. 2087-2097 - Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril, Krishnendu Chakrabarty
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops. 2098-2110 - Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty
Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis. 2111-2124 - Haralampos-G. D. Stratigopoulos, Christian Streitwieser:
Adaptive Test With Test Escape Estimation for Mixed-Signal ICs. 2125-2138 - Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement. 2139-2151 - Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. 2152-2165 - Yun Cheng, Huawei Li, Ying Wang, Haihua Shen, Bo Liu, Xiaowei Li
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. 2166-2179 - Paolo Maffezzoni
Variation-Aware Modeling of Integrated Capacitors Based on Floating Random Walk Extraction. 2180-2184
Volume 37, Number 11, November 2018
- Soonhoi Ha
Editorial. 2187 - Yecheng Zhao, Vinit Gala, Haibo Zeng:
A Unified Framework for Period and Priority Optimization in Distributed Hard Real-Time Systems. 2188-2199 - Jinghao Sun
A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF. 2200-2211 - Foivos Tsimpourlas, Lazaros Papadopoulos
A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices. 2212-2221 - Tao Qian, Frank Mueller
A Failure Recovery Protocol for Software-Defined Real-Time Networks. 2222-2232 - Stefan Jaksic
An Algebraic Framework for Runtime Verification. 2233-2243 - Jorge Martinez
Analytical Characterization of End-to-End Communication Delays With Logical Execution Time. 2244-2254 - Wei Zhang
Analyzing Data Cache Related Preemption Delay With Multiple Preemptions. 2255-2265 - Sanchari Sen
Approximate Computing for Long Short Term Memory (LSTM) Neural Networks. 2266-2276 - Vincent T. Lee
Architecture Considerations for Stochastic Computing Accelerators. 2277-2289 - N. Asokan
ASSURED: Architecture for Secure Software Update of Realistic Embedded Devices. 2290-2300 - Inpyo Bae, Barend Harris, Hyemi Min, Bernhard Egger
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators. 2301-2310 - Jiangchao Liu
Automatic Verification of Embedded System Code Manipulating Dynamic Structures Stored in Contiguous Regions. 2311-2322 - Mohamed Hassan
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems. 2323-2336 - Marvin Damschen
Co-Scheduling on Fused CPU-GPU Architectures With Shared Last Level Caches. 2337-2347 - Zhuoran Zhao
DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters. 2348-2359 - Duckhwan Kim
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks. 2360-2370 - Ekdeep Singh Lubana
Digital Foveation: An Energy-Aware Machine Vision Framework. 2371-2380 - Debasmita Lohar
Discrete Choice in the Presence of Numerical Uncertainties. 2381-2392 - Gang Chen
EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions. 2393-2403 - Zhuoqun Cheng, Richard West
End-to-End Analysis and Design of a Drone Flight Controller. 2404-2415 - Anway Mukherjee
Energy Management of Applications With Varying Resource Usage on Smartphones. 2416-2427 - Lei Mo
Energy-Quality-Time Optimized Task Mapping on DVFS-Enabled Multicores. 2428-2439 - Chen Pan
ENZYME: An Energy-Efficient Transient Computing Paradigm for Ultralow Self-Powered IoT Edge Devices. 2440-2450 - Jordi Cardona
EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems. 2451-2461 - Georgios Mappouras
Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice. 2462-2473 - Antonio Anastasio Bruto da Costa
Formal Feature Interpretation of Hybrid Systems. 2474-2484 - Debiprasanna Sahoo
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. 2485-2496 - Philipp Miedl
Frequency Scaling As a Security Threat on Multicore Systems. 2497-2508 - Seaghan Sefton
GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow. 2509-2518 - Jiale Yan, Shouyi Yin
GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. 2519-2529 - Siting Liu
Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines. 2530-2541 - Weiwen Jiang, Edwin Hsing-Mean Sha
Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs. 2542-2554 - Tingyuan Liang
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. 2555-2566 - Chun-Feng Wu
Hot-Spot Suppression for Resource-Constrained Image Recognition Devices With Nonvolatile Memory. 2567-2577 - Alain Girault, Christophe Prévot
Improving and Estimating the Precision of Bounds on the Worst-Case Latency of Task Chains. 2578-2589 - Miao-Chiang Yen
Lightweight, Integrated Data Deduplication for Write Stress Reduction of Mobile Flash Storage. 2590-2600 - Lei Gong
MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip. 2601-2612 - Hyunsung Shin
McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM. 2613-2622 - Hassaan Saadat
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication. 2623-2635 - Jiali Teddy Zhai, Sobhan Niknam
Modeling, Analysis, and Hard Real-Time Scheduling of Adaptive Streaming Applications. 2636-2648 - Masaki Waga
Moore-Machine Filtering for Timed and Untimed Pattern Matching. 2649-2660 - Lei Ju
NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion. 2661-2672 - Jyothi Krishna V. S
Optimizing Graph Algorithms in Asymmetric Multicore Processors. 2673-2684 - Luca Piccolboni
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators. 2685-2696 - Joost van Pinxten
Parametric Critical Path Analysis for Event Networks With Minimal and Maximal Time Lags. 2697-2708 - Fanruo Meng
Power- and Endurance-Aware Neural Network Training in NVM-Based Platforms. 2709-2719 - Mohammad Shihabul Haque
Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores. 2720-2731 - Maral Amir
Priority Neuron: A Resource-Aware Neural Network for Cyber-Physical Systems. 2732-2742 - Chenchen Fu
Real-Time Data Retrieval With Multiple Availability Intervals in CPS Under Freshness Constraints. 2743-2754 - Sobhan Niknam
Resource Optimization for Real-Time Streaming Applications Using Task Replication. 2755-2767 - Yifan Zhang
Safety Verification of Nonlinear Hybrid Systems Based on Bilinear Programming. 2768-2778 - Jonathan Bailey
Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs. 2779-2789 - Wei-Chen Wang
Scrubbing-Aware Secure Deletion for 3-D NAND Flash. 2790-2801 - Tanfer Alan
SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling. 2802-2811 - Sudipta Chattopadhyay
Symbolic Verification of Cache Side-Channel Freedom. 2812-2823 - Mischa Möstl
Synthesis of Monitors for Networked Systems With Heterogeneous Safety Requirements. 2824-2834 - Dustin Richmond
Synthesizable Higher-Order Functions for C++. 2835-2844 - Lingtai Wang, Naijun Zhan
The Opacity of Real-Time Automata. 2845-2856 - Youngmoon Lee
Thermal-Aware Resource Management for Embedded Real-Time Systems. 2857-2868 - Jin Hyun Kim
Towards Overhead-Free Interface Theory for Compositional Hierarchical Real-Time Systems. 2869-2880 - Nitthilan Kannappan Jayakodi
Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach. 2881-2893 - Zhenya Zhang
Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo Tree Search. 2894-2905 - Glen Chou
Using Control Synthesis to Generate Corner Cases: A Case Study on Autonomous Driving. 2906-2917 - Shunzhuo Wang
WARD: Wear Aware RAID Design Within SSDs. 2918-2928 - Matthias Wess
Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation. 2929-2939 - Francesco Conti
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference. 2940-2951 - Hyesun Hong
SeMo: Service-Oriented and Model-Based Software Framework for Cooperating Robots. 2952-2963
Volume 37, Number 12, December 2018
- Farshad Firouzi
Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions. 2965-2978 - Mohamed Baker Alawieh
Efficient Hierarchical Performance Modeling for Analog and Mixed-Signal Circuits via Bayesian Co-Learning. 2986-2998 - Paolo Maffezzoni
Exploiting Oscillator Arrays As Randomness Sources for Cryptographic Applications. 2999-3007 - Ming Tang
Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes. 3008-3019 - Michael Chen, Elham K. Moghaddam
Hardware Protection via Logic Locking Test Points. 3020-3030 - Frank Sill Torres
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata. 3031-3041 - Kailin Yang
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. 3042-3055 - Aidyn Zhakatayev
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. 3056-3066 - Pai-Yu Chen
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. 3067-3080 - Leibo Liu
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. 3081-3094 - Ibrahim Ahmed
Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs. 3095-3108 - Xuesong Peng
Stochastic Circuit Synthesis by Cube Assignment. 3109-3122 - Scott Ladenheim, Yi-Chung Chen
The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems. 3123-3136 - Zeyu Sun, Ertugrul Demircan, Mehul D. Shroff
Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires. 3137-3150 - Ioannis Messaris
A Data-Driven Verilog-A ReRAM Model. 3151-3162 - Siad Daboul
Provably Fast and Near-Optimum Gate Sizing. 3163-3176 - Panagiotis Georgiou, Fotis Vartziotis
Testing 3D-SoCs Using 2-D Time-Division Multiplexing. 3177-3185 - Jing Ye
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function. 3186-3197 - Ai Quoc Dao, Mark Po-Hung Lin
SAT-Based Fault Equivalence Checking in Functional Safety Verification. 3198-3205 - Le Tu
Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs. 3206-3210 - Wei-Che Wang, Charles Zhao, Puneet Gupta
Assessing Layout Density Benefits of Vertical Channel Devices. 3211-3215 - Liang-Ying Lu
Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis. 3216-3220 - Ananya Bose
Conditional Differential Coefficients Method for the Realization of Powers-of-Two FIR Filter. 3221-3225
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