A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The OpenPiton Platform

Functional verification project for the CORE-V family of RISC-V cores.

A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered by SpinalHDL and Verilator. Supports running simple OS like u…