A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC
CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC .
VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
Simple calculator implemented in VHDL using FSM logic
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022
Final project of Logical Networks course - Politecnico di Milano 2022/23
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
VHDL Implementation of Modulo2 Line by Matrix Multiplication (with Tutorial Series on Steemit)
A modular, synthesizable elevator control system implemented in VHDL with configurable floor count, request handling, FSM-based control, and 7-segment display output for FPGA implementation
FSM and Cache design for practicing the concepts of computer architecture
This project implements a complete UART communication system in VHDL, where a transmitter sends serial data, a receiver reconstructs it using mid-bit sampling, and a testbench automatically verifies correctness using simulation and waveforms.
Sistema de clasificación de objetos con VHDL y visión artificial usando red neuronal Python
An Elevator Control System engineered in VHDL using an advanced Finite State Machine (FSM) architecture, featuring concurrent behavioral logic and real-time testbench simulation.
Collection of RTL design projects implemented in VHDL and Verilog, including controllers, FSMs, and FPGA-ready modules.
FPGA implementation of SPI with BMP580 sensor and EEPROM memory using VHDL on ARTY S7-25