Scribd
Upload
8 views1 page

My Learn

The document provides technical specifications for the DS3231, an extremely accurate I2C-integrated RTC/TCXO/crystal. It includes details on timing parameters, voltage references, and operational conditions, particularly at low temperatures. Various notes clarify the device's functionality and requirements for proper operation within an I2C system.

Uploaded by

eie.ken.lee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
8 views1 page

My Learn

The document provides technical specifications for the DS3231, an extremely accurate I2C-integrated RTC/TCXO/crystal. It includes details on timing parameters, voltage references, and operational conditions, particularly at low temperatures. Various notes clarify the device's functionality and requirements for proper operation within an I2C system.

Uploaded by

eie.ken.lee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

DS3231 Extremely Accurate I2C-Integrated

RTC/TCXO/Crystal

SDA

tBUF tSP
tHD:STA
tLOW tF
tR

SCL

tHD:STA tHIGH tSU:STA


tSU:STO
STOP START tSU:DAT REPEATED
START
tHD:DAT

Note 2:
Limits at -40°C are guaranteed by design and not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
ICCA—SCL clocking at max frequency = 400kHz.
Note 5:
Current is the averaged input current, which includes the temperature conversion current.
Note 6:
The CC.
Note 7:
After this period, the first clock pulse is generated.
Note 8:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 9: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 11: CB—total capacitance of one bus line in pF.
Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range
CC CC(MAX) BAT
Note 13: This delay applies only if the oscillator is enabled and running. If the bit is a 1, tREC is bypassed and immedi-
ately goes high. The state of does not affect the I2C interface, RTC, or TCXO.

www.maximintegrated.com Maxim Integrated 6

You might also like