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ISSCC 2018: San Francisco, CA, USA
- 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. IEEE 2018, ISBN 978-1-5090-4940-0
- Vincent Roche:
Semiconductor innovation: Is the party over, or just getting started? 8-11 - Barbara De Salvo:
Brain-Inspired technologies: Towards chips that think? 12-18 - Yukihiro Kato:
Future mobility-enhanced society enabled by semiconductor technology. 21-26 - David A. Patterson:
50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set. 27-31 - Thomas Burd, Muhammad M. Khellah, Byeong-Gyu Nam:
Session 2 overview: Processors: Digital architectures and systems subcommittee. 32-33 - Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang:
SkyLake-SP: A 14nm 28-Core xeon® processor. 34-36 - Christopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Arthur O'neill, Robert J. Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves:
IBM z14™: 14nm microprocessor for the next-generation mainframe. 36-38 - Pascal Meinerzhagen, Carlos Tokunaga
, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. 38-40 - Noah Beck, Sean White, Milam Paraschou, Samuel Naffziger:
'Zeppelin': An SoC for multichip architectures. 40-42 - Utsav Banerjee
An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications. 42-44 - Longyang Lin, Saurabh Jain, Massimo Alioto:
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing. 44-46 - Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. 46-48 - Youngcheol Chae, Mahdi Kashmiri, Kofi A. A. Makinwa:
Session 3 overview: Analog techniques: Analog subcommittee. 48-49 - Thije Rooijers, Johan H. Huijsing, Kofi A. A. Makinwa:
A quiet digitally assisted auto-zero-stabilized voltage buffer with 0.6pA input current and offset. 50-52 - Ka-Meng Lei
A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power. 52-54 - Cagri Gurleyuk, Lorenzo Pedala, Fabio Sebastiano
A CMOS Dual-RC frequency reference with ±250ppm inaccuracy from -45°C to 85°C. 54-56 - Eric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, Michael Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille:
A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power level. 56-58 - Wen-Chieh Wang
A 0.0004% (-108dB) THD+N, 112dB-SNR, 3.15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques. 58-60 - Shih-Hsiung Chien, Yi-Wen Chen, Tai-Haur Kuo:
A 0.96mA quiescent current, 0.0032% THD+N, 1.45W Class-D audio amplifier with area-efficient PWM-residual-aliasing reduction. 60-62 - Shinwoong Park
A low-power 3.25GS/s 4th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing. 62-64 - Chun-Huat Heng, David McLaurin, Stefano Pellerano:
Session 4 overview: mm-Wave radios for 5G and beyond: Wireless subcommittee. 64-65 - Tirdad Sowlati, Saikat Sarkar, Bevin G. Perumana, Wei Liat Chan, Bagher Afshar, Michael Boers, Donghyup Shin, Timothy Mercer, Wei-Hong Chen, Anna Papio Toda, Alfred Grau Besoli
A 60GHz 144-element phased-array transceiver with 51dBm maximum EIRP and ±60° beam steering for backhaul application. 66-68 - Min-Yu Huang, Taiyun Chi, Fei Wang, Tso-Wei Li, Hua Wang
A 23-to-30GHz hybrid beamforming MIMO receiver array with closed-loop multistage front-end beamformers for full-FoV dynamic and autonomous unknown signal tracking and blocker rejection. 68-70 - Jeremy D. Dunworth
A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipment. 70-72 - Susnata Mondal
A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation. 72-74 - Shahriar Shahramian, Mike Holyoak, Amit Singh
A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test. 74-76 - Taiyun Chi, Jong Seok Park, Sensen Li, Hua Wang
A 64GHz full-duplex transceiver front-end with an on-chip multifeed self-interference-canceling antenna and an all-passive canceler supporting 4Gb/s modulation in one antenna footprint. 76-78 - Hayato Wakabayashi, Makoto Ikeda:
Session 5 overview: Image sensors: IMMD subcommittee. 78-79 - Masaki Sakakibara
A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC. 80-82 - Kazuko Nishimura, Sanshiro Shishido, Yasuo Miyake, Masaaki Yanagida, Yoshiaki Satou, Makoto Shouho, Hidenari Kanehara, Ryota Sakaida, Yoshihiro Sato, Junji Hirase, Yuko Tomekawa, Yutaka Abe, Hiroshi Fujinaka, Yoshiyuki Matsunaga, Masashi Murakami, Mitsuru Harada, Yasunori Inoue:
An 8K4K-resolution 60fps 450ke--saturation-signal organic-photoconductive-film global-shutter CMOS image sensor with in-pixel noise canceller. 82-84 - Yitae Kim, Wonchul Choi, Donghyuk Park, Heegeun Jeoung, Bumsuk Kim, Youngsun Oh, Sunghoon Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, Taesub Jung, Yongwoon Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang:
A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation. 84-86 - Oichi Kumagai, Atsumi Niwa, Katsuhiko Hanzawa, Hidetaka Kato, Shinichiro Futami, Toshio Ohyama, Tsutomu Imoto, Masahiko Nakamizo, Hirotaka Murakami, Tatsuki Nishino, Anas Bostamam, Takahiro Iinuma, Naoki Kuzuya, Kensuke Hatsukawa, Frederick T. Brady, William Bidermann, Toshifumi Wakano, Takashi Nagano, Hayato Wakabayashi, Yoshikazu Nitta:
A 1/4-inch 3.9Mpixel low-power event-driven back-illuminated stacked CMOS image sensor. 86-88 - Po-Sheng Chou, Chin-Hao Chang, Manoj M. Mhala, Charles Chih-Min Liu, Calvin Yi-Ping Chao, Chiao-Yi Huang, Honyih Tu, Thomas Meng-Hsiu Wu, Shang-Fu Yeh, Seiji Takahashi, Yi-Min Huang:
A 1.1μm-Pitch 13.5Mpixel 3D-stacked CMOS image sensor featuring 230fps full-high-definition and 514fps high-definition videos by reading 2 or 3 rows simultaneously using a column-switching matrix. 88-90 - Toshio Yasue, Kohei Tomioka, Ryohei Funatsu, Tomohiro Nakamura, Takahiro Yamasaki, Hiroshi Shimamoto, Tomohiko Kosugi, Sung-Wook Jun, Takashi Watanabe, Masanori Nagase, Toshiaki Kitajima, Satoshi Aoyama, Shoji Kawahito:
A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode. 90-92 - Kentaro Yoshioka
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. 92-94 - Cyrus S. Bamji, Swati Mehta, Barry Thompson, Tamer A. Elkhatib
IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binning. 94-96 - Augusto Ronchini Ximenes, Preethi Padmanabhan, Myung-Jae Lee, Yuichiro Yamashita, Dun-Nian Yaung, Edoardo Charbon:
A 256×256 45/65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6dB interference suppression. 96-98 - Leonardo Gasparini
A 32×32-pixel time-resolved single-photon image sensor with 44.64μm pitch and 19.48% fill-factor with on-chip row/frame skipping features reaching 800kHz observation rate for quantum physics applications. 98-100 - Mounir Meghelli, Hyeon-Min Bae, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. 100-101 - Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. 102-104 - Christian Menolfi, Matthias Braendli
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. 104-106 - Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr:
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. 106-108 - Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang:
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. 108-110 - Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone
A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. 110-112 - Emanuele Depaoli, Enrico Monaco, Giovanni Steffan, Marco Mazzini, Hongyang Zhang, Walter Audoglio, Oscar Belotti, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Andrea Mazzanti:
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. 112-114 - Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. 114-116 - Youngmin Shin, Phillip J. Restle, Edith Beigné:
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. 116-117 - Shiheng Yang, Jun Yin
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. 118-120 - Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko:
A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. 120-122 - Minseob Lee, Shinwoong Kim, Hwasuk Cho, Jahyun Koo, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC. 122-124 - Anvesha Amaravati, Saad Bin Nasir
A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robots. 124-126 - Wen-Hau Yang, Li-Cheng Chu, Shang-Hsien Yang, Yan-Jiun Lai, Shao-Qi Chen, Ke-Horng Chen
An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) Devices. 126-128 - Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. 128-130 - Meng-Yi Wu, Tsao-Hsin Yang, Lun-Chun Chen, Chi-Chang Lin, Hao-Chun Hu, Fang-Ying Su, Chih-Min Wang, James Po-Hao Huang, Hsin-Ming Chen, Chris Chun-Hung Lu, Evans Ching-Song Yang, Rick Shih-Jye Shen:
A PUF scheme using competing oxide rupture with bit error rate approaching zero. 130-132 - Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee
A 445F2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security. 132-134 - Yuan Gao, Zhiliang Hong, Axel Thomsen:
Session 8 overview: Wireless power and harvesting: Power management subcommittee. 134-135 - Kamala Raghavan Sadagopan
A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless Powering. 136-138 - Che-Hao Yeh, Yen-Ting Lin, Chun-Chieh Kuo, Chao-Jen Huang, Cheng-Yu Xie, Shen-Fu Lu, Wen-Hau Yang, Ke-Horng Chen
A 70W and 90% GaN-based class-E wireless-power-transfer system with automatic-matching-point-search control for zero-voltage switching and zero-voltage-derivative switching. 138-140 - Fangyu Mao, Yan Lu, Seng-Pan U., Rui Paulo Martins:
A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. 140-142 - Yu Wang, Dawei Ye
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. 142-144 - Sally Safwat Amin, Patrick P. Mercier
MISIMO: A multi-input single-inductor multi-output energy harvester employing event-driven MPPT control to achieve 89% peak efficiency and a 60, 000x dynamic range in 28nm FDSOI. 144-146 - Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage. 146-148 - Yifeng Cai, Yiannos Manoli:
A piezoelectric energy-harvesting interface circuit with fully autonomous conjugate impedance matching, 156% extended bandwidth, and 0.38μW power consumption. 148-150 - Anthony Quelen, Adrien Morel
A 30nA quiescent 80nW-to-14mW power-range shock-optimized SECE-based piezoelectric harvesting interface with 420% harvested-energy improvement. 150-152 - Sijun Du
A fully integrated split-electrode synchronized-switch-harvesting-on-capacitors (SE-SSHC) rectifier for piezoelectric energy harvesting with between 358% and 821% power-extraction enhancement. 152-154 - Se-un Shin, Minseong Choi, Seok-Tae Koh, Yu-Jin Yang, Seungchul Jung, Young-Hoon Sohn, Se-Hong Park
A 13.56MHz time-interleaved resonant-voltage-mode wireless-power receiver with isolated resonator and quasi-resonant boost converter for implantable systems. 154-156 - Alan Wong, Xin He, Stefano Pellerano:
Session 9 overview: Wireless transceivers and techniques: Wireless subcommittee. 156-157 - Brian P. Ginsburg
A multimode 76-to-81GHz automotive radar transceiver with autonomous monitoring. 158-160 - Liheng Lou, Kai Tang, Bo Chen, Ting Guo, Yisheng Wang, Wensong Wang, Zhongyuan Fang
A 253mW/channel 4TX/4RX pulsed chirping phased-array radar TRX in 65nm CMOS for X-band synthetic-aperture radar imaging. 160-162 - David J. McLaurin, Kevin G. Gard, Richard P. Schubert, Manish J. Manglani, Haiyang Zhu, David Alldred, Zhao Li, Steven R. Bal, Jianxun Fan, Oliver E. Gysel, Christopher M. Mayer, Tony Montalvo:
A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations. 162-164 - Shinwon Kang, Chintan Thakkar, Nathan Narevsky, Kaushik Dasgupta, Saeid Daneshgar, James E. Jaussi, Bryan Casper:
A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO. 164-166 - Saeid Daneshgar, Kaushik Dasgupta, Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper:
A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO. 166-168 - Korkut Kaan Tokgoz
A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. 168-170 - Kun-Da Chu, Mohamad Katanbaf, Tong Zhang, Chenxin Su, Jacques Christophe Rudell:
A broadband and deep-TX self-interference cancellation technique for full-duplex and frequency-domain-duplex transceiver applications. 170-172 - Qing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho:
A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS. 172-174 - Bagher Rabet, James F. Buckwalter:
A high-efficiency 28GHz outphasing PA with 23dBm output power using a triaxial balun combiner. 174-176 - Michael Kraft, Masayuki Miyamoto, Makoto Ikeda:
Session 10 overview: Sensor systems: IMMD subcommittee. 176-177 - Burak Eminoglu, Bernhard E. Boser:
Chopped rate-to-digital FM gyroscope with 40ppm scale factor accuracy and 1.2dph bias. 178-180 - Qingbo Guo, William Deng, Ozkan Bebek
Personal inertial navigation system employing MEMS wearable ground reaction sensor array and interface ASIC achieving a position accuracy of 5.5m over 3km walking distance without GPS. 180-182 - Jae-Sung An, Sang-Hyun Han, Kyeong-Bin Park, Ju Eon Kim, Jae-Hun Ye, Seung-Hwan Lee, Ji-Yong Jeong, Jung Soo Kim, Kwang-Hyun Baek, Ki-Seok Chung, Seong-Kwan Hong, Oh-Kyong Kwon:
Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels. 182-184 - Kyung-Hoon Lee, Sang-Pil Nam, Jung-Ho Lee, Michael Choi, Hyung-Jong Ko, San-Ho Byun, Jin-chul Lee, Yong-Hoon Lee, Yeong-Cheol Rhee, Yoon-Kyung Choi, Byunghoon Kang, Changbyung Park, Sungsoo Park, Taesung Kim:
A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses. 184-186 - Chao Chen, Zhao Chen, Deep Bera, Emile Noothout, Zu-yao Chang, Mingliang Tan
A 0.91mW/element pitch-matched front-end ASIC with integrated subarray beamforming ADC for miniature 3D ultrasound probes. 186-188 - Gwangrok Jung, M. Wasequr Rashid, Thomas M. Carpenter, Coskun Tekes, David M. J. Cowell, Steven Freear
Single-chip reduced-wire active catheter system with programmable transmit beamforming and receive time-division multiplexing for intracardiac echocardiography. 188-190 - Constantine Sideris, Parham Porsandeh Khial, Bill Ling
A 0.3ppm dual-resonance transformer-based drift-cancelling reference-free magnetic sensor for biosensing applications. 190-192 - Kiduk Kim, Seunghyun Park, Kye-Seok Yoon, Gyeong-Gu Kang, Hyun-Ki Han, Ji-Su Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee
A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm2 1.89μVrms noise 12b biasing DAC. 192-194 - Jonathan Chang, Chun Shiah, Leland Chang:
Session 11 overview: SRAM: Memory subcommittee. 194-195 - Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl:
A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. 196-198 - Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon:
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. 198-200 - Michael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang:
A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications. 200-201 - Seung-Jun Bae, Wolfgang Spirkl, Leland Chang:
Session 12 overview: DRAM: Memory subcommittee. 202-203 - Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. 204-206 - Ki Chul Chun, Yonggyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. 206-208 - Jin-Hee Cho, Jihwan Kim, Wooyoung Lee, Dong-Uk Lee, Tae-Kyun Kim, Heat Bit Park, Chunseok Jeong, Myeong-Jae Park, Seung Geun Baek, Seokwoo Choi, Byung Kuk Yoon, Young Jae Choi, Kyo Yun Lee, Daeyong Shim, Jonghoon Oh, Jinkook Kim, Seok-Hee Lee:
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control. 208-210 - Kyu-Dong Hwang, Boram Kim, Sang-Yeon Byeon, Kyu-Young Kim, Dae-Han Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-Young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee:
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. 210-212 - Seokbo Shim, Sungho Kim, Jooyoung Bae, Keunsik Ko, Eunryeong Lee, Kwidong Kim, Kyeongtae Kim, Sangho Lee, Jinhoon Hyun, Insung Koh, Joonhong Park, Minjeong Kim, Sunhye Shin, Dongha Lee, Yunyoung Lee, Sangah Hyun, Wonjohn Choi, Dain Im, Dongheon Lee, Jieun Jang, Sangho Lee, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee:
A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy. 212-214 - Dejan Markovic, Masato Motomura, Byeong-Gyu Nam:
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee. 214-215 - Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. 216-218 - Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sangyeob Kim, Hoi-Jun Yoo:
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision. 218-220 - Sungpill Choi, Jinsu Lee, Kyuho Jason Lee
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices. 220-222 - Daniel Bankman, Lita Yang, Bert Moons, Marian Verhelst
An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS. 222-224 - Wei Tang, Hemanth Prabhu, Liang Liu
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. 224-226 - Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu:
A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring. 226-228 - Matt Straayer, Seung-Tak Ryu, Un-Ku Moon:
Session 14 overview: High-resolution ADCs: Data converter subcommittee. 228-229 - Tao He, Michael Ashburn, Stacy Ho, Yi Zhang, Gabor C. Temes:
A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. 230-232 - Hariprasad Chandrakumar, Dejan Markovic:
A 15.2-ENOB continuous-time ΔΣ ADC for a 200mVpp-linear-input-range neural recording front-end. 232-234 - Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun:
A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. 234-236 - Patrick Vogelmann, Michael Haas, Maurits Ortmanns:
A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction. 236-238 - Shoubhik Karmakar, Burak Gonen, Fabio Sebastiano
A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW. 238-240 - Sung-En Hsieh, Chih-Cheng Hsieh:
A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator. 240-242 - Hongxing Li, Mark Maddox, Michael C. W. Coln, William Buckley, Derek Hummerston, Naveed Naeem:
A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL. 242-244 - Jiayoon Ru, Jaehyouk Choi, Piet Wambacq:
Session 15 overview: RF PLLs: RF subcommittee. 244-245 - Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. 246-248 - Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. 248-250 - Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn:
A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter. 250-252 - Luca Bertulessi
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. 252-254 - Cheng-Ru Ho, Mike Shuo-Wei Chen:
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. 254-256 - Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar:
A 0.01mm2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with -254dB FOM. 256-258 - Jahnavi Sharma, Harish Krishnaswamy:
A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc Reference Spurs. 258-260 - Zhiqiang Huang, Howard Cam Luong:
An 82-to-108GHz -181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC. 260-262 - Azita Emami, Andrew K. Joy, Frank O'Mahony:
Session 16 overview: Advanced optical and wireline techniques: Wireline subcommittee. 262-263 - Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae:
A 28Gb/s transceiver with chirp-managed EDC for DML systems. 264-266 - Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. 266-268 - Ashwin Ramachandran, Tejasvi Anand:
A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS. 268-270 - Sejun Jeon, Woohyun Kwon
A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS. 270-272 - Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces. 272-274 - Marc Erett, Declan Carey, James Hudner, Ronan Casey, Kevin Geary, Pedro Neto, Mayank Raj, Scott McLeod, Hongtao Zhang, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Kee Hian Tan, Yohan Frans, Ken Chang:
A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET. 274-276 - John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. 276-278 - Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang:
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. 278-280 - Patrick P. Mercier, Long Yan, Makoto Nagata:
Session 17 overview: Technologies for health and society: Technology directions subcommittee. 280-281 - Jaeeun Jang, Jihee Lee, Kyoung-Rog Lee, Jiwon Lee, Minseo Kim, Yongsu Lee, Joonsung Bae, Hoi-Jun Yoo:
4-Camera VGA-resolution capsule endoscope with 80Mb/s body-channel communication transceiver and Sub-cm range capsule localization. 282-284 - Ali Fazli Yeknami, Xiaoyang Wang, Somayeh Imani, Ali Nikoofard
A 0.3V biofuel-cell-powered glucose/lactate biosensing system employing a 180nW 64dB SNR passive δς ADC and a 920MHz wireless transmitter. 284-286 - Guangyang Qu, Hanqing Wang, Yimiao Zhao, John O'Donnell, Colin Lyden, Yincai Liu, Junbiao Ding, Dennis Dempsey, Leicheng Chen, Donal Bourke, Shurong Gu, Jun Gao, Lizhu Lu, Li Wang, Xuemin Li, Hongxing Li, Chao Chu, Ling Yang:
A 0.28mΩ-sensitivity 105dB-dynamic-range electrochemical impedance spectroscopy soc for electrochemical gas detection. 286-288 - Maged ElAnsary
50nW 5kHz-BW opamp-less ΔΣ impedance analyzer for brain neurochemistry monitoring. 288-290 - Wen Li, Yida Duan, Jan M. Rabaey:
A 200Mb/s inductively coupled wireless transcranial transceiver achieving 5e-11 BER and 1.5pJ/b transmit energy efficiency. 290-292 - Sunwoo Lee, Alejandro J. Cortese
A 330μm×90μm opto-electronically integrated wireless system-on-chip for recording of neural activities. 292-294 - Jiawei Xu, Mario Konijnenburg, Budi Lukita, Shuang Song
A 665μW silicon photomultiplier-based NIRS/EEG/EIT monitoring asic for wearable functional brain imaging. 294-296 - Gerard O'Leary, Mohammad Reza Pazhouhandeh, Michael Chang
A recursive-memory brain-state classifier with 32-channel track-and-zoom Δ2 Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators. 296-298 - Dennis Sylvester, Koji Hirairi, Edith Beigné:
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee. 298-299 - Christos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. 300-302 - Xun Sun, Sung Kim
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. 302-304 - Anthony Quelen, Gaël Pillonnet
A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range. 304-306 - Xiaofei Ma, Yan Lu, Rui Paulo Martins
A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS. 306-308 - Somnath Kundu
A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning. 308-310 - Yasu Lu, Fan Yang
A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOS. 310-312 - Loai G. Salem, Patrick P. Mercier
A sub-1.55mV-accuracy 36.9ps-FOM digital-low-dropout regulator employing switched-capacitor resistance. 312-314 - Jian-He Lin, Yu-Sheng Ma, Chia-Ming Huang, Li-Chi Lin, Chiao-Hung Cheng, Ke-Horng Chen
A high-efficiency and fast-transient digital-low-dropout regulator with the burst mode corresponding to the power-saving modes of DC-DC switching converters. 314-316 - Man-Kay Law, Taeik Kim, Kofi A. A. Makinwa:
Session 19 overview: Sensors and interfaces: Analog subcommittee. 316-317 - Cho-Ying Lu, Surej Ravikumar, Amruta D. Sali, Matthias Eberlein
An 8b subthreshold hybrid thermal sensor with ±1.07°C inaccuracy and single-element remote-sensing technique in 22nm FinFET. 318-320 - Sining Pan, Kofi A. A. Makinwa:
A 0.25mm2 resistor-based temperature sensor with an inaccuracy of 0.12°C (3σ) from -55°C to 125°C and a resolution FOM of 32fJK2. 320-322 - Woojun Choi, Yong-Tae Lee, Seonhong Kim, Sanghoon Lee, Jieun Jang, Junhyun Chun, Kofi A. A. Makinwa, Youngcheol Chae:
A 0.53pJK2 7000μm2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS. 322-324 - Long Xu, Johan H. Huijsing, Kofi A. A. Makinwa:
A ±4A high-side current sensor with 25V input CM range and 0.9% gain error from -40°C to 85°C using an analog temperature compensation technique. 324-326 - Chung-Lun Hsu, Drew A. Hall
A current-measurement front-end with 160dB dynamic range and 7ppm INL. 326-328 - Sechang Oh
A 2.5nJ duty-cycled bridge-to-digital converter integrated in a 13mm3 pressure-sensing system. 328-330 - Jaehoon Jun
A 21.8b sub-100μHz 1/f corner 2.4μV-offset programmable-gain read-out IC for bridge measurement systems. 330-332 - Zeyu Cai, Robert H. M. van Veldhoven, Hilco Suy, Ger de Graaf, Kofi A. A. Makinwa, Michiel A. P. Pertijs:
A phase-domain readout circuit for a CMOS-compatible thermal-conductivity-based carbon dioxide sensor. 332-334 - Ki-Tae Park, Yan Li, Leland Chang:
Session 20 overview: Flash-memory solutions: Memory subcommittee. 334-335 - Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, Ryo Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Yuki Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, Masatsugu Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, Naoki Kobayashi, Makoto Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Yusuke Ochi, Kenro Kubota, Taichi Wakui, Dong He, Weihan Wang, Hiroe Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Lih Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, Takuya Futatsuyama, Koji Hosono, Noboru Shibata, Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura:
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. 336-338 - Wooseong Cheong, Chanho Yoon, Seonghoon Woo, Kyuwook Han, Daehyun Kim, Chulseung Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jaechun Park, Ki-Whan Song, Ki-Tae Park, Sangyeun Cho, Hwaseok Oh, Daniel D. G. Lee, Jin-Hyeok Choi, Jaeheon Jeong:
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time. 338-340 - Seungjae Lee
A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput. 340-342 - Jan Genoe
Session 21 overview: Extending silicon and its applications: Technology directions subcommittee. 342-343 - Komail M. H. Badami, Juan Carlos Pena Ramos, Steven Lauwereins, Marian Verhelst
Mixed-signal programmable non-linear interface for resource-efficient multi-sensor analytics. 344-346 - Minhao Yang, Chung-Heng Yeh, Yiyin Zhou
A 1μW voice activity detector using analog feature extraction and digital deep neural network. 346-348 - Bichoy Bahr, Yanbo He
32GHz resonant-fin transistors in 14nm FinFET technology. 348-350 - Yvain Thonnart
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks. 350-352 - Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara
A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. 352-354 - Anh Chu, Benedikt Schlecker, Klaus Lips, Maurits Ortmanns, Jens Anders
An 8-channel 13GHz ESR-on-a-Chip injection-locked vco-array achieving 200μM-concentration sensitivity. 354-356 - Kostas Doris, Jan Westra, Un-Ku Moon:
Session 22 overview: Gigahertz data converters: Data converter subcommittee. 356-357 - Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET. 358-360 - Chi-Hung Lin, Jackie Koon Lun Wong, Tae-Youn Kim, Guangxi Ray Xie, Donald Major, Greg Unruh, Sunny Raj Dommaraju, Hans Eberhart, Ardie G. Venes:
A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS. 360-362 - Shiyu Su, Mike Shuo-Wei Chen:
A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. 362-364 - Hyunchol Shin, Andrea Bevilacqua, Piet Wambacq:
Session 23 overview: LO generation: RF subcommittee. 364-365 - Heein Yoon, Juyeop Kim
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. 366-368 - Farshad Piri
A >40dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55nm CMOS. 368-370 - Jingzhi Zhang
A 22.8-to-43.2GHz tuning-less injection-locked frequency tripler using injection-current boosting with 76.4% locking range for multiband 5G applications. 370-372 - Chen Jiang, Mohammed Aseeri, Andreia Cathelin, Ehsan Afshari:
A 301.7-to-331.8GHz source with entirely on-chip feedback loop for frequency stabilization in 0.μm BiCMOS. 372-374 - Chee-Cheow Lim, Jun Yin
An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM. 374-376 - Fabio Padovan, Fabio Quadrelli
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations. 376-378 - Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang:
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. 378-380 - Yogesh K. Ramadass, Gerard Villar Pique, Axel Thomsen:
Session 24 overview: GaN drivers and converters: Power management subcommittee. 380-381 - Lin Cong, Hoi Lee:
A 2MHz 150-to-400V input isolated DC-DC bus converter with monolithic slope-sensing ZVS detection achieving 13ns turn-on delay and 1.6W power saving. 382-384 - Achim Seidel, Bernhard Wicht
A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors. 384-386 - Xugang Ke, Dongsheng Brian Ma:
A 3-to-40V VIN 10-to-50MHz 12W isolated GaN driver with self-excited tdead minimizer achieving 0.2ns/0.3ns tdead, 7.9% minimum duty ratio and 50V/ns CMTI. 386-388 - Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony:
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. 388-389 - Stanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Turkur Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang:
A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET. 390-392 - Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu:
A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS. 392-394 - Cheng-Ru Ho, Mike Shuo-Wei Chen:
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. 394-396 - Taeho Seong
A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC. 396-398 - Giuseppe Gramegna, Hua Wang, Piet Wambacq:
Session 26 overview: RF techniques for communication and sensing: RF subcommittee. 398-399 - Sanket Jain
A 0.55-to-0.9GHz 2.7dB NF full-duplex hybrid-coupler circulator with 56MHz 40dB TX SI suppression. 400-402 - Huy Thong Nguyen, Taiyun Chi, Sensen Li, Hua Wang
A 62-to-68GHz linear 6Gb/s 64QAM CMOS doherty radiator with 27.5%/20.1% PAE at peak/6dB-back-off output power leveraging high-efficiency multi-feed antenna-based active load modulation. 402-404 - Behrooz Abiri, Ali Hajimiri
A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLL. 404-406 - Sheikh Nijam Ali
A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays. 406-408 - Yun Yin, Liang Xiong, Yiting Zhu, Bowen Chen, Hao Min, Hongtao Xu:
A compact dual-band digital doherty power amplifier using parallel-combining transformer for cellular NB-IoT applications. 408-410 - Tso-Wei Li, Ming-Yu Huang, Hua Wang
A continuous-mode harmonically tuned 19-to-29.5GHz ultra-linear PA supporting 18Gb/s at 18.4% modulation PAE and 43.5% peak PAE. 410-412 - Marco Vigilante, Patrick Reynaert:
A coupled-RTWO-based subharmonic receiver front-end for 5G E-Band backhaul links in 28nm bulk CMOS. 412-414 - Lorenzo Lotti, Greg LaCaille, Ali M. Niknejad
A 12mW 70-to-100GHz mixer-first receiver front-end for mm-wave massive-MIMO arrays in 28nm CMOS. 414-416 - Pingyue Song, Hossein Hashemi
A 13th-order CMOS reconfigurable RF BPF with adjustable transmission zeros for SAW-less SDR receivers. 416-418 - Philipp Hillger, Ritesh Jain
A 128-pixel 0.56THz sensing array for real-time near-field imaging in 0.13μm SiGe BiCMOS. 418-420 - Makoto Takamiya, Yen Hsun Hsu, Axel Thomsen:
Session 27 overview: Power-converter techniques: Power management subcommittee. 420-421 - Yang Jiang
A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2. 422-424 - Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo:
A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle. 424-426 - Arunkumar Salimath, Edoardo Bonizzoni, Edoardo Botti, Giovanni Gonano, Paolo Cacciagrano, Davide Luigi Brambilla, Tommaso Barbieri, Franco Maloberti:
An 86% efficiency SIMO DC-DC converter with one boost, one buck, and a floating output voltage for car-radio. 426-428 - Min-Woo Ko, Kiduk Kim, Young-Jin Woo, Se-Un Shin, Hyun-Ki Han, Yeunhee Huh, Gyeong-Gu Kang, Jeong-Hyun Cho, Sang-Jin Lim, Se-Hong Park
A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management. 428-430 - Se-Un Shin, Yeunhee Huh, Yong-Min Ju, Sung-Won Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park
A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple. 430-432 - Chen-Yen Ho, Shih-Mei Lin, Che-Hao Meng, Hao-Ping Hong, Sheng-Hong Yan, Ting-Hsun Kuo, Chia-Sheng Peng, Chieh-Hsun Hsiao, Hsin-Hung Chen, Da-Wei Sung, Chien-Wei Kuan:
An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOS. 432-434 - Takahiro Nomiyama, Yong-Sik Youn, Young-Hwan Choo, Dong-Su Kim, Jae-Yeol Han, Jun-Hee Jung, Jongbeom Baek, Sung-Jun Lee, Euiyoung Park, Jeong-Hyun Choi, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
A 2TX supply modulator for envelope-tracking power amplifier supporting intra- and inter-band uplink carrier aggregation and power class-2 high-power user equipment. 434-436 - Wei-Chung Chen, Tzu-Chi Huang, Chao-Chang Chiu, Chih-Wei Chang, Kuo-Chun Hsu:
94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone. 436-438 - Moataz Abdelfattah, Muhammad Swilam, Brian Dupaix, Dale Shane Smith, Ayman A. Fayed
An on-chip resonant-gate-drive switched-capacitor converter for near-threshold computing achieving 70.2% efficiency at 0.92A/mm2 current density and 0.4V output. 438-440 - Howard C. Luong, Kyoo Hyun Lim, Stefano Pellerano:
Session 28 overview: Wireless connectivity: Wireless subcommittee. 440-441 - Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka
An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. 442-444 - Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. 444-446 - Ming Ding, Xiaoyan Wang, Peng Zhang, Yuming He, Stefano Traferro, Kenichi Shibata, Minyoung Song
A 0.8V 0.8mm2 bluetooth 5/BLE digital-intensive transceiver with a 2.3mW phase-tracking RX utilizing a hybrid loop filter for interference resilience in 40nm CMOS. 446-448 - Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. 448-450 - Jun Yin
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. 450-452 - Jesse Moody, Pouyan Bassirian
A -76dBm 7.4nW wakeup radio with automatic offset compensation. 452-454 - Angad Singh Rekhi
A 14.5mm2 8nW -59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applications. 454-456 - Bo Zhao, Nai-Chung Kuo, Benyuanyi Liu, Yi-An Li, Lorenzo Lotti, Ali M. Niknejad:
A 5.8GHz power-harvesting 116μmx116μm "dielet" near-field radio with on-chip coil antenna. 456-458 - Pedram Mohseni, Nick Van Helleputte, Makoto Ikeda:
Session 29 overview: Advanced biomedical systems: IMMD subcommittee. 458-459 - Scott Stanslaski, Jeffrey Herron, Elizabeth Fehrmann, Rob Corey, Heather Orser, Enrico Opri, Václav Kremen
Creating neural "co-processors" to explore treatments for neurological disorders. 460-462 - Daniel DeDorigo
A fully immersible deep-brain neural probe with modular architecture and a delta-sigma ADC integrated under each electrode for parallel readout of 144 recording sites. 462-464 - Carolina Mora Lopez
A 16384-electrode 1024-channel multimodal CMOS MEA for high-throughput intracellular action potential measurements and impedance spectroscopy in drug-screening applications. 464-466 - Gabriel Gagnon-Turcotte, Christian Ethier, Yves De Koninck, Benoit Gosselin
A 13μm CMOS SoC for simultaneous multichannel optogenetics and electrophysiological brain recording. 466-468 - Yaoyao Jia, S. Abdollah Mirbozorgi, Byunghun Lee, Wasif Khan, Fatma Madi, Arthur J. Weber, Wen Li, Maysam Ghovanloo:
A mm-sized free-floating wirelessly powered implantable optical stimulating system-on-a-chip. 468-470 - Chul Kim, Siddharth Joshi, Hristos Courellis, Jun Wang
A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging. 470-472 - Sehwan Lee, Arup K. George
A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS. 472-474 - Do-Hun Jang, SeongHwan Cho:
A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop. 474-476 - Shinichiro Shiratake, Edoardo Charbon, Leland Chang, Makoto Nagata:
Session 30 overview: Emerging memories: Memory and technology directions subcommittees. 476-477 - Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng, Chih-Feng Li, Chih-Yang Chang, Wei-Chi Chen, Yu-Der Chih, Tsung-Yung Jonathan Chang:
An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance. 478-480 - Qing Dong, Zhehong Wang, Jongyup Lim
A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. 480-482 - Tzu-Hsien Yang, Kai-Xiang Li, Yen-Ning Chiang, Wei-Yu Lin, Huan-Ting Lin, Meng-Fan Chang:
A 28nm 32Kb embedded 2T2MTJ STT-MRAM macro with 1.3ns read-access time for fast and reliable read applications. 482-484 - Shuhei Maeda, Satoru Ohshita, Kazuma Furutani, Yuto Yakubo, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda, Masahiro Fujita, Shunpei Yamazaki:
A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors. 484-486 - Naveen Verma, Fatih Hamzaoglu, Makoto Nagata, Leland Chang:
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. 486-487 - Avishek Biswas, Anantha P. Chandrakasan:
Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. 488-490 - Sujan Kumar Gonugondla
A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training. 490-492 - Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study. 492-494 - Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. 494-496 - Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. 496-498 - Xiang Gao:
Tutorials: Low-Jitter PLLs for wireless transceivers. 499-501 - Vivek De, Dennis Sylvester, James Myers, Jun Deguchi, Shinichiro Shiratake, Ingrid Verbauwhede
F1: Intelligent energy-efficient systems at the edge of IoT. 502-504 - Venkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee:
F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective. 505-507 - Brian P. Ginsburg:
F3: Circuits and architectures for wireless sensing, radar and imaging. 508-510 - Pierre Busson, Howard C. Luong, Chih-Ming Hung, Harish Krishnaswamy, Theodore Georgantas, Patrick P. Mercier:
F4: Circuit and system techniques for mm-wave multi-antenna systems. 511-513 - Bo Zhang, Frederic Gianesello, Simone Erba, Mounir Meghelli, Azita Emami, Takayuki Shibasaki:
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. 514-516 - Axel Thomsen, Bernhard Wicht, Pieter Harpe, Man Kay Law, Young Cheol Chae:
F6: Advances in energy efficient analog design. 517-519 - Vivienne Sze, Alison J. Burdett, Sonia Leon, Rikky Muller, Farhana Sheikh, Yildiz Sinangil, Trudy Stetzler, Ingrid Verbauwhede
EE2: Workshop on circuits for social good. 523-525 - Alison J. Burdett, Eugenio Cantatore, Kush Gulati, Yan Li:
EE3: Industry showcase. 525-527 - Kostas Doris, Stefano Stanzione, Paul Ferguson:
EE4: Figures-of-merit on trial. 527-529 - Phillip J. Restle, Kostas Doris, Vivek De, Paul Ferguson:
EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!). 529-531 - Jaeha Kim, Ki-Tae Park:
EE6: Can artificial intelligence replace my job? The dawn of a new IC industry with AI. 531-533 - Daniel J. Friedman:
SC: Hardware approaches to machine learning and inference. 533-534
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