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IEEE Journal of Solid-State Circuits, Volume 56
Volume 56, Number 1, January 2021
- Friedel Gerfers
, Ping-Hsuan Hsieh
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). 3-6 - Jay Im
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. 7-18 - Hao Li
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control. 19-29 - Eric Groen
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture. 30-42 - Somnath Kundu
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS. 43-54 - Tianyu Jia
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. 55-65 - Jong-Hyeok Yoon
NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. 66-78 - Pascal Vivet
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. 79-97 - David Wolpert
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. 98-111 - Chieh Chung, Chia-Hsiang Yang
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots. 112-122 - Yi-Chung Wu
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. 123-135 - Debayan Das
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. 136-150 - Weiwei Shan
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. 151-164 - Kasho Yamamoto
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. 165-178 - Tsung-Yung Jonathan Chang, Yen-Huei Chen
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. 179-187 - Mahmut E. Sinangil
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. 188-198 - Ki Chul Chun
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. 199-211 - Chang-Kyo Lee
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. 212-224 - Toshiyuki Kouchi
A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs. 225-234 - Guoxiang Han
A Multi-Branch Receiver With Modulated Mixer Clocks for Concurrent Dual-Carrier Reception and Rapid Compressive-Sampling Spectrum Scanning. 235-253 - Ming Ding
A Bluetooth 5 Transceiver With a Phase-Tracking RX and Its Corresponding Digital Baseband in 40-nm CMOS. 254-266 - Keng Chen, Luca Petruzzi, Ronald Hulfachor, Marvin Onabajo
A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers. 267-276 - Sanfeng Zhang
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming. 277-286 - Hui Liu
A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS. 287-297 - Seyeon Yoo
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. 298-309 - Bahaa Radi
A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End. 310-323 - Eric J. Carlson, Kai Strunz, Brian P. Otis:
Erratum to "A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting". 324
Volume 56, Number 2, February 2021
- Xiang Yi
A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture. 327-339 - Muhammad Ibrahim Wasiq Khan
CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication. 340-354 - Qian Zhong
Terahertz Even-Order Subharmonic Mixer Using Symmetric MOS Varactors. 355-366 - Gholamreza Nikandish
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement. 367-381 - Umut Çelik
Robust, Efficient Distributed Power Amplifier Achieving 96 Gbit/s With 10 dBm Average Output Power and 3.7% PAE in 22-nm FD-SOI. 382-391 - Kaituo Yang
A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5-6-GHz WLAN Carrier Aggregation. 392-403 - Amir Bozorg
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse. 404-415 - Po-Han Peter Wang
An Interference-Resilient BLE-Compatible Wake-Up Receiver Employing Single-Die Multi-Channel FBAR-Based Filtering and a 4-D Wake-Up Signature. 416-426 - Suoping Hu
A Type-II Phase-Tracking Receiver. 427-439 - Nilan Udayanga
A Radio Frequency Analog Computer for Computational Electromagnetics. 440-454 - Il-Min Yi
A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation. 455-464 - Il-Min Yi
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS. 465-475 - Abhishek Mukherjee
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. 476-487 - Jong-Seok Kim
A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays. 488-500 - Sining Pan
A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA. 501-510 - Feng Chen
A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS. 511-520 - Xugang Ke, Dong Yan
A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and VSW Dual-Edge Dead-Time Modulation Techniques. 521-530 - Yingping Chen
A 10-MHz Closed-Loop EMI-Regulated GaN Switching Power Converter Using Emulated Miller Plateau Tracking and Adaptive Strength Gate Driving. 531-540 - Junyoung Maeng
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications. 541-553 - Hanwool Jeong, Tae Hyun Kim
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. 554-565 - Cheng Wang
A Terahertz Molecular Clock on CMOS Using High-Harmonic-Order Interrogation of Rotational Transition for Medium-/Long-Term Stability Enhancement. 566-580 - Hyunsu Park, Junyoung Song
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. 581-590 - Nahmil Koo
A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS. 591-600 - Benoît Labbé
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller. 601-611 - Yaoyu Tao
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. 612-623 - Zhengyu Chen
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. 624-635 - Jie-Fang Zhang
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. 636-647 - Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee:
A 354F2 Leakage-Based Physically Unclonable Function With Lossless Stabilization Through Remapping for Low-Cost IoT Security. 648-657 - Fengbin Tu
Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. 658-673
Volume 56, Number 3, March 2021
- Qun Jane Gu
Guest Editorial 2020 Custom Integrated Circuits Conference. 679-680 - Shenggang Dong
A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver. 681-693 - Dongyi Liao
A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation. 694-704 - Amr Ahmed
A 43-97-GHz Mixer-First Front-End With Quadrature Input Matching and On-Chip Image Rejection. 705-714 - Arian Hashemi Talkhooncheh
A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT. 715-728 - Alok Baluni
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback. 729-738 - Chen-Kai Hsu
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. 739-749 - Kuan-Chang Xavier Chen
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS. 750-762 - Ping-Hung Yin, Chih-Wen Lu
A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs. 763-777 - Marco Croce
A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment. 778-787 - Shovan Maity
Sub-μWRComm: 415-nW 1-10-kb/s Physically and Mathematically Secure Electro-Quasi-Static HBC Node for Authentication and Medical Applications. 788-802 - Minkyu Kim
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. 803-813 - Vijay Kiran Kalyanam
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor. 814-823 - Zhehong Wang
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. 824-833 - Peter Lawrence Brown
A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network. 834-843 - Taehoon Jeong
S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance. 844-854 - Chen Chen
A 2-MHz 9-45-V Input High-Efficiency Three-Switch ZVS Step-Up/-Down Hybrid Converter. 855-865 - Yanqiao Li
An Optically Powered, High-Voltage, Switched- Capacitor Drive Circuit for Microrobotics. 866-875 - Yijie Wei
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier. 876-886 - Jaehyuk Lee
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection. 887-898 - Maciej Kucharski
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation. 899-913 - Alireza Asoodeh
A Highly Linear and Efficient 28-GHz PA With a Psat of 23.2 dBm, P1 dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS. 914-927 - Shi Bu
Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends. 928-939 - Hayun Chung
A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS. 940-949 - Zhaoyang Yin
Low Bit-Depth ADCs for Multi-bit Quanta Image Sensors. 950-960 - Hyunjin Kim
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode. 961-971 - Abishek Manian
A Simultaneous Bidirectional Single-Ended Coaxial Link With 24-Gb/s Forward and 312.5-Mb/s Back Channels. 972-987 - Keji Zhou
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. 988-1000 - Mohamed I. Ibrahim
High-Scalability CMOS Quantum Magnetometer With Spin-State Excitation and Detection of Diamond Color Centers. 1001-1014
Volume 56, Number 4, April 2021
- Brian P. Ginsburg
Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits. 1019-1021 - Hyeongseok Seo
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter. 1022-1035 - Matheus F. Pimenta
A 200-μW Interface for High-Resolution Eddy-Current Displacement Sensors. 1036-1045 - Jiannan Huang
A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation. 1046-1057 - Rishika Agarwala
A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. 1058-1070 - Hyochan An
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks. 1071-1081 - Phil C. Knag
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. 1082-1092 - Ji-Hoon Kim
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. 1093-1104 - Ziyun Li
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. 1105-1115 - Masanori Natsui
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. 1116-1128 - Dae-Hoon Na
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. 1129-1140 - Raghavan Kumar
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. 1141-1151 - Christopher L. Ayala
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices. 1152-1165 - Vijay Kiran Kalyanam
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor. 1166-1175 - Huajun Zhang
A High-Linearity and Low-EMI Multilevel Class-D Amplifier. 1176-1185 - Dong Yan
An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques. 1186-1196 - Jun-Ho Boo
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. 1197-1206 - Efraïm Eland
A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW. 1207-1215 - Dong-Ryeol Oh
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. 1216-1226 - Benjamin P. Hershberg
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. 1227-1240 - Daniel S. Truesdell
A 0.5-V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator With 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop. 1241-1253 - Lianbo Wu
A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain. 1254-1264 - Haidang Lin, Charlie Boecker, Masum Hossain
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET. 1265-1277 - Yong-Un Jeong
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. 1278-1287 - Po-Han Peter Wang
A Dual-Mode Wi-Fi/BLE Wake-Up Receiver. 1288-1298 - Ali Nikoofard
A 0.6-mW 16-FSK Receiver Achieving a Sensitivity of -103 dBm at 100 kb/s. 1299-1309 - Jian Pang
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. 1310-1326
Volume 56, Number 5, May 2021
- Mohyee Mikhemar:
Guest Editorial Introduction to the Special Section on the 2020 RFIC Symposium. 1331 - Tomoyuki Arai
A 77-GHz 8RX3TX Transceiver for 250-m Long-Range Automotive Radar in 40-nm CMOS Technology. 1332-1344 - Masato Kohtani
76- to 81-GHz CMOS Built-In Self-Test With 72-dB C/N and Less Than 1 ppm Frequency Tolerance for Multi-Channel Radar Applications. 1345-1359 - Sohail Ahasan
Frequency-Domain-Multiplexing Single-Wire Interface and Harmonic-Rejection-Based IF Data De-Multiplexing in Millimeter-Wave MIMO Arrays. 1360-1373 - Rundao Lu
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver. 1374-1386 - Xiang Yi
Realization of In-Band Full-Duplex Operation at 300 and 4.2 K Using Bilateral Single-Sideband Frequency Conversion. 1387-1397 - Aravind Nagulu
A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay-Bandwidth Limit. 1398-1411 - Aravind Nagulu
Ultra-Wideband Switched-Capacitor Delays and Circulators - Theory and Implementation. 1412-1424 - Negar Reiskarimian
Inductorless, Widely Tunable N-Path Shekel Circulators Based on Harmonic Engineering. 1425-1437 - Hyungjoo Seo
A Passive-Mixer-First Acoustic-Filtering Superheterodyne RF Front-End. 1438-1453 - Pingyue Song
mm-Wave Mixer-First Receiver With Selective Passive Wideband Low-Pass Filtering. 1454-1463 - Milad Frounchi
Millimeter-Wave SiGe Radiometer Front End With Transformer-Based Dicke Switch and On-Chip Calibration Noise Source. 1464-1474 - Omar El-Aassar
Octave-Tuning Dual-Core Folded VCO Leveraging a Triple-Mode Switch-Less Tertiary Magnetic Loop. 1475-1486 - Huizhen Jenny Qian
A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement. 1487-1501 - Kun-Da Chu, Steven Callender, Yanjie Wang
A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm Psat and 26.5% PAE in 16-nm FinFET CMOS. 1502-1513 - Muhammad Waleed Mansha
A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI. 1514-1526 - Sajad Golabighezelahmad
A 0.7-5.7 GHz Reconfigurable MIMO Receiver Architecture for Analog Spatial Notch Filtering Using Orthogonal Beamforming. 1527-1540 - Saba Zargham
A 2.4-GHz 1.3-mW OQPSK RF Front-End TX Based on an Injection-Locked Power Amplifier. 1541-1552 - Lang Chen, Hang Liu
A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off. 1553-1564 - Mohammad Reza Pazhouhandeh
Opamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance. 1565-1575 - Zhe Hua
A 1.2-A Dual-Output SC DC-DC Regulator With Continuous Gate-Drive Modulation Achieving ≤0.01-mV/mA Cross Regulation. 1576-1587 - Tzu-Hsiang Hsu
A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. 1588-1596 - Kwanseo Park
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. 1597-1607 - Kuan-Chun Chen
A Tri-Mode Compressed Analytics Engine for Low-Power AF Detection With On-Demand EKG Reconstruction. 1608-1617 - Longyang Lin
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes. 1618-1629 - Donghyeon Han
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning. 1630-1640 - Bohan Lin
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source. 1641-1650
Volume 56, Number 6, June 2021
- Milad Kalantari
A W-Band Single-Antenna FMCW Radar Transceiver With Adaptive Leakage Cancellation. 1655-1667 - Fei Wang
A High-Power Broadband Multi-Primary DAT-Based Doherty Power Amplifier for mm-Wave 5G Applications. 1668-1681 - Huan Wang
An LO Leakage Suppression Technique for Blocker-Tolerant Wideband Receivers With High-Q Selectivity at RF Input. 1682-1696 - Tae Hwan Jang
120-GHz Wideband I/Q Receiver Based on Baseband Equalizing Technique. 1697-1710 - Yiyang Shu
A 2-D Mode-Switching Quad-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting. 1711-1721 - Wei Tang
A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. 1722-1731 - Sensen Li
A MM-Wave Current-Mode Inverse Outphasing Transmitter Front-End: A Circuit Duality of Conventional Voltage-Mode Outphasing. 1732-1744 - Mohamed Atef Shehata
A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator. 1745-1760 - Moon Hyung Jang
A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC. 1761-1771 - Yan Song
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC. 1772-1783 - Erfan Ghaderi
A Four-Element 500-MHz 40-mW 6-bit ADC-Enabled Time-Domain Spatial Signal Processor. 1784-1794 - Cheng-Ze Shao
A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes. 1795-1804 - Nghia Tang
Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm2 Peak Current Density and 78% Peak Power Efficiency. 1805-1815 - Pengcheng Xu
A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform. 1816-1826 - Sandip Uprety
A 0.65-mW-to-1-W Photovoltaic Energy Harvester With Irradiance-Aware Auto-Configurable Hybrid MPPT Achieving >95% MPPT Efficiency and 2.9-ms FOCV Transient Time. 1827-1836 - Soumya Bose
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting. 1837-1848 - Keun-Mok Kim
A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection Crystal Oscillator. 1849-1858 - Giuseppe Sciortino
Four-Channel Differential Lock-in Amplifiers With Autobalancing Network for Stimulated Raman Spectroscopy. 1859-1870 - Zhao Zhang
A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps. 1871-1885 - Hyunsu Park, Jincheol Sim, Yoonjae Choi
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. 1886-1896 - Navid Hosseinzadeh
A Distributed Low-Noise Amplifier for Broadband Linearization of a Silicon Photonic Mach-Zehnder Modulator. 1897-1909 - Jihee Lee, Kyoung-Rog Lee
A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System. 1910-1923 - Zhiyu Chen
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference. 1924-1935 - Jinshan Yue
STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration. 1936-1948 - Qing Li
Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates. 1949-1958
Volume 56, Number 7, July 2021
- Xing Chen
A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets. 1963-1974 - Akshay Visweswaran
A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization. 1975-1993 - Anoop Narayan Bhat
A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications. 1994-2006 - Bart J. Thijssen
2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter. 2007-2017 - Shiyu Su
A Time-Approximation Filter for Direct RF Transmitter. 2018-2028 - Shih-Chang Hung
A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier. 2029-2039 - Yatao Peng
A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications. 2040-2053 - Fu-Bin Yang
Structure-Reconfigurable Power Amplifier (SR-PA) and 0X/1X Regulating Rectifier for Adaptive Power Control in Wireless Power Transfer System. 2054-2064 - Yuxuan Luo
A 70-μW 1.35-mm2 Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver. 2065-2076 - Ali Hajimiri
Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond. 2077-2101 - Mo Huang
A Hybrid Boost Converter With Cross-Connected Flying Capacitors. 2102-2112 - Kang Wei
A 10-MHz DAB Hysteretic Control Switching Power Converter for 5G IoT Power Delivery. 2113-2122 - Pen-Jui Peng
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS. 2123-2131 - Hyeon-June Kim
11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors. 2132-2141 - Aria Samiei
A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers. 2142-2157 - William Lemaire
Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link. 2158-2170 - Xiahan Zhou
A 9.7-nTᵣₘₛ, 704-ms Magnetic Biosensor Front-End for Detecting Magneto-Relaxation. 2171-2181 - Sachin Taneja
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. 2182-2192 - Kunyang Liu
A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement. 2193-2204 - Aseem Sayal
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing. 2205-2220 - Hyunjoon Kim
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks. 2221-2233 - Hassan Dbouk
A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting. 2234-2244 - Sungju Ryu
Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations. 2245-2255 - David Bol
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. 2256-2269 - Chuxiong Lin
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. 2270-2280 - Luke R. Everson
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. 2281-2290
Volume 56, Number 8, August 2021
- Robin Garg
A 28-GHz Beam-Space MIMO RX With Spatial Filtering and Frequency-Division Multiplexing-Based Single-Wire IF Interface. 2295-2307 - Fei Wang
A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design. 2308-2323 - Xiaolong Liu
A 59-to-276-GHz CMOS Signal Generator Using Varactor-Less VCO and Dual-Mode ILFD. 2324-2334 - Pietro Caragiulo
A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm2 Switched-Capacitor DAC in 16-nm FinFET CMOS. 2335-2346 - Eric Swindlehurst
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. 2347-2359 - Benjamin P. Hershberg
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. 2360-2374 - Dongyang Jiang
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. 2375-2387 - Woojin Hong
A 10-MHz Current-Mode AOT Boost Converter With Dual-Ramp Modulation Scheme and Translinear Loop-Based Current Sensor for WiFi IoT Applications. 2388-2401 - Xiaosen Liu
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning. 2402-2415 - Kang Wei
Direct 12V/24V-to-1V Tri-State Double Step-Down Power Converter With Online VCF Rebalancing and In-Situ Precharge Rate Regulation. 2416-2426 - Joeri Lechevallier
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging. 2427-2437 - Doohwan Jung
A CMOS 21 952-Pixel Multi-Modal Cell-Based Biosensor With Four-Point Impedance Sensing for Holistic Cellular Characterization. 2438-2451 - Anh Tuan Nguyen
Redundant Crossfire: A Technique to Achieve Super-Resolution in Neurostimulator Design by Exploiting Transistor Mismatch. 2452-2465 - Xinyue Yuan
Extracellular Recording of Entire Neural Networks Using a Dual-Mode Microelectrode Array With 19 584 Electrodes and High SNR. 2466-2475 - Stefan Reich
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip. 2476-2487 - Ivan Peric
High-Voltage CMOS Active Pixel Sensor. 2488-2502 - Chanmin Park
A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing. 2503-2515 - Tzu-Hsiang Hsu
A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. 2516-2524 - Min-Seong Choo
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. 2525-2538 - Hannes Ramon
A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS. 2539-2549 - Zhiting Lin
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. 2550-2562 - Hyeongjun Ko
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. 2563-2573 - Kyeongho Lee, Woong Choi
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. 2574-2584 - Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu:
Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters. 2585-2601
Volume 56, Number 9, September 2021
- Pavan Kumar Hanumolu:
New Associate Editors. 2607-2608 - Shahriar Shahramian
Guest Editorial Introduction to the Special Section on the 2020 IEEE BCICTS Conference. 2609-2610 - Philipp Thomas
1-to-4 Analog Demultiplexer With up to 128 GS/s for Interleaving of Bandwidth-Limited Digitizers in Wireline and Optical Receivers. 2611-2623 - Michael Collisi
Resolution-Related Design Considerations for a 120-GS/s 8-bit 2: 1 Analog Multiplexer in SiGe-BiCMOS Technology. 2624-2634 - Takaaki Yoshioka
Ku-Band 70-/30-W-Class Internally Matched GaN Power Amplifiers With Low IMD3 Over a Wide Offset Frequency Range of Up To 400 MHz. 2635-2646 - Fabian Thome
First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth. 2647-2655 - Keun-Mok Kim
A -123-dBm Sensitivity Split-Channel BFSK Reconfigurable Data/Wake-Up Receiver for Low-Power Wide-Area Networks. 2656-2667 - Cheonhoo Jeon
A 2.5-nW Radio Platform With an Internal Wake-Up Receiver for Smart Contact Lens Using a Single Loop Antenna. 2668-2679 - Haoyu Zhuang
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC. 2680-2690 - Dong-Jin Chang
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration. 2691-2700 - Ka-Meng Lei
A 0.35-V 5, 200-μm2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator. 2701-2710 - Eslam Helal
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL. 2711-2723 - Hyunjin Kim
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme. 2724-2735 - Qin Kuai
A Dual-Frequency Thermal Energy Harvesting Interface With Real-Time-Calculation ZCD. 2736-2747 - Yingyi Yan
A Scalable Multiphase Current-Mode Buck Controller With Sub-Milliohm DCR Current Sensing and Synchronized Overcurrent Protection. 2748-2759 - Fangyu Mao
A Hybrid Single-Inductor Bipolar-Output DC-DC Converter With Floating Negative Output for AMOLED Displays. 2760-2769 - Jie Lin
A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation. 2770-2780 - Sung Justin Kim
0.5-1-V, 90-400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation. 2781-2794 - Mostafa Gamal Ahmed
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. 2795-2803 - Zhixuan Wang
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. 2804-2816 - Xin Si
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. 2817-2831 - Zhiting Lin
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. 2832-2844 - Sanghoon Kang
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation. 2845-2857 - Donghyeon Han
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching. 2858-2869 - Ibrahim Ahmed
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. 2870-2880 - Jifu Liang
An Offset-Cancelling Discrete-Time Analog Computer for Solving 1-D Wave Equations. 2881-2894 - Fengbin Tu
Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". 2895 - Alireza Asoodeh
Corrections to "A Highly Linear and Efficient 28-GHz PA With a Pₛₐₜ of 23.2 dBm, P₁ dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS". 2896
Volume 56, Number 10, October 2021
- Pavan Kumar Hanumolu:
New Associate Editor. 2899 - Robert Chen-Hao Chang
Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC). 2900-2901 - Myungjun Kim
A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole. 2902-2912 - Joanne Si Ying Tan
A Fully Energy-Autonomous Temperature-to-Time Converter Powered by a Triboelectric Energy Harvester for Biomedical Applications. 2913-2923 - Jianming Zhao
A 310-nA Quiescent Current 3-fs-FoM Fully Integrated Capacitorless Time-Domain LDO With Event-Driven Charge Pump and Feedforward Transient Enhancement. 2924-2933 - Hao-Chung Cheng, Po-Han Chen, Yu-Tong Su, Po-Hung Chen:
A Reconfigurable Capacitive Power Converter With Capacitance Redistribution for Indoor Light-Powered Batteryless Internet-of-Things Devices. 2934-2942 - Mitsuya Fukazawa
A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction. 2943-2955 - Byungchoul Park
A 64 × 64 SPAD-Based Indirect Time-of-Flight Image Sensor With 2-Tap Analog Pulse Counters. 2956-2967 - Soyeon Kim
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization. 2968-2980 - Saurabh Jain
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing. 2981-2992 - Ji-Hwan Seol
Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur. 2993-3007 - Nimrod Ginzberg
A 65 nm CMOS Quadrature Balanced Switched-Capacitor Power Amplifier for Full- and Half-Duplex Wireless Operation. 3008-3020 - Jianxun Yang
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. 3021-3038 - Gicheol Shin, Eunyoung Lee, Jongmin Lee, Yongmin Lee, Yoonmyung Lee:
An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination. 3039-3048 - Sachin Taneja
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core. 3049-3061 - Sung-Hao Wang
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. 3062-3076 - Peigen Zhou
A -28.5-dB EVM 64-QAM 45-GHz Transceiver for IEEE 802.11aj. 3077-3093 - Ahmed Hamza
A Full-Duplex Rake Receiver Using RF Code-Domain Signal Processing for Multipath Environments. 3094-3108 - Mannem Naga Sasikanth
Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture. 3109-3122 - Minhao Yang
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction. 3123-3133 - Luigi Fassio, Longyang Lin
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. 3134-3144 - Hung-Yi Huang
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone. 3145-3156 - Douwe van Willigen
A Transceiver ASIC for a Single-Cable 64-Element Intra-Vascular Ultrasound Probe. 3157-3166 - Ya-Ting Hsu, Zong-Yi Lin, Jia-Jyun Lee
An Envelope Tracking Supply Modulator Utilizing a GaN-Based Integrated Four-Phase Switching Converter and Average Power Tracking-Based Switch Sizing With 85.7% Efficiency for 5G NR Power Amplifier. 3167-3176 - Hamed Rahmani
A Wirelessly Powered Reconfigurable FDD Radio With On-Chip Antennas for Multi-Site Neural Interfaces. 3177-3190 - Enrique Alvarez-Fontecilla
Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs. 3191-3201 - Zhi Hu
Erratum to "High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure". 3202 - Stefan Reich
Erratum to "A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System-on-Chip". 3203 - Rundao Lu
Erratum to "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver". 3204
Volume 56, Number 11, November 2021
- Vyshnavi Suntharalingam, Sudip Shekhar
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). 3207-3208 - Min-Sun Keel
A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation. 3209-3219 - Jun Ogi
A 124-dB Dynamic-Range SPAD Photon-Counting Image Sensor Using Subframe Sampling and Extrapolating Photon Count. 3220-3227 - Chihiro Okada
A 50.1-Mpixel 14-Bit 250-frames/s Back-Illuminated Stacked CMOS Image Sensor With Column-Parallel kT/C-Canceling S&H and ΔΣADC. 3228-3235 - Jiannan Huang
A 178.9-dB FoM 128-dB SFDR VCO-Based AFE for ExG Readouts With a Calibration-Free Differential Pulse Code Modulation Technique. 3236-3246 - Maged ElAnsary
Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission. 3247-3262 - Abraham Akinin
An Optically Addressed Nanowire-Based Retinal Prosthesis With Wireless Stimulation Waveform Control and Charge Telemetering. 3263-3273 - Zhixuan Wang
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. 3274-3288 - Jongseok Park
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits. 3289-3306 - Yi-Pei Su
A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications. 3307-3317 - Hadi Bameri
A 200-GHz Power Amplifier With a Wideband Balanced Slot Power Combiner and 9.4-dBm P sat in 65-nm CMOS: Embedded Power Amplification. 3318-3330 - Huizhen Jenny Qian
A 4-Element Digital Modulated Polar Phased-Array Transmitter With Phase Modulation Phase-Shifting. 3331-3347 - Zhixian Deng
A 22.9-38.2-GHz Dual-Path Noise-Canceling LNA With 2.65-4.62-dB NF in 28-nm CMOS. 3348-3359 - Dawei Ye
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. 3360-3374 - Sashank Krishnamurthy
Design of High-Linearity Mixer-First Receivers for mm-Wave Digital MIMO Arrays. 3375-3387 - Dae-Woong Park
Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-Gmax Gain Boosting Technique. 3388-3398 - Gabriel Guimarães
A 670-GHz 4 × 2 Oscillator-Radiator Array Achieving 7.4-dBm EIRP in 40-nm CMOS. 3399-3411 - Jiaxin Liu
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. 3412-3423 - Sein Oh
An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure. 3424-3433 - Alexander S. Delke
A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C. 3434-3444 - Jianglin Du
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. 3445-3457 - Hanyang Su
A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp. 3458-3469 - Tae-Gyun Song
A 50.7-dB-DR Finger-Resistance Extracting Multi-Touch Sensor IC for Soft Classification of Fingers Contacted on 6.7-in Capacitive Touch Screen Panel. 3470-3485 - Jae-Sung An
A Readout IC for Capacitive Touch Screen Panels With 33.9 dB Charge-Overflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation. 3486-3498 - Nilanjan Pal
A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications. 3499-3510 - Christoph Rindfleisch
A Resonant One-Step 325 V to 3.3-10 V DC-DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques. 3511-3520 - Chang Yang
Design and Characterization of a 10-MHz GaN Gate Driver Using On-Chip Feed-Forward Gaussian Switching Regulation for EMI Reduction. 3521-3532 - Viveka Konandur Rajanna
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications. 3533-3543
Volume 56, Number 12, December 2021
- Yun Chiu
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). 3547-3550 - Sining Pan
A Self-Calibrated Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor. 3551-3559 - Heyi Li
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. 3560-3572 - Atsushi Matamura
An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With -93-dB THD+N, 113-dB SNR, and 93% Efficiency. 3573-3582 - Thije Rooijers
A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers. 3583-3592 - Seok-Tae Koh
A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique. 3593-3607 - Mojtaba Ashourloo
An Automotive-Grade Monolithic Masterless Fault-Tolerant Hybrid Dickson DC-DC Converter for 48-V Multi-Phase Applications. 3608-3618 - Yu-Yung Kao, Sheng-Hsi Hung, Hsuan-Yu Chen, Jia-Jyun Lee
Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch With Temperature-Compensated Fast Turn-on Technique for Achieving Switching Frequency of 50 MHz and Slew Rate of 118.3 V/Ns. 3619-3627 - Haixiao Cao
A 12-Level Series-Capacitor 48-1V DC-DC Converter With On-Chip Switch and GaN Hybrid Power Conversion. 3628-3638 - Alessandro Novello
A 1.25-GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators. 3639-3654 - Daniel Gruber
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. 3655-3667 - Tzu-Han Wang
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation. 3668-3680 - Lu Jie
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. 3681-3693 - Valdrin Qunaj
A Ka-Band Doherty-Like LMBA for High-Speed Wireless Communication in 28-nm CMOS. 3694-3703 - Yang Zhang
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS. 3704-3714 - Bingzheng Yang
Quadrature Switched/Floated Capacitor Power Amplifier With Reconfigurable Self-Coupling Canceling Transformer for Deep Back-Off Efficiency Enhancement. 3715-3727 - Yiyang Shu
A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique. 3728-3740 - Junjun Qiu
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. 3741-3755 - Wanghua Wu
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. 3756-3767 - Mohammadreza Beikmirza
A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter. 3768-3783 - Masoud Pashaeifar
A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications. 3784-3798 - Gaurav Singh
An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-nm CMOS. 3799-3810 - Emily Naviasky
A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO. 3811-3826 - Dragan Simic
A 420-GHz Sub-5-μm Range Resolution TX-RX Phase Imaging System in 40-nm CMOS Technology. 3827-3839 - Hooman Saeidi
THz Prism: One-Shot Simultaneous Localization of Multiple Wireless Nodes With Leaky-Wave THz Antennas and Transceivers in CMOS. 3840-3854
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