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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 41
Volume 41, Number 1, January 2022
- Shuhan Zhang
, Fan Yang
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. 1-14 - Jingxiao Ma
Approximate Logic Synthesis Using Boolean Matrix Factorization. 15-28 - Xiang-Min Yang, Pei-Pei Chen
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. 29-34 - Rana Elnaggar
Runtime Malware Detection Using Embedded Trace Buffers. 35-48 - Zhuo Su
Code Synthesis for Dataflow-Based Embedded Software Design. 49-61 - Zhishan Guo
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority. 62-75 - Yawen Wu
Cooperative Communication Between Two Transiently Powered Sensor Nodes by Reinforcement Learning. 76-90 - Tai Chang, Jen-Wei Hsieh
EMT: Elegantly Measured Tanner for Key-Value Store on SSD. 91-103 - Mehdi Sadi
Test and Yield Loss Reduction of AI and Deep Learning Accelerators. 104-115 - Xinkai Song
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks. 116-128 - Elena-Diana Sandru
Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction. 129-142 - Haocheng Li
Pin-Accessible Legalization for Mixed-Cell-Height Circuits. 143-154 - Yibai Meng
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs. 155-168 - Lihua Yang
Improving F2FS Performance in Mobile Devices With Adaptive Reserved Space Based on Traceback. 169-182 - Animesh Basak Chowdhury
Robust Deep Learning for IC Test Problems. 183-195 - Jintao Yu
APmap: An Open-Source Compiler for Automata Processors. 196-200
Volume 41, Number 2, February 2022
- Maryam Shafiee
An In-Field Programmable Adaptive CMOS LNA for Intelligent IoT Sensor Node Applications. 201-210 - Salim Ullah
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators. 211-224 - Junick Ahn
State-of-Charge Estimation of Supercapacitors in Transiently-Powered Sensor Nodes. 225-237 - Jiawan Wang
PDF: Path-Oriented, Derivative-Free Approach for Safety Falsification of Nonlinear and Nondeterministic CPS. 238-251 - Hengli Huang, Xiaohang Wang
Detection of and Countermeasure Against Thermal Covert Channel in Many-Core Systems. 252-265 - Satwik Patnaik
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. 266-280 - Sanjit Kumar Roy
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms. 281-293 - Renping Liu, Duo Liu
Self-Adapting Channel Allocation for Multiple Tenants Sharing SSD Devices. 294-305 - Zhaoying Li
ChordMap: Automated Mapping of Streaming Applications Onto CGRA. 306-319 - Zhe Jiang
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems. 320-333 - Yufei Ni
Agglomerative Memory and Thread Scheduling for High-Performance Ray-Tracing on GPUs. 334-345 - Weifan Sun, Wei Fan, Mengying Zhao
Deep Reinforcement-Learning-Guided Backup for Energy Harvesting Powered Systems. 346-358 - Lingling Lao
Timing and Resource-Aware Mapping of Quantum Circuits to Superconducting Processors. 359-371 - Zheng Qu
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition. 372-385 - Darong Huang
COCKTAIL: Multicore Co-Optimization Framework With Proactive Reliability Management. 386-399
Volume 41, Number 3, March 2022
- Hongyu An
Three-Dimensional Neuromorphic Computing System With Two-Layer and Low-Variation Memristive Synapses. 400-409 - Kyungwook Chang
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. 410-423 - Amin Monfared
Secure and Efficient Exponentiation Architectures Using Gaussian Normal Basis. 424-437 - Jim Plusquellic
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor. 438-451 - Huanyu Wang
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks. 452-465 - Xingyu Meng
RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities. 466-477 - Guoqi Xie
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling. 478-491 - Jie Zhan
Exploring the Effect of Energy Storage Sizing on Intermittent Computing System Performance. 492-501 - Linwei Niu
Fixed-Priority Scheduling for Reliable and Energy-Aware (m, k)-Deadlines Enforcement With Standby-Sparing. 502-515 - Junlong Zhou
Throughput-Conscious Energy Allocation and Reliability-Aware Task Assignment for Renewable Powered In-Situ Server Systems. 516-529 - Zhuwei Qin
CaptorX: A Class-Adaptive Convolutional Neural Network Reconfiguration Framework. 530-543 - Yina Lv
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices. 544-557 - Debraj Kundu, Sudip Roy
Mixing Models as Integer Factorization: A Key to Sample Preparation With Microfluidic Biochips. 558-570 - Mackenzie J. Wibbels
Causal Path Identification for Timed and Sequential Circuits. 571-582 - Bing Li
An Automated Quantization Framework for High-Utilization RRAM-Based PIM. 583-596 - Yun Liang
An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models. 597-613 - Patrick Sittel
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. 614-627 - Jianyi Cheng
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. 628-641 - Chang-Cheng Ko
Majority Logic Circuit Minimization Using Node Addition and Removal. 642-655 - Byungmin Ahn, Taewhan Kim
Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach. 656-668 - Ran Chen
Faster Region-Based Hotspot Detection. 669-680 - Zhiqiang Liu
feGRASS: Fast and Effective Graph Spectral Sparsification for Scalable Power Grid Analysis. 681-694 - Dennis D. Weller
Fast and Efficient High-Sigma Yield Analysis and Optimization Using Kernel Density Estimation on a Bayesian Optimized Failure Rate Model. 695-708 - Wei Zhong
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization. 709-722 - Bin Zhou
A-Cache: Asymmetric Buffer Cache for RAID-10 Systems Under a Single-Disk Failure to Significantly Boost Availability. 723-736 - Kuen-Jong Lee
An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults. 737-749 - Youngkwang Lee, Young-Woo Lee
Reduced-Pin-Count BOST for Test-Cost Reduction. 750-761 - Mengyun Liu, Xin Li, Krishnendu Chakrabarty
Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation. 762-775 - Irith Pomeranz
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults. 776-783 - Andrew B. Kahng, Jian Kuang, Wen-Hao Liu, Bangqi Xu
In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. 784-788 - Zhengqi Gao
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space. 789-793 - Akira Ito
Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials. 794-798
Volume 41, Number 4, April 2022
- Khanh N. Dang
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems. 799-812 - Jun Tao
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. 813-826 - Dongning Ma
DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature Variations. 827-839 - Ilaria Scarabottolo
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. 840-853 - Abdulrahman Alaql
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection. 854-867 - Abhijitt Dhavlle
Imitating Functional Operations for Mitigating Side-Channel Leakage. 868-881 - Zhaoyan Shen
Prism-SSD: A Flexible Storage Interface for SSDs. 882-896 - Justin Morris
Locality-Based Encoder and Model Quantization for Efficient Hyper-Dimensional Computing. 897-907 - Zhifei Wang
HERO: Pbit High-Radix Optical Switch Based on Integrated Silicon Photonics for Data Center. 908-921 - Yuhao Zhang
A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions. 922-935 - Xiaobing Chen
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training. 936-949 - Muhammad Imran
ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change Memory. 950-963 - Jincheng Yu
INCAME: Interruptible CNN Accelerator for Multirobot Exploration. 964-978 - Huimei Cheng
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming. 979-992 - Chia-Chih Chi, Jie-Hong R. Jiang
Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation. 993-1005 - Saurabh Dash
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation. 1006-1019 - Moritz Scherer
CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration With Better-Than-Binary Energy Efficiency. 1020-1033 - Arman Iranfar
Multiagent Reinforcement Learning for Hyperparameter Optimization of Convolutional Neural Networks. 1034-1047 - Zihao Yuan
PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies. 1048-1061 - Federico Terraneo
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models. 1062-1075 - Andrew B. Kahng, Lutong Wang
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine. 1076-1089 - Jin-Tai Yan
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. 1090-1102 - Jianli Chen
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints. 1103-1115 - Zhe Jiang
Bridging the Pragmatic Gaps for Mixed-Criticality Systems in the Automotive Industry. 1116-1129 - Irith Pomeranz
Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence. 1130-1141 - Sangmin Park, Minho Cheong
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery. 1142-1153 - Sreeja Rajendran
A Novel Algorithm for Hardware Trojan Detection Through Reverse Engineering. 1154-1166 - Faiq Khalid
ForASec: Formal Analysis of Hardware Trojan-Based Security Vulnerabilities in Sequential Circuits. 1167-1180 - Mehran Goli
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. 1181-1185 - Junnan Shan
Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms. 1186-1190 - Theresa Kahale
Memristor Modeling Using the Modified Nodal Analysis Approach. 1191-1195
Volume 41, Number 5, May 2022
- Qi Xu
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC. 1196-1208 - Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. 1209-1221 - Zhengqi Gao
Efficient Non-Monte-Carlo Yield Estimation. 1222-1235 - Ying Wang
A Fast Precision Tuning Solution for Always-On DNN Accelerators. 1236-1248 - Davide Zoni
Design of Side-Channel-Resistant Power Monitors. 1249-1263 - Davide Poggi
Checking Robustness Against EM Side-Channel Attacks Prior to Manufacturing. 1264-1275 - Farzad Niknia
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips. 1276-1289 - Yufei Cui
Online Rare Category Identification and Data Diversification for Edge Computing. 1290-1301 - Yi Wang
PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory. 1302-1315 - Hui Chen
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission. 1316-1329 - Jeongbin Kim
STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment. 1330-1343 - Yunhui Qiu
A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration. 1344-1357 - Yuke Wang
STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms. 1358-1370 - Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza
FastSim: A Fast Simulation Framework for High-Level Synthesis. 1371-1385 - Xiaotong Cui
Toward Building and Optimizing Trustworthy Systems Using Untrusted Components: A Graph-Theoretic Perspective. 1386-1399 - Alexander A. Barkalov
Reducing LUT Count for Mealy FSMs With Transformation of States. 1400-1411 - Chia-Chun Lin
Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. 1412-1422 - Rachel Sterneck
Noise Sensitivity-Based Energy Efficient and Robust Adversary Detection in Neural Networks. 1423-1435 - Gang Li
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA. 1436-1447 - Tsung-Wei Huang
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System. 1448-1452 - Jinwei Zhang
Full-Chip Power Density and Thermal Map Characterization for Commercial Microprocessors Under Heat Sink Cooling. 1453-1466 - Ming Yang
Volume Reduction and Fast Generation of the Precharacterization Data for Floating Random Walk-Based Capacitance Extraction. 1467-1480 - Renan Netto
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. 1481-1494 - Chung-Kuan Cheng
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. 1495-1508 - Behnaz Ranjbar
Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems. 1509-1522 - Boqian Wang
Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture. 1523-1536 - Biresh Kumar Joardar
High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers. 1537-1549 - Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Zuo-Wei Yeh, Zhaofang Li, Chih-Cheng Lu, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang:
MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks. 1550-1562 - Jun-Yu Yang
Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction. 1563-1572 - Alireza Mahzoon
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. 1573-1586 - Irith Pomeranz
Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis. 1587-1591
Volume 41, Number 6, June 2022
- Andres Goens
mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary Topologies. 1592-1605 - Xiaofan Zhang
Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems. 1606-1619 - Lin Cheng
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. 1620-1635 - Emanuele Parisi
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping. 1636-1648 - Nicola Capodieci
A Taxonomy of Modern GPGPU Programming Methods: On the Benefits of a Unified Specification. 1649-1662 - Ismail Emir Yüksel
MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs. 1663-1673 - Adam Siemieniuk
OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory. 1674-1686 - Gowrish Basavarajappa
An Efficient EM-Based Synthesis Technique for Single-Band and Dual-Band Waveguide Filters. 1687-1692 - Quan Chen
EI-NK: A Robust Exponential Integrator Method With Singularity Removal and Newton-Raphson Iterations for Transient Nonlinear Circuit Simulation. 1693-1703 - Pritam Bhattacharjee
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. 1704-1715 - Dominik Sisejkovic
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. 1716-1729 - Nidish Vashistha
Detecting Hardware Trojans Using Combined Self-Testing and Imaging. 1730-1743 - Morteza Soltani
An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory. 1744-1756 - Che-Wei Chang
Leveraging Write Heterogeneity of Phase Change Memory on Supporting Self-Balancing Binary Tree. 1757-1770 - Jinhua Cui
ADS: Leveraging Approximate Data for Efficient Data Sanitization in SSDs. 1771-1784 - Jinhua Cui
Exploiting Uncorrectable Data Reuse for Performance Improvement of Flash Memory. 1785-1798 - Xiangzhong Luo
Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond. 1799-1812 - Di Liu
CARTAD: Compiler-Assisted Reinforcement Learning for Thermal-Aware Task Scheduling and DVFS on Multicores. 1813-1826 - Necati Uysal
XMAP: Programming Memristor Crossbars for Analog Matrix-Vector Multiplication: Toward High Precision Using Representable Matrices. 1827-1841 - Taozhong Li
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. 1842-1854 - Ankit Wagle, Sarma B. K. Vrudhula
Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance. 1855-1867 - Zi Wang
SSSL: Secure Search Space Locking of Behavioral IPs. 1868-1877 - Georgios Tziantzioulis
OPDB: A Scalable and Modular Design Benchmark. 1878-1887 - Bentian Jiang
CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization. 1888-1901 - Kai Huang, Siang Chen
Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating. 1902-1915 - Shiyu Xu, Qi Wang
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation. 1916-1928 - Jeongwoo Heo
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. 1929-1942 - Supriyo Maji
A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs. 1943-1956 - Genggeng Liu
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. 1957-1970 - Lanlan Cui
A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash. 1971-1975
Volume 41, Number 7, July 2022
- Inga Abel
A Hierarchical Performance Equation Library for Basic Op-Amp Design. 1976-1989 - Tinghuan Chen
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation. 1990-2003 - Michael Zuzak
Evaluating the Security of Logic-Locked Probabilistic Circuits. 2004-2009 - Dimitris Mouris
Privacy-Preserving IP Verification. 2010-2023 - Zongsheng Hou
Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. 2024-2037 - Donghyun Min
A Content-Based Ransomware Detection and Backup Solid-State Drive for Ransomware Defense. 2038-2051 - Rana Elnaggar
Securing SoCs With FPGAs Against Rowhammer Attacks. 2052-2065 - Rana Elnaggar
Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters. 2066-2079 - Hengshan Yue
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism. 2080-2093 - Zihan Zhang
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. 2094-2106 - Dinesh Rajasekharan
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model. 2107-2114 - Yintao He
Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. 2115-2127 - Jinyu Zhan
Accelerating Queries of Big Data Systems by Storage-Side CPU-FPGA Co-Design. 2128-2141 - Lana Josipovic
From C/C++ Code to High-Performance Dataflow Circuits. 2142-2155 - Bosheng Liu
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks. 2156-2169 - Renjian Pan, Zhaobo Zhang, Xin Li, Krishnendu Chakrabarty
Unsupervised Two-Stage Root-Cause Analysis for Integrated Systems. 2170-2184 - Xing Huang
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips. 2185-2198 - Shenglan Ni
Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors. 2199-2212 - Jiahua Li
Efficient Static-Driven Integration for Step-Function Transient Simulation. 2213-2222 - Steven Herbst
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs. 2223-2236 - Yu-Sheng Lu
Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip. 2237-2249 - Mengting Lu
EDC: An Elastic Data Cache to Optimizing the I/O Performance in Deduplicated SSDs. 2250-2262 - Rassul Bairamkulov
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping. 2263-2275 - Romain Mercier
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation. 2276-2289 - Bartosz Kaczmarek
LBIST for Automotive ICs With Enhanced Test Generation. 2290-2300 - Ching-Yuan Chen
Efficient Identification of Critical Faults in Memristor-Based Inferencing Accelerators. 2301-2314 - Irith Pomeranz
GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults. 2315-2322 - Chong-Siao Ye
Efficient Test Compression Configuration Selection. 2323-2336 - Jun-Yu Yang
Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing. 2337-2347 - Arjun Chaudhuri
C-Testing and Efficient Fault Localization for AI Accelerators. 2348-2361 - Sudipa Mandal
Migrating Assertions From Dense to Discrete Time. 2362-2371
Volume 41, Number 8, August 2022
- Xiaopeng Wu
A Fast Analysis Method of Multiphysics Coupling for 3-D Microsystem. 2372-2379 - Satyajit Mohapatra
Dispersion in Placement: Quantification and Insights. 2380-2392 - Zahra Ramezani
Testing Cyber-Physical Systems Using a Line-Search Falsification Method. 2393-2406 - Yangguang Cui, Kun Cao
Client Scheduling and Resource Management for Efficient Training in Heterogeneous IoT-Edge Federated Learning. 2407-2420 - Jiaji He
Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations. 2421-2434 - Lilas Alrahis
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. 2435-2448 - Julian Leonhard, Nimisha Limaye
Digitally Assisted Mixed-Signal Circuit Security. 2449-2462 - Shuo-Han Chen
A File-Oriented Fast Secure Deletion Strategy for Shingled Magnetic Recording Drives. 2463-2476 - Yubiao Pan
HCFTL: A Locality-Aware Flash Translation Layer for Efficient Address Translation. 2477-2489 - Mohamed Ibrahim
Efficient Regulation of Synthetic Biocircuits Using Droplet-Aliquot Operations on MEDA Biochips. 2490-2503 - Mahmoud Elfar
Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips. 2504-2517 - Matthias Függer
Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. 2518-2531 - Mohamed A. Elgammal
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement. 2532-2545 - Yun Liang
FCNNLib: A Flexible Convolution Algorithm Library for Deep Learning on FPGAs. 2546-2559 - Xin Fan
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application. 2560-2572 - Siang-Yun Lee
A Simulation-Guided Paradigm for Logic Synthesis and Verification. 2573-2586 - Pengcheng Zhu
An Iterated Local Search Methodology for the Qubit Mapping Problem. 2587-2597 - Yifan Chang, Yifan Wang, Jian Peng
MFS: A Brain-Inspired Memory Formation System for GAN. 2598-2610 - Wei Jiang
Interpretability-Guided Defense Against Backdoor Attacks to Deep Neural Networks. 2611-2624 - Abhiroop Bhattacharjee
NEAT: Nonlinearity Aware Training for Accurate, Energy-Efficient, and Robust Implementation of Neural Networks on 1T-1R Crossbars. 2625-2637 - Paolo Manfredi
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression. 2638-2651 - Luigi Colalongo
A Second-Order Surface Potential Core Model for Submicron MOSFETs. 2652-2656 - Hao Geng
High-Speed Adder Design Space Exploration via Graph Neural Processes. 2657-2670 - Bentian Jiang
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. 2671-2684 - Hao Geng
Hotspot Detection via Attention-Based Deep Layout Metric Learning. 2685-2698 - Jin-Tai Yan
Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs. 2699-2713 - Mahmut Burak Karadeniz
TALIPOT: Energy-Efficient DNN Booster Employing Hybrid Bit Parallel-Serial Processing in MSB-First Fashion. 2714-2727 - Muhammad Ibtesam
Highly Efficient Test Architecture for Low-Power AI Accelerators. 2728-2738 - Hogyeong Kim
Multibank Optimized Redundancy Analysis Using Efficient Fault Collection. 2739-2752 - Jen-Wei Hsieh
Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache. 2753-2757 - Md Rubel Ahmed
Mining Patterns From Concurrent Execution Traces. 2758-2762 - Pragnan Chakravorty
A Modified General Diode Equation. 2763-2767
Volume 41, Number 9, September 2022
- Kangkang Xu
The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source. 2768-2779 - Konstantinos Touloupas
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing. 2780-2793 - Keertana Settaluri
Automated Design of Analog Circuits Using Reinforcement Learning. 2794-2807 - Yongchen Wang
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. 2808-2820 - Honghui Tang
MPFA: An Efficient Multiple Faults-Based Persistent Fault Analysis Method for Low-Cost FIA. 2821-2834 - Chun-Feng Wu
Performance Enhancement of SMR-Based Deduplication Systems. 2835-2848 - Weiguang Pang
Toward the Predictability of Dynamic Real-Time DNN Inference. 2849-2862 - David Kuang-Hui Yu
Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems. 2863-2876 - Yang Wang
Locking Protocols for Parallel Real-Time Tasks With Semaphores Under Federated Scheduling. 2877-2890 - Yiwen Zhang:
Energy-Aware Nonpreemptive Scheduling of Mixed-Criticality Real-Time Task Systems. 2891-2900 - Saravanan Sethuraman
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem. 2901-2914 - Mark Wijtvliet
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture. 2915-2928 - Baofen Yuan
Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. 2929-2942 - Khouloud Bouaziz
Mesh of Trees FPGA Architecture: Exploration and Optimization. 2943-2956 - Tao Luo
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory. 2957-2969 - Sanjai Narain
Fast Design Space Exploration of Nonlinear Systems: Part I. 2970-2983 - Prerit Terway
Fast Design Space Exploration of Nonlinear Systems: Part II. 2984-2999 - Renao Yan
Multilayer Memristive Neural Network Circuit Based on Online Learning for License Plate Detection. 3000-3011 - Shayan Hassantabar
SCANN: Synthesis of Compact and Accurate Neural Networks. 3012-3025 - Myeonggu Kang
A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture. 3026-3039 - Abdelrahman Hosny
Characterizing and Optimizing EDA Flows for the Cloud. 3040-3051 - Cong Xu, Chunhua Wang
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask. 3052-3065 - Liang Chen
Electrothermal Simulation and Optimal Design of Thermoelectric Cooler Using Analytical Approach. 3066-3077 - Rui Zhang, Taizhi Liu, Kexin Yang, Linda Milor
CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration. 3078-3091 - Zhifeng Lin, Yanyue Xie
An Incremental Placement Flow for Advanced FPGAs With Timing Awareness. 3092-3103 - Yi-Chen Lu
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning. 3104-3117 - Guojin Chen, Wanli Chen, Qi Sun
DAMO: Deep Agile Mask Optimization for Full-Chip Scale. 3118-3131 - Yibo Lin
Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing. 3132-3142 - Qisheng Wang
Equivalence Checking of Sequential Quantum Circuits. 3143-3156 - Adrian Tatulian
Nonuniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation. 3157-3161
Volume 41, Number 10, October 2022
- Martin Rapp
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. 3162-3181 - Qi Xu
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. 3182-3187 - Sujan K. Gonugondla
Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications. 3188-3201 - Andrew Stern
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment. 3202-3215 - Pranesh Santikellur, Rajat Subhra Chakraborty
Correlation Integral-Based Intrinsic Dimension: A Deep-Learning-Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks. 3216-3227 - Yanjiang Liu
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic. 3228-3238 - Behnaz Ranjbar
BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems. 3239-3251 - Zhuo Su
MDD: A Unified Model-Driven Design Framework for Embedded Control Software. 3252-3265 - Vanchinathan Venkataramani
ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC. 3266-3275 - Chenlin Ma
Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory. 3276-3289 - Dhananjaya Wijerathne
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. 3290-3303 - Yu-Pei Liang
Planting Fast-Growing Forest by Leveraging the Asymmetric Read/Write Latency of NVRAM-Based Systems. 3304-3317 - Anirudh Mohan Kaushik
Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multicore Real-Time Systems. 3318-3331 - Sanchita Saha Ray
Worst Case O(N) Comparison-Free Hardware Sorting Engine. 3332-3345 - Rassul Bairamkulov
QuCTS - Single-Flux Quantum Clock Tree Synthesis. 3346-3358 - Asif Mirza
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations. 3359-3372 - Kuan-Yu Chang
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture. 3373-3386 - Jungi Lee, Jongeun Lee
Specializing CGRAs for Light-Weight Convolutional Neural Networks. 3387-3399 - Cheng Liu, Cheng Chu, Dawen Xu, Ying Wang, Qianlong Wang, Huawei Li, Xiaowei Li
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. 3400-3413 - Jinyu Zhan
Improving Fault Tolerance for Reliable DNN Using Boundary-Aware Activation. 3414-3425 - Ahmet Inci
DeepNVM++: Cross-Layer Modeling and Optimization Framework of Nonvolatile Memories for Deep Learning. 3426-3437 - Yingcheng Bu
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory. 3438-3451 - Ruslan Dashkin
General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. 3452-3465 - Zizheng Guo
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. 3466-3478 - Chengning Wang
Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction. 3479-3491 - Qi Xu
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning. 3492-3502 - Rongjian Liang
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. 3503-3514 - Vidya A. Chhabria
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis. 3515-3528 - Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen
Timing-Aware Fill Insertions With Design-Rule and Density Constraints. 3529-3542 - Debao Wei
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory. 3543-3547 - Mehdi Safarpour
A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming. 3548-3552 - Irith Pomeranz
Storage-Based Logic Built-in Self-Test With Multicycle Tests. 3553-3557 - Hao Du
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network. 3558-3562
Volume 41, Number 11, November 2022
- Yu Huang
ReaDy: A ReRAM-Based Processing-in-Memory Accelerator for Dynamic Graph Convolutional Networks. 3567-3578 - Jiaxian Chen, Yiquan Lin, Kaoyi Sun, Jiexin Chen, Chenlin Ma
GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory. 3579-3590 - Huichuan Zheng
Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs. 3591-3601 - Shailja Pandey
NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory. 3602-3613 - Rehan Ahmed
Stochastic Guarantees for Adaptive Energy Harvesting Systems. 3614-3625 - Chukwufumnanya Ogbogu
Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet. 3626-3637 - Ying-Jan Wu
iNVMFS: An Efficient File System for NVRAM-Based Intermittent Computing Devices. 3638-3649 - Sosei Ikeda
Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification. 3650-3660 - Mohammed Abderehman
BLAST: Belling the Black-Hat High-Level Synthesis Tool. 3661-3672 - Gaoyang Dai
Response-Time Analysis of Limited-Preemptive Sporadic DAG Tasks. 3673-3684 - Junjie Feng
eRDAC: Efficient and Reliable Remote Direct Access and Control for Embedded Systems. 3685-3696 - Rongwei Zheng
SENTunnel: Fast Path for Sensor Data Access on Automotive Embedded Systems. 3697-3708 - Chenlin Ma
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model. 3709-3720 - Wei-Che Tsai
Intermittent-Aware Distributed Concurrency Control. 3721-3732 - Arnaud de Grandmaison, Karine Heydemann
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification. 3733-3744 - Long Zheng
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures. 3745-3756 - Andrea Fanti
Toward Register Spilling Security Using LLVM and ARM Pointer Authentication. 3757-3766 - Jan Sommer, M. Akif Özkan
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. 3767-3778 - Weidong Zhu
NASA: NVM-Assisted Secure Deletion for Flash Memory. 3779-3790 - Yin-Chiuan Chen
Exploring Synchronous Page Fault Handling. 3791-3802 - Jiali Li
Horae: A Hybrid I/O Request Scheduling Technique for Near-Data Processing-Based SSD. 3803-3813 - Jin-Wei Chang, Tseng-Yi Chen
When B-Tree Meets Skyrmion Memory: How Skyrmion Memory Affects an Indexing Scheme. 3814-3825 - Lilas Alrahis
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. 3826-3837 - Ourania Spantidi
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration. 3838-3849 - Jiwon Kim
DynLiB: Maximizing Energy Availability of Hybrid Li-Ion Battery Systems. 3850-3861 - Jinyu Zhan
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems. 3862-3873 - Shuangshuang Chang
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms. 3874-3885 - Jiaming Qiu
Adaptive Edge Offloading for Image Classification Under Rate Limit. 3886-3897 - Banghu Yin
Efficient Complete Verification of Neural Networks via Layerwised Splitting and Refinement. 3898-3909 - Yue Tang
Enabling Weakly Supervised Temporal Action Localization From On-Device Learning of the Video Stream. 3910-3921 - Xiaofeng Ding
FRL: Fast and Reconfigurable Accelerator for Distributed Sound Source Localization. 3922-3933 - Elbruz Ozen
Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation. 3934-3945 - Dharamjeet
LLSM: A Lifetime-Aware Wear-Leveling for LSM-Tree on NAND Flash Memory. 3946-3956 - Paolo Pazzaglia
Characterizing the Effect of Deadline Misses on Time-Triggered Task Chains. 3957-3968 - Liren Yang
Efficient Backward Reachability Using the Minkowski Difference of Constrained Zonotopes. 3969-3980 - Chenchen Fu
Throughput Maximization in Wireless Communication Systems Powered by Hybrid Energy Harvesting. 3981-3992 - Weiwei Chen
Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning. 3993-4003 - Soumik Sinha
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning. 4004-4015 - Clara Hobbs
Safety Analysis of Embedded Controllers Under Implementation Platform Timing Uncertainties. 4016-4027 - Bingyao Wang
Tinkertoy: Build Your Own Operating Systems for IoT Devices. 4028-4039 - Jiaojiao Wu
Adaptive Switch on Wear Leveling for Enhancing I/O Latency and Lifetime of High-Density SSDs. 4040-4051 - Francesco Restuccia
Cut and Forward: Safe and Secure Communication for FPGA System on Chips. 4052-4063 - Xiaohang Wang
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum. 4064-4075 - Qiao Li
Resolving the Reliability Issues of Open Blocks for 3-D NAND Flash: Observations and Strategies. 4076-4087 - Teng Wang
ViA: A Novel Vision-Transformer Accelerator Based on FPGA. 4088-4099 - Jun Xia
PervasiveFL: Pervasive Federated Learning for Heterogeneous IoT Systems. 4100-4111 - Chuxi Li
Memory-Computing Decoupling: A DNN Multitasking Accelerator With Adaptive Data Arrangement. 4112-4123 - Jie Peng
CMQ: Crossbar-Aware Neural Network Mixed-Precision Quantization via Differentiable Architecture Search. 4124-4133 - Nikhil Rangarajan
A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. 4134-4144 - Harsh Sharma
SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator. 4145-4156 - Junjie Shi
Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS. 4157-4168 - Wojciech Romaszkan
SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration. 4169-4180 - Jiwon Kim
PVoT: Reconfigurable Photovoltaic Array for Indoor Light Energy-Powered Batteryless Devices. 4181-4192 - Nicole Fronda
Differentiable Inference of Temporal Logic Formulas. 4193-4204 - Chiao Hsieh
Verifying Controllers With Vision-Based Perception Using Safe Approximate Abstractions. 4205-4216 - Bo Liu
An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing. 4217-4228 - Chih-Hsuan Yen
Stateful Neural Networks for Intermittent Systems. 4229-4240 - Gokul Krishnan
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. 4241-4252 - Zhiwei Feng
Online Rerouting and Rescheduling of Time-Triggered Flows for Fault Tolerance in Time-Sensitive Networking. 4253-4264 - Manish Goyal
NExG: Provable and Guided State-Space Exploration of Neural Network Control Systems Using Sensitivity Approximation. 4265-4276 - Samuele Germiniani
HARM: A Hint-Based Assertion Miner. 4277-4288 - Jan Spieck
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. 4289-4300 - Chia-Chih Lin
Enhancing Reliability and Security: A Configurable Poisoning PUF Against Modeling Attacks. 4301-4312 - Jiaen Xu, Xiaohang Wang
Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays. 4313-4324 - Mochamad Asri
CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures. 4325-4336 - Sairam Sri Vatsavai
Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors. 4337-4348 - Hassan Nassar
CaPUF: Cascaded PUF Structure for Machine Learning Resiliency. 4349-4360 - Rose Bohrer
Cyber-Physical Verification of Intermittently Powered Embedded Systems. 4361-4372 - Yiwen Xu
MIDAS: Safeguarding IoT Devices Against Malware via Real-Time Behavior Auditing. 4373-4384 - Priyanka Panigrahi
Quantifying Information Leakage for Security Verification of Compiler Optimizations. 4385-4396 - Yufei Cui
Bits-Ensemble: Toward Light-Weight Robust Deep Ensemble by Bits-Sharing. 4397-4408 - Aditi Kabra
Verified Train Controllers for the Federal Railroad Administration Train Kinematics Model: Balancing Competing Brake and Track Forces. 4409-4420 - Zhenya Zhang
Online Reset for Signal Temporal Logic Monitoring. 4421-4432 - Linjun Wu
FLAM-PUF: A Response-Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF. 4433-4444 - Samvid Mistry
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks. 4445-4456 - Feilong Zuo
Vulnerability Detection of ICS Protocols via Cross-State Fuzzing. 4457-4468 - Niccolò Borgioli
An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems. 4469-4480 - Fangzhu Lin
Fast and Low Overhead Metadata Operations for NVM-Based File System Using Slotted Paging. 4481-4491 - Wen Zhang
Sparsity-Aware Intelligent Spatiotemporal Data Sensing for Energy Harvesting IoT System. 4492-4503 - Zehong Yu
Mercury: Instruction Pipeline Aware Code Generation for Simulink Models. 4504-4515 - Enrico Tabanelli
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge. 4516-4526 - Yuhong Wen
WA-OPShare: Workload-Adaptive Over-Provisioning Space Allocation for Multi-Tenant SSDs. 4527-4538 - Jongouk Choi
CapOS: Capacitor Error Resilience for Energy Harvesting Systems. 4539-4550 - Nuzhat Yamin
Near-Optimal Energy Management for Energy Harvesting IoT Devices Using Imitation Learning. 4551-4562 - Yuheng Shen
Tardis: Coverage-Guided Embedded Operating System Fuzzing. 4563-4574 - Yi-Chen Lu
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs. 4575-4586 - Rakibul Hassan
A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic Locking. 4587-4599 - Sven Thijssen
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension. 4600-4611 - Sudip Poddar
A Generic Sample Preparation Approach for Different Microfluidic Labs-on-Chips. 4612-4625 - Tianyang Gai
Flexible Hotspot Detection Based on Fully Convolutional Network With Transfer Learning. 4626-4638 - Jianli Chen
Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints. 4639-4652 - Yu-Sheng Lu
On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment. 4653-4666 - Zhiyao Xie
Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. 4667-4680 - Jinwei Chen
NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design. 4681-4693 - Fuxun Yu
AntiDoteX: Attention-Based Dynamic Optimization for Neural Network Runtime Efficiency. 4694-4707 - Jie Xiao
Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive Attributes. 4708-4720 - Zheng Dong
Schedulability Analysis for Coscheduling Real-Time Tasks on Multiprocessors. 4721-4732 - Liqiang Lu
Morphling: A Reconfigurable Architecture for Tensor Computation. 4733-4746 - Ang Li
BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators. 4747-4757 - Xingchen Li
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. 4758-4770 - Jhon Gomez
DDtM: Increasing Latent Defect Detection in Analog/Mixed-Signal ICs Using the Difference in Distance to Mean Value. 4771-4781 - Ling Liang
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. 4782-4796 - Menghua Jia, Yachen Kong
Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory. 4797-4807 - Chen Chen
High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and g/I Methodology. 4808-4820 - Hsiao-Lun Liu
A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks. 4821-4825 - Jaeseong Lee
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology. 4826-4836 - Valeriy Sukharev
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. 4837-4850 - Jesús Jiménez-León
A Compact Modeling Methodology for Experimental Memristive Devices. 4851-4861 - Irith Pomeranz
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan. 4862-4872 - Fupeng Chen
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. 4873-4886 - Xiaodong Wang
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. 4887-4900 - Amin Sabet
Similarity-Aware CNN for Efficient Video Recognition at the Edge. 4901-4914 - Zichang He
PoBO: A Polynomial Bounding Method for Chance-Constrained Yield-Aware Optimization of Photonic ICs. 4915-4926 - Debayan Das
EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation. 4927-4938 - Gyungbin Kim
SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction. 4939-4951 - Abraham Peedikayil Kuruvila
Explainable Machine Learning for Intrusion Detection via Hardware Performance Counters. 4952-4964 - Fayu Wan
Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology. 4965-4974 - Shayan Hassantabar
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search. 4975-4990 - Lizhou Wu
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. 4991-5004 - Bin Zhou
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory. 5005-5015 - Hui-Chieh Yu
Contamination-Aware Synthesis for Programmable Microfluidic Devices. 5016-5029 - Wei Li
Adaptive Layout Decomposition With Graph Embedding Neural Networks. 5030-5042 - Jingyu Wang
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs. 5043-5056 - Yu-Teng Nien
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. 5057-5070 - Xiaoyu Zhang
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture. 5071-5084 - Sanbao Su, Chang Meng
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis. 5085-5099 - Kun-Chih Chen
Thermal Sensor Placement for Multicore Systems Based on Low-Complex Compressive Sensing Theory. 5100-5111 - Qiulin Wu
Understanding and Exploiting the Full Potential of SSD Address Remapping. 5112-5125 - Gabriel Ammes
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. 5126-5130 - Williams Paul Nwadiugwu
Reconfigurable Physical Resource Block Using Novel - Beamforming Filter Circuit for LTE-Based Cell-Edge Terminals. 5131-5135
Volume 41, Number 12, December 2022
- Zhenxin Zhao
Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning. 5138-5151 - Baidyanath Ray, Debanjana Datta
Cell-Based Synthesis of Multiple Analog Filter and Oscillator Topologies Employing Graph. 5152-5168 - Jiwoo Hong
An Automatic Circuit Design Framework for Level Shifter Circuits. 5169-5181 - Ranran Zhou
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm. 5182-5192 - Qi Sun
Counteracting Adversarial Attacks in Autonomous Driving. 5193-5206 - Sarah Amir
EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming. 5207-5219 - Jooyeon Choi, Hyeonuk Sim, Sangyun Oh
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution. 5220-5231 - Hui Chen
LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs. 5232-5245 - Sangeet Saha
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches. 5246-5260 - Xiao Moyuan
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs. 5261-5274 - Zhengyu Mei
TEA-Z: A Tiny and Efficient Architecture Based on Z Channel for Image Watermarking and Its Versatile Hardware Implementation. 5275-5287 - Fazal Hameed
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture. 5288-5298 - Debao Wei
TCSE: A Target Cell States Elimination Coding Strategy for Highly Reliable Data Storage Based on 3-D nand Flash Memory. 5299-5312 - Fangxin Liu
IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization. 5313-5326 - Mahta Mayahinia
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM. 5327-5332 - Xuhang Chen, Xueyan Wang
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. 5333-5342 - Hongxiang Fan
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. 5343-5356 - Yehua Ling
Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network. 5357-5366 - Yuheng Jiang, Jiajia Chen
A New Algorithm to Derive High Performance and Low Hardware Cost DCT for HEVC. 5367-5379 - Yuhao Zhou
An Efficient Power Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Metaheuristic Optimization Algorithm. 5380-5393 - Zhenge Jia
Personalized Neural Network for Patient-Specific Health Monitoring in IoT: A Metalearning Approach. 5394-5407 - Sourav Sanyal
Neuro-Ising: Accelerating Large-Scale Traveling Salesman Problems via Graph Neural Network Guided Localized Ising Solvers. 5408-5420 - Kai Zhong
Exploring the Potential of Low-Bit Training of Convolutional Neural Networks. 5421-5434 - Morteza Fayazi
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks. 5435-5448 - Xing Huang
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports. 5449-5463 - Qilin Zheng
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. 5464-5475 - Haikun Liu
A Simulation Framework for Memristor-Based Heterogeneous Computing Architectures. 5476-5488 - Yuhang Zhang
XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder. 5489-5500 - Tianshu Hou
A Space-Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing. 5501-5514 - Shumpei Morita
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. 5515-5525 - Grace Li Zhang
VirtualSync+: Timing Optimization With Virtual Synchronization. 5526-5540 - Jianli Chen
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects. 5541-5553 - Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures. 5554-5567 - Yih-Lang Li
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. 5568-5581 - Wei-Hsiang Tseng
A Bridge-Based Compression Algorithm for Topological Quantum Circuits. 5582-5595 - Darong Huang
Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers. 5596-5609 - Aurea Edna Moreno-Mojica
Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances. 5610-5620 - Ahmed Al-Qallaf
Design of Time-Mode PI Controller for Switched-Capacitor DC/DC Converter Using Differential Evolution Algorithm - A Design Methodology. 5621-5634 - Irith Pomeranz
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults. 5635-5643 - Natalia Lylina
SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. 5644-5656 - Arjun Chaudhuri
Functional Criticality Analysis of Structural Faults in AI Accelerators. 5657-5670 - Hyeonchan Lim, Hyojoon Yun, Sungho Kang
A Hybrid Test Scheme for Automotive IC in Multisite Testing. 5671-5680 - Mohamed Saleh Abouelyazid
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods. 5681-5694 - Sayandeep Sanyal
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits. 5695-5708 - Binod Kumar
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. 5709-5721 - Lama Shaer, Rouwaida Kanj
Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs. 5722-5726 - Hai Wang
DBP: Distributed Power Budgeting for Many-Core Systems in Dark Silicon. 5727-5731 - Qinyu Chen
Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance. 5732-5736
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