Verilator open-source SystemVerilog simulator and lint system

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

VeeR EH1 core

Project F brings FPGAs to life with exciting open-source designs you can build on.

Contains the code examples from The UVM Primer Book sorted by chapters.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Tile based architecture designed for computing efficiency, scalability and generality

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

SHA256 in (System-) Verilog / Open Source FPGA Miner

Proposed RISC-V Composable Custom Extensions Specification

Demo SoC for SiliconCompiler.

The RTL source for AnyCore RISC-V

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

FPGA on-device training and inference of a MLP neural network