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RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/
Lua based interactive firmware for ESP8266, ESP8285 and ESP32
Projects for an undergraduate OS course
GNU toolchain for RISC-V, including GCC
Including the SDK、HDK、Datasheet of RISC-V MCU CH32V307 and other relevant development materials
RISC-V cryptography extensions standardisation work.
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Pocket sized ESP32 display board with 180µW Always On Display
eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V
Source code for testing the Row Hammer error mechanism in DRAM devices. Described in the ISCA 2014 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf.
FreeBSD adapted for CHERI-RISC-V and Arm Morello.
PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publ…
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
Let's bring the Scott CPU to life. And program it.
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
SparseP is the first open-source Sparse Matrix Vector Multiplication (SpMV) software package for real-world Processing-In-Memory (PIM) architectures. SparseP is developed to evaluate and characteri…
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
DE10 NANO SHA3-256 Proof of Work Miner
Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs