🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

A Forth CPU and System on a Chip, based on the J1, written in VHDL

AXIOM firmware (linux image, gateware and software tools)

A rudimental RISCV CPU supporting RV32I instructions, in VHDL

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Verilog Convolutional Neural Network on PYNQ

FPGA related files for ORAM

A Simulation/Emulation of the CMV12000 image sensor for Apertus AXIOM Beta - GSoC

Advanced Computer Architecture at EPFL.