PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

Open source FPGA-based NIC and platform for in-network compute

Must-have verilog systemverilog modules

Verilog AXI components for FPGA implementation

HDL libraries and projects

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Verilog PCI express components

An open source GPU based off of the AMD Southern Islands ISA.

The USRP™ Hardware Driver Repository

32-bit Superscalar RISC-V CPU

A tiny Open POWER ISA softcore written in VHDL 2008

synthesiseable ieee 754 floating point library in verilog

Verilog I2C interface for FPGA implementation

Repository for basic (and not so basic) Verilog blocks with high re-use potential

A DDR3 memory controller in Verilog for various FPGAs

Verilog UART

AMBA bus lecture material

Opensource DDR3 Controller

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

A simple, basic, formally verified UART controller

The USRP™ Hardware Driver FPGA Repository

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

It's a core. Made on Twitch.

SystemC/TLM-2.0 Co-simulation framework

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Verilog Configurable Cache

An open source FPGA design for DSLogic

Standard Cell Library based Memory Compiler using FF/Latch cells