DRV8329-Q1

SLVSHB1 – MARCH 2023

DRV8329-Q1 4.5 to 60 V Three-phase BLDC Gate Driver

1 Features 3 Description
• 65-V Three Phase Half-Bridge Gate Driver The DRV8329-Q1 family of devices is an integrated
– Drives 3 High-Side and 3 Low-Side N-Channel gate driver for three-phase applications. The devices
MOSFETs (NMOS) provide three half-bridge gate drivers, each capable
– 4.5 to 60-V Operating Voltage Range of driving high-side and low-side N-channel power
– Supports 100% PWM Duty Cycle with Trickle MOSFETs. The device generates the correct gate
Charge pump drive voltages using an internal charge pump and
• Bootstrap based Gate Driver Architecture enhances the high-side MOSFETs using a bootstrap
– 1000-mA Maximum Peak Source Current circuit. A trickle charge pump is included to support
– 2000-mA Maximum Peak Sink Current 100% duty cycle. The Gate Drive architecture
• Integrated Current Sense Amplifier with low input supports peak gate drive currents up to 1-A source
offset (optimized for 1 shunt) and 2-A sink. The DRV8329-Q1 can operate from a
– Adjustable Gain (5, 10, 20, 40 V/V) single power supply and supports a wide input supply
• Hardware interface provides simple configuration range of 4.5 to 60 V.
• Ultra-low power sleep mode <1 uA at 25 ̊C The 6x and 3x PWM modes allow for simple
• 4-ns (typ) propagation delay matching between interfacing to controller circuits. The device has
phases integrated accurate 3.3-V LDO that can be used
• Independent driver shutdown path (DRVOFF) to power external controller and can be used as
• 65-V tolerant wake pin (nSLEEP) reference for CSA. The configuration settings for the
• Supports negative transients upto -10V on SHx device are configurable through hardware (H/W) pins.
• 6x and 3x PWM Modes
• Supports 3.3-V, and 5-V Logic Inputs The DRV8329-Q1 devices integrate low-side current
• Accurate LDO (AVDD), 3.3 V ±3%, 80 mA sense amplifier that allow current sensing for sum of
• Compact QFN Packages and Footprints current from all three phases of the drive stage.
• Adjustable VDS overcurrent threshold through A low-power sleep mode is provided to achieve
VDSLVL pin low quiescent current by shutting down most of
• Adjustable deadtime through DT pin the internal circuitry. Internal protection functions
• Efficient System Design With Power Blocks are provided for undervoltage lockout, GVDD fault,
• Integrated Protection Features MOSFET overcurrent, MOSFET short circuit, and
– PVDD Undervoltage Lockout (PVDDUV) overtemperature. Fault conditions are indicated on
– GVDD Undervoltage (GVDDUV) nFAULT pin.
– Bootstrap Undervoltage (BST_UV)
Device Information(1)
– Overcurrent Protection (VDS_OCP, SEN_OCP)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Thermal Shutdown (OTSD)
– Fault Condition Indicator (nFAULT) DRV8329ARGF-Q1 WQFN (40) 7.00 mm × 5.00 mm

2 Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Brushless-DC (BLDC) Motor Modules and PMSM
4.5 to 60 V
• Automotive Pumps
• Automotive HVAC fans
• E-Bikes, E-Scooters, and E-Mobility PWM (6x/3x)
DRV8329-Q1

• Automotive Body Electronics (Window, Door,

N-Channel
MOSFETs

Gate
nSLEEP 3 ½-H Bridge
Sunroof, Seat, Wiper) Modules
Drive M
Controller

DRVOFF Gate Driver

HW Current
Sense
nFAULT 1x Current Sense
SO
Built In Protection

DRV8329-Q1 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................28
2 Applications..................................................................... 1 8 Application and Implementation.................................. 29
3 Description.......................................................................1 8.1 Application Information............................................. 29
4 Device Comparison Table...............................................3 8.2 Typical Application.................................................... 29
5 Pin Configuration and Functions...................................4 8.3 Power Supply Recommendations.............................43
6 Specification.................................................................... 6 8.4 Layout....................................................................... 44
6.1 Absolute Maximum Ratings........................................ 6 9 Device and Documentation Support............................47
6.2 ESD Ratings Auto....................................................... 6 9.1 Device Support......................................................... 47
6.3 Recommended Operating Conditions.........................7 9.2 Documentation Support............................................ 47
6.4 Thermal Information 2pkg........................................... 7 9.3 Related Links............................................................ 47
6.5 Electrical Characteristics.............................................8 9.4 Receiving Notification of Documentation Updates....47
6.6 Typical Characteristics.............................................. 15 9.5 Community Resources..............................................47
7 Detailed Description......................................................16 9.6 Trademarks............................................................... 47
7.1 Overview................................................................... 16 10 Revision History.......................................................... 47
7.2 Functional Block Diagram......................................... 17 11 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................18 Information.................................................................... 47

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4 Device Comparison Table

Table 4-1. Different Device Variants
DEVICE DEVICE VARIANT Package LDO output DT pin and VDSLVL PWM_MODE
40-pin QFN
DRV8329-Q1 DRV8329A-Q1 3.3 V Available 6x
(7.00 mm x 5.00 mm)

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5 Pin Configuration and Functions

CSAGAIN
CSAREF

nSLEEP
VDSLVL

nFAULT

INLA
SO
DT
40

39

38

37

36

35

34

33
NC 1 32 INLB

NC 2 31 INLC

NC 3 30 INHA

GND 4 29 INHB

PVDD 5 28 INHC

NC 6 Thermal 27 AVDD

CPL 7 Pad 26 AGND

CPH 8 25 DRVOFF

GVDD 9 24 SN

BSTA 10 23 SP

SHA 11 22 LSS

GHA 12 21 GLC
13

14

15

16

17

18

19

20

Not to scale
GLA

BSTB

SHB

GHB

GLB

BSTC

SHC

GHC

Figure 5-1. DRV8329 RGF Package 40-pin VQFN With Exposed Thermal Pad Top View

Table 5-1. Pin Functions—40-Pin DRV8329-Q1 Devices

PIN NO.
NAME TYPE(1) DESCRIPTION
DRV8329
NC 1 — No connection.
NC 2 — No connection.
NC 3 — No connection.
GND 4 PWR Device ground. Refer Section 8.4.1 for the recommendation on connection.
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R,
PVDD 5 PWR 0.1µF, >2x PVDD-rated ceramic and >10uF local capacitance between the PVDD and GND pins.
TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
NC 6 — No connection.
CPL 7 PWR Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor between the
CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating
CPH 8 PWR voltage of the pin.
Gate driver power supply output. Connect a X5R or X7R, 30V rated ceramic ≥ 10-uF local capacitance
GVDD 9 PWR-O between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating
at least twice the normal operating voltage of the pin.
BSTA 10 O Bootstrap output pin. Connect a X5R or X7R, 1-µF, 25V ceramic capacitor between BSTA and SHA
High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the
SHA 11 I/O
VDS monitor and the output for the high-side gate driver sink.
GHA 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.

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Table 5-1. Pin Functions—40-Pin DRV8329-Q1 Devices (continued)

PIN NO.
NAME TYPE(1) DESCRIPTION
DRV8329
GLA 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
BSTB 14 O Bootstrap output pin. Connect a X5R or X7R, 1µF, 25V ceramic capacitor between BSTB and SHB
High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the
SHB 15 I/O
VDS monitor and the output for the high-side gate driver sink.
GHB 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLB 17 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
BSTC 18 O Bootstrap output pin. Connect a X5R or X7R, 1µF, 25V ceramic capacitor between BSTC and SHC
High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the
SHC 19 I/O
VDS monitor and the output for the high-side gate driver sink.
GHC 20 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLC 21 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink
LSS 22 PWR path for the low-side gate driver, and serves as an input to monitor the low-side MOSFET VDS voltage
and VSEN_OCP voltage.
Current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
SP 23 I
current shunt resistor.
SN 24 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the
DRVOFF 25 I
gate drivers into the pull-down state. This signal bypasses and overrides the digital core of DRV8329.
AGND 26 PWR Device analog ground. Refer Section 8.4.1 for the recommendation on connection.
3.3V regulator output. Connect a X5R or X7R, 1µF, >6.3V ceramic capacitor between the AVDD and
AVDD 27 PWR-O AGND pins. This regulator can source up to 80mA externally. TI recommends a capacitor voltage
rating at least twice the normal operating voltage of the pin.
INHC 28 I High-side gate driver control input for Phase C. This pin controls the output of the high-side FET.
INHB 29 I High-side gate driver control input for Phase B. This pin controls the output of the high-side FET.
INHA 30 I High-side gate driver control input for Phase A. This pin controls the output of the high-side FET.
INLC 31 I Low-side gate driver control input for Phase C. This pin controls the output of the low-side FET.
INLB 32 I Low-side gate driver control input for Phase B. This pin controls the output of the low-side FET.
INLA 33 I Low-side gate driver control input for Phase A. This pin controls the output of the low-side FET.
Gain settings for Current sense amplifier. The pin is a 4 level input pin set by an external resistor. See
CSAGAIN 34 I
Section 7.3.4 for more information.
Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power sleep mode. An
nSLEEP 35 I
1 to 1.2µs low pulse can be used to reset fault conditions without entering sleep mode.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external
nFAULT 36 OD
pull-up resistor to 3.3V to 5.0V.
VDS monitor trip point setting. Connect an analog level input from 0.1V to 2.5V to set a VDS monitor
VDSLVL 37 I
trip point setting for MOSFET overcurrent protection. See Section 8.2.1.1.7 for more information.
Current sense amplifier reference. Connect a X5R or X7R, 0.1µF, 6.3V ceramic capacitor between the
CSAREF 38 I
CSAREF and AGND pins.
Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and
SO 39 O
capacitor to AGND)
Gate drive deadtime setting. Connect a resistor of value between 10kΩ to 390kΩ between DT and
DT 40 I AGND to adjust deadtime between 100ns to 2000ns. If pin is left floating or connected to AGND fixed
value of 55ns deadtime is inserted.
Thermal Pad PWR Must be connected to GND

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output

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6 Specification
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage PVDD -0.3 65 V
Bootstrap pin voltage BSTx -0.3 80 V
Bootstrap pin voltage BSTx with respect to SHx -0.3 20 V
Bootstrap pin voltage BSTx with respect to GHx -0.3 20 V
Charge pump pin voltage CPL, CPH -0.3 VGVDD V
Gate driver regulator pin voltage GVDD -0.3 20 V
Analog regulator pin voltage AVDD -0.3 4 V
Logic pin voltage (nSLEEP) nSLEEP -0.3 65 V
DRVOFF, DT, INHx, INLx, nFAULT,
Logic pin voltage -0.3 6 V
VDSLVL
High-side gate drive pin voltage GHx -8 80 V
Transient 500-ns high-side gate drive pin voltage GHx -10 80 V
High-side gate drive pin voltage GHx with respect to SHx -0.3 20 V
High-side source pin voltage SHx -8 70 V
Transient 500-ns high-side source pin voltage SHx -10 72 V
Low-side gate drive pin voltage GLx with respect to LSS -0.3 20 V
Transient 500-ns low-side gate drive pin voltage(2) GLx with respect to LSS -1 20 V
Low-side gate drive pin voltage GLx with respect to GVDD 0.3 V
Transient 500-ns low-side gate drive pin voltage GLx with respect to GVDD 1 V
Low-side source sense pin voltage LSS -1 1 V
Transient 500-ns low-side source sense pin voltage LSS -10 8 V
Internally Internally
Gate drive current GHx, GLx A
Limited Limited
Current sense amplifer reference input pin voltage CSAREF -0.3 5.5 V
Shunt amplifier input pin voltage SN, SP -1 1 V
Transient 500-ns shunt amplifier input pin voltage SN, SP -10 8 V
Shunt amplifier output pin voltage SO -0.3 VCSAREF + 0.3 V
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Supports upto 5A for 500 nS when GLx-LSS is negative

6.2 ESD Ratings Auto

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
HBM ESD Classification Level 2
Electrostatic
V(ESD) V
discharge Charged device model (CDM), per AEC Q100-011 Corner pins ±750
CDM ESD Classification Level C4B Other pins ±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VPVDD Power supply voltage PVDD 4.5 60 V
Power supply voltage ramp rate at power
VPVDD_RAMP PVDD 30 V/us
up
Power supply voltage ramp rate during
VPVDD_RAMP PVDD 4 V/us
operation
Bootstrap pin voltage with respect to
VBST nSLEEP = High, INHx is switching 4 20 V
SHx
IAVDD (1) Regulator external load current AVDD 80 mA
Trickle charge pump external load
ITRICKLE BSTx 2 µA
current
VIN Logic input voltage DRVOFF, INHx, INLx, nSLEEP 0 5.5 V
VIN Logic input voltage DT, VDSLVL 0 3.4 V
fPWM PWM frequency INHx, INLx 0 200 kHz
VOD Open drain pullup voltage nFAULT 5.5 V
IOD Open drain output current nFAULT -10 mA
Total average gate-drive current (Low
IGS (1) IGHx, IGLx 30 mA
Side and High Side Combined)
Current sense amplifier reference
VCSAREF CSAREF 2.8 5.5 V
voltage
VSHSL Slew Rate on SHx pins 4 V/ns
CBSTx Capacitor between BSTx and SHx 4.7 (2) µF
CGVDD Capacitor between GVDD and GND 130 µF
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C

(1) Power dissipation and thermal limits must be observed

(2) Current flowing through boot diode (DBOOT) needs to be limited for CBSTx > 4.7µF.

6.4 Thermal Information 2pkg

DEVICE
THERMAL METRIC(1) RGF (VQFN) UNIT
40
RθJA Junction-to-ambient thermal resistance 30.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.1 °C/W
RθJB Junction-to-board thermal resistance 12.0 °C/W
ΨJT Junction-to-top characterization parameter 0.4 °C/W
ΨJB Junction-to-board characterization parameter 12.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (AVDD, PVDD, GVDD)
VPVDD =24V, nSLEEP = 0, TA = 25°C 1 µA
IPVDDQ PVDD sleep mode current
nSLEEP = LOW 2 µA
VPVDD = 24 V; nSLEEP = HIGH, INHx =
2 4 mA
INLX = LOW, DRVOFF = HIGH
IPVDDS PVDD standby mode current
nSLEEP = HIGH, INHx = INLX = LOW,
3 5.5 mA
DRVOFF = HIGH
VPVDD = 24 V, nSLEEP = HIGH, INHx
= INLX = Switching@20kHz, No FETs 4 7 mA
connected
nSLEEP = HIGH, INHx = INLX =
5 10 mA
IPVDD PVDD active mode current Switching@20kHz, No FETs connected
VPVDD = 8 V, nSLEEP = HIGH, INHx =
5 10 mA
INLX = LOW, No FETs connected
VPVDD = 24 V, nSLEEP = HIGH, INHx =
5 7 mA
INLX = LOW, No FETs connected
VBSTx = VSHx = 60V, VGVDD = 0V,
ILBSx Bootstrap pin leakage current 5 10 16 µA
nSLEEP = LOW
Bootstrap pin active mode transient INLx = INHx = Switching@20kHz, No
ILBS_TRAN 60 115 300 µA
leakage current FETs connected
INHx = HIGH, INLx = LOW, INLy
= INLz = HIGH, nSLEEP = HIGH,
135 200 280 µA
VPVDD = VSHX = VGVDD = 12V, VBSTx -
VSHx = 5V
INHx = HIGH, INLx = LOW, INLy
= INLz = HIGH, nSLEEP = HIGH,
70 105 145 µA
Bootstrap pin active mode leakage static VPVDD = VSHX = VGVDD = 12V, VBSTx -
ILBS_DC_SRC VSHx = 7V
source current
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX = 25 50 90 µA
VGVDD = 12V, VBSTx - VSHx = 5V
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX = 16 28 50 µA
VGVDD = 12V, VBSTx - VSHx = 7V
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX = 10 40 90 µA
Bootstrap pin active mode leakage static VGVDD = 12V, VBSTx - VSHx = 12V
ILBS_DC_SINK
sink current INHx = High, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX = 14 45 91 µA
VGVDD = 12V, VBSTx - VSHx = 12V
INHx = INLx = LOW, VBSTx - VSHx
= 15, VSHx = 0 to 60V, nSLEEP = 80 145 210 µA
HIGH, DRVOFF = LOW
INHx = INLx = LOW, VBSTx - VSHx
= 11, VSHx = 0 to 60V, nSLEEP = 15 20 30 µA
HIGH, DRVOFF = LOW
ILSHx Source pin leakage current
INHx = High, INLx = LOW, VBSTx -
VSHx = 15, VSHx = 0 to 60V, nSLEEP = 80 145 210 µA
HIGH, DRVOFF = LOW
INHx = HIGH, INLx = LOW, VBSTx -
VSHx = 11, VSHx = 0 to 60V, nSLEEP = 13 25 35 µA
HIGH, DRVOFF = LOW

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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
nSLEEP = HIGH to Active
mode (Outputs Ready), DRVOFF = 1 2 ms
LOW, CGVDD = 10 uF, CBSTx = 1 uF
nSLEEP = High to Active mode (Outputs
Turnon time (nSLEEP) Ready). CGVDD = 100 uF, CAVDD = 10 10 15 ms
tWAKE uF, CBSTx = 10 uF
VPVDD = 12V, nSLEEP = HIGH to
Active mode (Outputs Ready), DRVOFF 1 2 ms
= LOW, CGVDD = 10 uF
DRVOFF = LOW to Active mode
Turnon time (DRVOFF) 0.05 0.1 ms
(Outputs Ready), nSLEEP = High
tSLEEP Turnoff time nSLEEP = LOW to Sleep mode 20 us
tRST Minimum Reset Pulse Time nSLEEP = LOW period to reset faults 1 1.2 us
VPVDD ≥ 40 V, IGS = 10 mA, TJ= 25°C 11.8 13 15 V
22 V ≤VPVDD ≤ 40 V, IGS = 30 mA, TJ=
11.8 13 15 V
25°C
8 V ≤VPVDD ≤ 22 V, IGS = 30 mA, TJ=
GVDD Gate driver regulator voltage 11.8 13 15 V
VGVDD_RT 25°C
(Room Temperature)
6.75 V ≤VPVDD ≤ 8 V, IGS = 10 mA, TJ=
11.8 13 14.5 V
25°C
4.5 V ≤VPVDD ≤ 6.75 V, IGS = 10 mA, TJ= 2*VPVDD
13.5 V
25°C -1
VPVDD ≥ 40 V, IGS = 10 mA 11.5 15.5 V
22 V ≤VPVDD ≤ 40 V, IGS = 30 mA 11.5 15.5 V
8 V ≤VPVDD ≤ 22 V; IGS = 30 mA 11.5 15.5 V
VGVDD GVDD Gate driver regulator voltage
6.75 V ≤VPVDD ≤ 8 V, IGS = 10 mA 11.5 14.5 V
2*VPVDD
4.5 V ≤VPVDD ≤ 6.75 V, IGS = 10 mA 13.5 V
- 1.4
VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 30 mA, TJ=
3.26 3.3 3.33 V
25°C
AVDD Analog regulator voltage (Room VPVDD ≥ 6 V, 30 mA ≤ IAVDD ≤ 80 mA, TJ=
VAVDD_RT 3.2 3.3 3.4 V
Temperature) 25°C
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA, TJ=
3.13 3.3 3.46 V
25°C
VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 80 mA 3.2 3.3 3.4 V
VAVDD AVDD Analog regulator voltage
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA 3.125 3.3 3.5 V
LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP etc)
DRVOFF 0.8 V
VIL Input logic low voltage
INLx, INHx pins 0.8 V
DRVOFF 2.2 V
VIH Input logic high voltage
INLx, INHx pins 2.2 V
DRVOFF 200 400 650 mV
VHYS Input hysteresis
INLx, INHx pins 45 240 350 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V; -1 0 1 µA
nSLEEP, VPIN (Pin Voltage) = 65 V; 3 6.5 10 µA
IIH Input logic high current nSLEEP, VPIN (Pin Voltage) = 5 V; 3 6 10 µA
Other pins, VPIN (Pin Voltage) = 5 V; 7 20 35 µA
RPD_DRVOFF Input pulldown resistance DRVOFF To GND 100 200 300 kΩ
RPD_nSLEEP Input pulldown resistance nSLEEP To GND 500 800 1500 kΩ
RPD Input pulldown resistance All other pins To GND 150 250 350 kΩ

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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FOUR-LEVEL INPUTS (GAIN)
0.18*AV
VL1 Input level 1 voltage Tied to GND 0 V
DD
0.48*AV 0.5*AVD 0.52*AV
VL2 Input level 2 voltage 50 kΩ +/- 5% tied to GND V
DD D DD
0.82*AV 0.833*AV 0.85*AV
VL3 Input level 3 voltage 200 kΩ +/- 5% tied to GND V
DD DD DD
VL4 Input level 4 voltage HiZ or Connect to AVDD AVDD V
RPU Input pullup resistance GAIN To AVDD 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (nFAULT etc)
VOL Output logic low voltage IOD = 5 mA 0.4 V
IOZ Output logic high current VOD = 5 V -1 1 µA
COD Output capacitance VOD = 5 V 30 pF
GATE DRIVERS (GHx, GLx, SHx, SLx)
IGLx = -100 mA; VGVDD = 12V; No FETs
VGSHx_LO High-side gate drive low level voltage 0.05 0.11 0.24 V
connected
High-side gate drive high level voltage IGHx = 100 mA; VGVDD = 12V; No FETs
VGSHx_HI 0.28 0.44 0.82 V
(VBSTx - VGHx) connected
IGLx = -100 mA; VGVDD = 12V; No FETs
VGSLx_LO Low-side gate drive low level voltage 0.05 0.11 0.27 V
connected
Low-side gate drive high level voltage IGHx = 100 mA; VGVDD = 12V; No FETs
VGSLx_HI 0.28 0.44 0.82 V
(VGVDD - VGHx) connected
INHx = HIGH, INLx = LOW, INLy = INLz
8.4 9.6 11.1 V
= HIGH, VPVDD >15V, VGVDD ≥11.5V
High-side gate drive voltage in steady INHx = HIGH, INLx = LOW, INLy = INLz
VGSH_100_PH 7.5 8.3 9 V
state with 100 % duty cycle (GHx- SHx) = HIGH, VGVDD ≥11.5V
INHx = HIGH, INLx = LOW, INLy = INLz
5.7 6.5 7.6 V
= HIGH, 7V ≥VGVDD ≥ 8V
RDS(ON)_PU_
High-side pullup switch resistance IGHx = 100 mA; VGVDD= 12V 2.7 4.5 8.4 Ω
HS

RDS(ON)_PD_
High-side pulldown switch resistance IGHx = 100 mA; VGVDD = 12V 0.2 1.1 2.4 Ω
HS

RDS(ON)_PU_
Low-side pullup switch resistance IGLx = 100 mA; VGVDD = 12V 2.7 4.5 8.3 Ω
LS

RDS(ON)_PD_
Low-side pulldown switch resistance IGLx = 100 mA; VGVDD = 12V 0.2 1.1 2.8 Ω
LS

IDRIVEP_HS High-side peak source gate current VGSHx = 12V 550 1000 1575 mA
IDRIVEN_HS High-side peak sink gate current VGSHx = 0V 1150 2000 2675 mA
IDRIVEP_LS Low-side peak source gate current VGSLx = 12V 550 1000 1575 mA
IDRIVEN_LS Low-side peak sink gate current VGSLx = 0V 1150 2000 2675 mA
RPD_LS Low-side passive pull down GLx to LSS 80 100 120 kΩ
RPDSA_HS High-side semiactive pull down GHx to SHx, VGSHx = 2V 8 10 12.5 kΩ
GATE DRIVERS TIMINGS
tPDR_LS Low-side rising propagation delay INLx to GLx rising, VGVDD > 8V 70 100 145 ns
tPDF_LS Low-side falling propagation delay INLx to GLx falling, VGVDD > 8V 70 100 135 ns
INHx to GHx rising, VGVDD = VBSTx -
tPDR_HS High-side rising propagation delay 65 100 145 ns
VSHx > 8V
INHx to GHx falling, VGVDD = VBSTx -
tPDF_HS High-side falling propagation delay 70 100 140 ns
VSHx > 8V

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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GLx turning ON to GLx turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -25 ±4 25 ns
to 60V, No load on GHx and GLx
GLx turning OFF to GHx turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -28 ±4 28 ns
tPD_MATCH_P to 60V, No load on GHx and GLx
Matching propagation delay per phase
H GHx turning ON to GHx turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -25 ±4 25 ns
to 60V, No load on GHx and GLx
GHx turning OFF to GLx turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -25 ±4 25 ns
to 60V, No load on GHx and GLx
GHx turning ON to GHy turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -10 ±4 10 ns
to 60V, No load on GHx and GLx
GLx turning ON to GLy turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -10 ±4 10 ns
tPD_MATCH_P Matching propagation delay phase to to 60V, No load on GHx and GLx
H_PH phase GHx turning OFF to GHy turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V to -15 ±4 15 ns
60V, No load on GHx and GLx
GLx turning OFF to GLy turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V -10 ±4 10 ns
to 60V, No load on GHx and GLx
Minimum input pulse width on INHx,
tPW_MIN INLx that changes the output on GHx, 18 32 45 ns
GLx
tDEAD Gate drive dead time configurable range 50 2000 ns
DT pin floating 35 55 90 ns
DT pin connected to GND 25 55 80 ns
tDEAD Gate drive dead time
10 kΩ between DT pin and GND 75 100 140 ns
390 kΩ between DT pin and GND 1350 2000 2650 ns
BOOTSTRAP DIODES
IBOOT = 100 µA 0.8 V
VBOOTD Bootstrap diode forward voltage
IBOOT = 100 mA 1.6 V
Bootstrap dynamic resistance
RBOOTD IBOOT = 100 mA and 50 mA 4.5 5.5 9 Ω
(ΔVBOOTD/ΔIBOOT)
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, CSAREF)
CSAGAIN = Tied to GND 4.92 5 5.05 V/V
CSAGAIN = 50kΩ ±5% tied to GND 9.9 10 10.1 V/V
ACSA Sense amplifier gain
CSAGAIN = 200kΩ ±5% tied to GND 19.75 20 20.2 V/V
CSAGAIN =Hi-Z; 39.6 40 40.6 V/V
ACSA_ERR Sense amplifier gain error TJ = 25℃ -1.5 1.5 %
ACSA_ERR_D Sense amplifier gain error temperature
-20 20 ppm/℃
RIFT drift
NL Non linearity Error 0.01 0.05 %

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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD =
0.6 1 µs
500pF
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD =
0.6 1.1 µs
500pF
tSET Settling time to ±1%
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD =
0.7 1.2 µs
500pF
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD =
0.8 1.7 µs
500pF
VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD =
0.3 0.5 µs
60pF
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD =
0.3 0.5 µs
60pF
tSET Settling time to ±1%
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD =
0.3 0.65 µs
60pF
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD =
0.3 0.8 µs
60pF
ACSA = 5 V/V, CLOAD = 60-pF, small
3 5 7 MHz
signal -3 dB
ACSA = 10 V/V, CLOAD = 60-pF, small
2.5 4.8 6.6 MHz
signal -3 dB
BW Bandwidth
ACSA = 20 V/V, CLOAD = 60-pF, small
2 4 5.4 MHz
signal -3 dB
ACSA = 40 V/V, CLOAD = 60-pF, small
1.75 3 4.2 MHz
signal -3 dB
VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD =
12 V/µs
60-pF, low to high transition
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD =
13 V/µs
60-pF, low to high transition
tSR Output slew rate
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD =
11 V/µs
60-pF, low to high transition
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD =
11 V/µs
60-pF, low to high transition
VSWING Output voltage range VCSAREF = 3 0.25 2.75 V
VSWING Output voltage range VCSAREF = 5.5 0.25 5.25 V
VCSAREF
VSWING Output voltage range VCSAREF = 3 to 5.5 V 0.25 V
- 0.25
VCOM Common-mode input range -0.15 0.15 V
VDIFF Differential-mode input range -0.3 0.3 V
VSP = VSN = GND; TJ = -40℃,
VOFF Input offset voltage -2.0 2.0 mV
CSA_VREF = 0
VSP = VSN = GND; TJ = 25℃,
VOFF Input offset voltage -1.9 1.9 mV
CSA_VREF = 0
VSP = VSN = GND; TJ = 175℃,
VOFF Input offset voltage -2.0 2.0 mV
CSA_VREF= 0
VOFF Input offset voltage VSP = VSN = GND -2.0 2.0 mV
VOFF_DRIFT Input drift offset voltage VSP = VSN = GND 8 µV/℃
VBIAS Output voltage bias ratio VSP = VSN = GND 0.122 0.125 0.128 V
VBIAS_ACC Output voltage bias ratio accuracy VSP = VSN = GND -1.2 1.2 %
VSP = VSN = GND, VCSAREF = 3V to
IBIAS Input bias current 100 µA
5.5V
IBIAS_OFF Input bias current offset ISP – ISN -1 1 µA
ICSASRC SO ouput sink current capability 5 7 11 mA

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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICSASRC SO ouput source current capability 2 3.7 6.6 mA
DC 80 dB
CMRR Common-mode rejection ratio
20 kHz 65 dB
CSAREF to SOx, DC, Differential 80 dB
PSRR Power-supply rejection ratio (CSAREF)
CSAREF to SOx, 20 kHz, Differential 70 dB
PSRR Power-supply rejection ratio (CSAREF) CSAREF to SOx, 20 kHz, Single Ended 40 dB
ICSA_SUP Supply current for CSA VCSAREF = 3.V to 5.5V 1.5 2.1 mA
TCMREC Common mode recovery time 0.6 0.7 us
CLOAD Maximum load capacitance 10 nF
ACSA = 5 V/V -3 3 mV
ACSA = 10 V/V -4 4 mV
VOFF_OUT Output offset error
ACSA = 20 V/V -5 5 mV
ACSA = 40 V/V -6 6 mV
PROTECTION CIRCUITS
VPVDD rising 4.3 4.4 4.5
VPVDD_UV PVDD undervoltage lockout threshold V
VPVDD falling 4 4.1 4.25
VPVDD_UV_H
PVDD undervoltagelockout hysteresis Rising to falling threshold 225 265 325 mV
YS

tPVDD_UV_DG PVDD undervoltage deglitch time 10 20 30 µs

AVDD rising 2.7 2.85 3.0
VAVDD_POR AVDD supply POR threshold V
AVDD falling 2.5 2.65 2.8
VAVDD_POR_
AVDD POR hysteresis Rising to falling threshold 170 200 250 mV
HYS

tAVDD_POR_D
AVDD POR deglitch time 7 12 22 µs
G

VGVDD rising 7.3 7.5 7.8 V

VGVDD_UV GVDD undervoltage threshold
VGVDD falling 6.4 6.7 6.9 V
VGVDD_UV_H
GVDD undervoltage hysteresis Rising to falling threshold 800 900 1000 mV
YS

tGVDD_UV_DG GVDD undervoltage deglitch time 5 10 15 µs

VBSTx- VSHx; VBSTx rising 3.9 4.45 5 V
VBST_UV Bootstrap undervoltage threshold
VBSTx- VSHx; VBSTx falling 3.7 4.2 4.8 V
VBST_UV_HYS Bootstrap undervoltage hysteresis Rising to falling threshold 150 220 285 mV
tBST_UV_DG Bootstrap undervoltage deglitch time 2 4 6 µs
VDS overcurrent protection threshold
VDS_LVL_RNG 0.1 2.5 V
linear range
VDS overcurrent protection disable
VDS_DIS VDSLVL pin to GVDD 70 100 500 kΩ
resistor
VDSLVL = 100 kΩ to GVDD 3 4.2 5.5 V
VDS overcurrent protection threshold
VDS_LVL VDSLVL = 0.1V 0.065 0.1 0.145
Reference V
VDSLVL pin = 2.5V 2.2 2.5 2.8
VSENSE_LVL VSENSE overcurrent protection threshold LSS to GND pin = 0.5V 0.48 0.5 0.52 V
tDS_BLK VDS overcurrent protection blanking time 0.5 1 2.7 µs
VDS and VSENSE overcurrent protection
tDS_DG 1.5 3 5 µs
deglitch time
tSD_SINK_DIG DRVOFF peak sink current duration 3 5 7 µs
tSD_DIG DRVOFF digital shutdown delay 0.5 1.5 2.2 µs

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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSD DRVOFF analog shutdown delay 7 14 21 µs
TOTSD Thermal shutdown temperature TJ rising; 160 170 187 °C
THYS Thermal shutdown hysteresis 16 20 23 °C

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6.6 Typical Characteristics

8.5 14
8.25 -40 C 13.5
8 25 C
150 C 13
7.75
12.5
7.5
Active Current (mA)

GVDD Voltage (V)

7.25 12
7 11.5
6.75 11
6.5 10.5
6.25 10
6
9.5
5.75
9 -40 C
5.5 25 C
5.25 8.5 150 C
5 8
0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60
PVDD Voltage (V) PVDD Voltage (V)

Figure 6-1. Supply Current over PVDD Voltage Figure 6-2. GVDD Voltage over PVDD Voltage
3.34 2500
-40 C High Side Source
3.33 25 C High Side Sink
2250
150 C Low Side Source
3.32 Low Side Sink
2000

Peak Current (mA)

AVDD Voltage (V)

3.31

3.3 1750

3.29
1500
3.28
1250
3.27

3.26 1000

3.25 750
0 8 16 24 32 40 48 56 64 72 80 -40 -20 0 20 40 60 80 100 120 140
Load Current (mA)
Junction Temperature (C)
Figure 6-3. AVDD Voltage over Load Current Figure 6-4. Driver Peak Current over Junction
Temperature
9 0.65
Bootstrap Diode Forward Voltage Drop (V)

8.75
0.625
8.5
Bootstrap Diode Resistance ()

8.25 0.6
8 0.575
7.75
0.55
7.5
7.25 0.525
7 0.5
6.75
0.475
6.5
6.25 0.45
6
0.425
5.75
5.5 0.4
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Junction Temperature () Junction Temperature (C)

Figure 6-5. Bootstrap Diode Resistance over Figure 6-6. Bootstrap Diode Forward Voltage Drop
Junction Temperature over Junction Temperature

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7 Detailed Description
7.1 Overview
The DRV8329-Q1 family of devices is an integrated three-phase gate driver supporting an input voltage range
of 4.5-V to 60-V. These devices decrease system component count, cost, and complexity by integrating three
independent half-bridge gate drivers, trickle charge pump, and a charge pump with linear regulator for the
supply voltages of the high-side and low-side gate drivers. DRV8329-Q1 also integrates an accurate low
voltage regulator (AVDD) capable of supporting 3.3 V at 80 mA output. A hardware interface allows for simple
configuration of the motor driver and control of the motor.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak gate drive currents with a 30-mA average output current. A bootstrap circuit with capacitor
generates the supply voltage of the high-side gate drive and a trickle charge pump is employed to support 100%
duty cycle. The supply voltage of the low-side gate driver is generated using a charge pump with linear regulator
GVDD from the PVDD power supply that regulates to 12 V.
In addition to the high level of device integration, the DRV8329-Q1 family of devices provides a wide range of
integrated protection features. These features include power supply undervoltage lockout (PVDDUV), regulator
undervoltage lockout (GVDDUV), Bootstrap Voltage undervoltage lockout (BSTUV), VDS overcurrent monitoring
(OCP), Sense resistor overcurrent monitoring (SEN_OCP) and overtemperature shutdown (TSD). Fault events
are indicated by the nFAULT pin.
The DRV8329-Q1 is available in 0.5-mm pitch, 5 × 7 mm 40-pin QFN surface-mount packages.

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7.2 Functional Block Diagram

PVDD

+
0.1 μF bulk
CPVDD1 CPVDD2

GVDD Power PVDD

CGVDD GVDD Trickle
10 μF CP
BSTA

VCP CBSTA
CPH
Charge HS GHA
CCP HS
Pump
470 nF
CPL
SHA
GVDD

LS GLA
80 mA AVDD LS
3.3-V LDO
CAVDD LSS
AGND
1 μF
GVDD Trickle
CP
nSLEEP BSTB PVDD
CBSTB
HS GHB
HS
INHA
SHB
INLA GVDD

LS GLB
INHB LS
Digital
Control Control LSS
INLB Inputs
GVDD Trickle
+
CP PVDD
INHC - BSTC
CBSTC
INLC HS GHC
HS

SHC
GVDD
DT
LS GLC
LS
RDT AVDD

RnFAULT LSS
DRVOFF
nFAULT Outputs

LSS

LSS
+
-
0.5V

VDSLVL 3x LS, 3x HS VSENSE OCP

-

VDS +
CSAGAIN SP
CSAREF

SO - SP
VCSAREF/8 + - SN RSENSE
+
CSAREF -
CSA SN
+

GND

Thermal Pad

Figure 7-1. Block Diagram of DRV8329

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7.3 Feature Description

Table 7-1 lists the recommended values of the external components for the gate driver and the buck regulator.
Table 7-1. DRV8329-Q1 External Components
COMPONENTS PIN 1 PIN 2 RECOMMENDED
CPVDD1 PVDD PGND X5R or X7R, 0.1-µF, >2x PVDD-rated capacitor
CPVDD2 PVDD PGND ≥ 10 µF, >2x PVDD-rated capacitor
CCP CPH CPL X5R or X7R, 470-nF, PVDD-rated capacitor
CGVDD GVDD GND X5R or X7R, ≥10-uF, 25V-rated capacitor
CAVDD AVDD AGND X5R or X7R, ≥1-µF, 6.3-V capacitor
CBSTx BSTx SHx X5R or X7R, 1-µF (typical), 25V-rated capacitor
RnFAULT VCC(1) nFAULT Pullup resistor (10 kΩ)
Hardware interface resistor. Refer to Deadtime and
RDT DT AGND
Cross-Conduction Prevention for the details.

(1) The VCC pin is not a pin on the DRV8329-Q1 , but a VCC supply voltage pullup is required for the open-drain output, nFAULT. This pin
can also be pulled up to AVDD.

7.3.1 Three BLDC Gate Drivers

The DRV8329-Q1 family of devices integrates three half-bridge gate drivers, each capable of driving high-side
and low-side N-channel power MOSFETs. A charge pump is used to generate the GVDD to supply the correct
gate bias voltage across a wide operating voltage range. The low side gate outputs are driven directly from
GVDD, while the high side gate outputs are driven using a bootstrap circuit with an integrated diode. An internal
trickle charge pump provides support for 100% duty cycle operation. The half-bridge gate drivers can be used in
combination to drive a three-phase motor or separately to drive other types of loads.
7.3.1.1 PWM Control Modes

7.3.1.1.1 6x PWM Mode

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 7-2.
Table 7-2. 6x PWM Mode Truth Table
INLx INHx GLx GHx SHx
0 0 L L Hi-Z
0 1 L H H
1 0 H L L
1 1 L L Hi-Z

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7.3.1.1.2 3x PWM Mode

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 7-3.
Table 7-3. 3x PWM Mode Truth Table
INLx INHx GLx GHx SHx
0 X L L Hi-Z
1 0 H L L
1 1 L H H

7.3.1.2 Device Hardware Interface

The DRV8329-Q1 utilize a hardware interface to configure different device settings. These hardware
configurable inputs are DT and VDSLVL. General fault information is reported on the nFAULT pin.
• The DT pin configures the gate drive dead time. The dead time can adjusted by changing the resistor value
from the DT pin to GND.
• The VDSLVL pin configures the voltage threshold of the VDS overcurrent monitors. The voltage applied to the
VDSLVL pin is directly used as reference for the VDS comparator
For more information on the hardware interface, see Section 7.3.3.

VDSLVL

Hardware
Interface

DT

RDT

Figure 7-2. Hardware Interface

7.3.1.3 Gate Drive Architecture

The gate driver device use a complimentary, push-pull topology for both the high-side and low-side drivers. This
topology allows for both a strong pullup and pulldown of the external MOSFET gates. The low side gate drivers
are supplied directly from the GVDD regulator supply. The operating mode of GVDD depends on the voltage of
PVDD, when the PVDD >18V, the GVDD voltage is generated by an LDO, whereas PVDD < 18V, the GVDD
voltage is generated by a charge pump. For the high-side gate drivers a bootstrap diode and capacitor are
used to generate the floating high-side gate voltage supply. The bootstrap diode is integrated and an external
bootstrap capacitor is used between BSTx and SHx pins. To support 100% duty cycle control, a trickle charge
pump is integrated into the device. The trickle charge pump is connected to the BSTx node to prevent voltage
drop due to the leakage currents of the driver and external MOSFET.
The high-side gate driver has a semi-active pulldown and low side gate has passive pulldown to help prevent the
external MOSFET from turning ON during sleep state or when the power supply is disconnected.

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CGVDD

GVDD

PVDD
Trickle
CPVDD2 CPVDD1 Charge
Pump

CPH Charge DBSTx

Pump VBAT
CCP
BSTx
CPL
CBSTx

INHx Level GHx

Shifters

Semi-active
pull-down

RPDSA_HS
INLx SHx
Digital
Core
GVDD

GLx
Level
Shifters

RPD_LS
LSS

GND

GND

Figure 7-3. Gate Driver Block Diagram

7.3.1.3.1 Propagation Delay

The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the digital propagation delay, and the delay through the analog
gate drivers.
To support multiple control modes and dead time insertion, a small digital delay is added as the input command
propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall
propagation delay of the device.
7.3.1.3.2 Deadtime and Cross-Conduction Prevention
In the DRV8329-Q1, high- and low-side inputs operate independently, with an exception to prevent cross
conduction when the high and low side of the same half-bridge are turned ON at same time. The device turns
OFF high- and low- side output to prevent shoot through when high- and low-side inputs are logic high at same
time.
The DRV8329-Q1 also provides dead time insertion to prevent both external MOSFETs of each half-bridge from
switching on at the same time. In devices with a DT pin, deadtime can be linearly adjusted between 100 ns and
2000 ns by connecting s resistor between DT and ground. When the DT pin is left floating or connected to GND,
a fixed deadtime of 55 ns (typical value) is inserted. The value of the resistor can be calculated using following
equation.

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Deadtime ns
RDT kΩ = 5 − 10 kΩ (1)

INHx/INLx Inputs

INHx

INLx

GHx/GLx outputs

GHx

GLx

DT DT

Cross
Conduction
Prevention

Figure 7-4. Cross Conduction Prevention and Deadtime Insertion

7.3.2 AVDD Linear Voltage Regulator

A 3.3-V, 80-mA linear regulator is available for use by external circuitry. The output of the LDO is fixed to 3.3-V.
This regulator can provide the supply voltage for a low-power MCU or other circuitry with low supply current
needs. The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V
ceramic capacitor routed back to the AGND pin.
PVDD

REF +
± AVDD 3.3-V, 80 mA

1 …F
AGND

Figure 7-5. AVDD Linear Regulator Block Diagram

The power dissipated in the device by the AVDD linear regulator can be calculated as follows: P = (VPVDD-
VAVDD) x IAVDD
For example, at a VPVDD of 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in
Equation 2.

P 24 V 3.3 V u 20 mA 414 mW (2)

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7.3.3 Pin Diagrams

Figure 7-6 shows the input structure for the logic level pins, INHx and INLx. The input can be driven with a
voltage or external resistor.

AVDD

STATE RESISTANCE INPUT

VIH Tied to AVDD Logic High

VIL Tied to AGND Logic Low

RPD

Figure 7-6. Logic-Level Input Pin Structure

Figure 7-7 shows the structure of the four level input pins, MODE and CSAGAIN, on hardware interface devices.
The input can be set with an external resistor.

GAIN

AVDD AVDD AVDD

STATE RESISTANCE 5 V/V
+
VL1 Tied to AGND
RPU –
50k
±5% tied to 10 V/V
VL2
AGND
+
200k ±5% tied to RPD
VL3
AGND –
Hi-Z or connect to 20 V/V
VL4
AVDD +

–
40 V/V

Figure 7-7. Four Level Input Pin Structure

Figure 7-8 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external
pullup resistor to function correctly.

AVDD

STATE STATUS RPU

No Fault Inactive OUTPUT

Fault Active Active

Inactive

Figure 7-8. Open-Drain Output Pin Structure

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7.3.4 Low-Side Current Sense Amplifiers

The DRV8329 integrates a high-performance low-side current sense amplifier for current measurements using
a low-side shunt resistor. Low-side current measurements are commonly used to implement overcurrent
protection, external torque control, or brushless DC commutation with the external controller. The current
sense amplifier can be used to sense the sum of the half-bridge currents. The current sense amplifiers
includes features such as configurable gain (CSAGAIN), and a voltage reference pin (CSAREF). The DRV8329
generates internally a common voltage of VCSAREF/8.
The gain setting is adjustable between four different levels (5 V/V, 10 V/V, 20 V/V, and 40 V/V). Gain settings can
be configured through CSAGAIN pin.
Table 7-4. CSA Gain setting
CSAGAIN pin CSA Gain Setting
Connect to GND 5 V/V
50 kΩ +/- 5% to GND 10 V/V
200 kΩ +/- 5% to GND 20 V/V
HiZ or Connect to AVDD 40 V/V

7.3.4.1 Current Sense Operation

DRV8329 internally generates a common mode voltage of VCSAREF/8 to obtain maximum resolution for current
measurement. SO pin outputs an analog voltage equal to the voltage across the SP and SN pins multiplied by
the gain setting (CSAGAIN).
Use Equation 3 to calculate the current through the shunt resistor (RSENSE).

V
VSO − CSAREF
I = CSAGAIN × R8 (3)
SENSE

50 k

100 k

200 k

400 k
SN
CSAREF
10 k

SO -
10 k
+ SP

CSAREF
50 k

100 k
-
200 k
VCSAREF/8 +
400 k

GND

Figure 7-9. Current-Sense Configuration

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SO (V)

VCSAREF

VCSAREF – 0.25V

VLINEAR

VCSAREF /8

0.25 V

VSP – VSN

Figure 7-10. Current-Sense Output

I

SP
SO R
AV

SN

SO
VCSAREF
VSP – VSN
0.3 V
VCSAREF – 0.25V

I × RSENSE

VSO(range+)

VOFF,
VSO(off)max VDRIFT
VCSAREF/8 0V
VSO(off)min
VSO(range-) -I × RSENSE

0.25 V -0.3 V

0V

Figure 7-11. Current-Sense Regions

7.3.5 Gate Driver Shutdown Sequence (DRVOFF)

When DRVOFF is driven high, the gate driver goes into shutdown, overriding signals on inputs pins INHx and
INLx. DRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver
output (see Figure 7-12). This pin provides a mechanism for externally monitored faults to disable the gate driver
by directly bypassing an external controller or the internal control logic. When the DRV8329-Q1 detects that the
DRVOFF pin is driven high, it disables the gate driver and puts it into pulldown mode (see Figure 7-13). The
gate driver shutdown sequence proceeds as shown in Figure 7-13. When the gate driver initiates the shutdown
sequence, the active driver pulldown is applied at ISINK current for the tSD_SINK_DIG time, after which the gate
driver moves to passive pulldown mode.

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PVDD

OFF

DRVOFF
GHA OFF

GHB
OFF
A
GHC
Gate B
Digital Driver
OFF
C
GLA
OFF
GLB
OFF
GLC

GND

Figure 7-12. DRV8329-Q1 DRVOFF Gate Driver Output State

High
INHx (INLx)

GHx-SHx
(GLx-LSS)
tSD_DIG

DRVOFF pin
tSD_SINK_DIG

tSD

Predriver Passive (RPD_LS) and Semiactive

ISOURCE/ISINK ISINK PullDown (RPDSA_HS)
Current

Figure 7-13. Gate Driver Shutdown Seqeunce

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7.3.6 Gate Driver Protective Circuits

The DRV8329-Q1 are protected against PVDD undervoltage and overvoltage, AVDD power-on reset, bootstrap
undervoltage, GVDD undervoltage, MOSFET VDS and VSENSE overcurrent events.
Table 7-5. Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT GATE DRIVER LOGIC RECOVERY
PVDD
Automatic:
undervoltage VPVDD < VPVDD_UV - nFAULT Disabled1 Disabled
VPVDD > VPVDD_UV
(PVDD_UV)
AVDD POR Automatic:
VAVDD < VAVDD_POR - nFAULT Disabled1 Disabled
(AVDD_POR) VAVDD > VAVDD_POR
GVDD
Latched:
undervoltage VGVDD < VGVDD_UV - nFAULT Pulled Low 2 Active
nSLEEP Reset Pulse
(GVDD_UV)
BSTx
VBSTx - VSHx < VBST_UV and Latched:
undervoltage - nFAULT Pulled Low 2 Active
INHx = High nSLEEP Reset Pulse
(BST_UV)
Latched:
0.1V < VVDSLVL < 2.5V nFAULT Pulled Low 2 Active
VDS overcurrent nSLEEP Reset Pulse
VDS > VDS_LVL
(VDS_OCP) VDSLVL pin 100kΩ
None Active Active No action
tied to GVDD
Latched:
VSENSE - nFAULT Pulled Low 2 Active
nSLEEP Reset Pulse
overcurrent VSP > VSENSE_LVL
(SEN_OCP) VDSLVL pin 100kΩ
None Active Active No action
tied to GVDD
Thermal
Latched:
shutdown TJ > TOTSD - nFAULT Pulled Low 2 Active
nSLEEP Reset Pulse
(OTSD)

1. Disabled: Passive pull down for GLx and semiactive pull down for GHx
2. Pulled Low: GHx and GLx are actively pulled low by the gate driver
7.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
If at any time the power supply voltage on the PVDD pin falls below the VPVDD_UV threshold for longer than the
tPVDD_UV_DG time, the device detects a PVDD undervoltage event. After detecting the undervoltage condition, the
gate driver is disabled, the charge pump is disabled, the internal digital logic is disabled, and the nFAULT pin is
driven low. Normal operation starts again (the gate driver becomes operable and the nFAULT pin is released)
when the PVDD pin rises above VPVDD_UV.
7.3.6.2 AVDD Power on Reset (AVDD_POR)
If at any time the supply voltage on the AVDD pin falls below the VAVDD_POR threshold for longer than the
tAVDD_POR_DG time, the device enters an inactive state, disabling the gate driver, the charge pump, and the
internal digital logic, and nFAULT is driven low. Normal operation (digital logic operational) requires nSLEEP to
be asserted high and AVDD to exceed VAVDD_POR level.
7.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
If at any time the voltage on the GVDD pin falls lower than the VGVDD_UV threshold voltage for longer than the
tGVDD_UV_DG time, the device detects a GVDD undervoltage event. After detecting the GVDD_UV undervoltage
event, all of the gate driver outputs are driven low to disable the external MOSFETs, the charge pump is disabled
and nFAULT pin is driven low. After the GVDD_UV condition is cleared, the fault state remains latched and can
be cleared through an nSLEEP pin reset pulse (tRST)

Note
After the GVDD_UV fault is cleared through an nSLEEP pin reset pulse, the nFAULT pin is held low
until the GVDD capacitor is refreshed by the charge pump. After the GVDD capacitor is charged, the
nFAULT pin is automatically released. The duration that the nFAULT pin is low after the fault is cleared
will not exceed tWAKE time.

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7.3.6.4 BST Undervoltage Lockout (BST_UV)

If at any time the voltage across BSTx and SHx pins falls lower than the VBST_UV threshold voltage for longer
than the tBST_UV_DG time, the device detects a BST undervoltage event. Afer detecting the BST_UV event, all of
the gate driver outputs are driven low to disable the external MOSFETs, and nFAULT pin is driven low. After the
BST_UV condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset
pulse (tRST).
7.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
The device has adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external
power MOSFETs. A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the
external MOSFET RDS(on). The high-side VDS monitors measure between the PVDD and SHx pins and the low-
side VDS monitors measure between the SHx and LSS pins. If the voltage across external MOSFET exceeds
the VDS_LVL threshold for longer than the tDS_DG deglitch time, a VDS_OCP event is recognized. Afer detecting
the VDS overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and
nFAULT pin is driven low. The VDS threshold can be set between 0.1 V to 2.5 V by applying a voltage on the
VDSLVL pin. VDS OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor. After the
VDS_OCP condition is cleared, the fault state remains latched and can be cleared through the nSLEEP pin reset
pulse (tRST).
PVDD
PVDD
+
+ VDS
VDS –
– VVDS_OCP
GHx

SHx
+
+ VDS
VDS –
– VVDS_OCP GLx

LSS

GND

Figure 7-14. DRV8329-Q1 VDS Monitors

7.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)

Overcurrent is also monitored by sensing the voltage drop across the external current sense resistor between
the LSS and GND pins. If at any time the voltage on the LSS input exceeds the VSEN_OCP threshold for longer
than the tDS_DEG deglitch time, a SEN_OCP event is recognized. Afer detecting the SEN_OCP overcurrent
event, all of the gate driver outputs are driven low to disable the external MOSFETs and the nFAULT pin is
driven low. The VSENSE threshold is fixed at 0.5 V and deglitch time is fixed to 3 µs. After the SEN_OCP
condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset pulse
(tRST). SEN_OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor.
7.3.6.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), an OTSD event is recognized.
After detecting the OTSD overtemperature event, all of the gate driver outputs are driven low to disable the
external MOSFETs, charge pump is disabled and nFAULT pin is driven low. After OTSD condition is cleared, the
fault state remains latched and can be cleared through an nSLEEP pin reset pulse (tRST)

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7.4 Device Functional Modes

7.4.1 Gate Driver Functional Modes
7.4.1.1 Sleep Mode
The nSLEEP pin manages the state of the DRV8329-Q1. When the nSLEEP pin is low, the device goes to a
low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
GVDD regulator is disabled and the AVDD regulator is disabled. The tSLEEP time must elapse after a falling edge
on the nSLEEP pin before the device goes to sleep mode. The device comes out of sleep mode automatically if
the nSLEEP pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.

Note
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held
low as the internal regulators are not active. After the regulators have been active, the nFAULT pin is
automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or tWAKE
time.

7.4.1.2 Operating Mode

When the nSLEEP pin is high and the VPVDD voltage is greater than the VPVDD_UV voltage, the device goes
to operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the GVDD
regulator and AVDD regulator are active.
7.4.1.3 Fault Reset (nSLEEP Reset Pulse)
In the case of device latched faults, the DRV8329-Q1 goes into a partial shutdown state to help protect the
external power MOSFETs and system.

Note
If the user wants to put the device into sleep state after latched fault event, the inputs INHx and INLx
needs to be pulled low prior to driving the nSLEEP pin. If the inputs INHx and INLx are not driven low,
then the fault is reset after nSLEEP is driven low for the tRST time and there can be pulses on gate
driver outputs GHx and GLx prior to device entering sleep. The duration of pulses on GHx and GLx
can be of duration tSLEEP if INHx and INLx are not pulled low.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The DRV8329-Q1 family of devices is primarily used in applications for three-phase brushless DC motor control.
The design procedures in the Section 8.2 section highlight how to use and configure the DRV8329-Q1 family of
devices.
8.2 Typical Application
8.2.1 Three Phase Brushless-DC Motor Control
In this application, the DRV8329-Q1 is used to drive a three-phase Brushless-DC motor.

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PVDD

GVDD PVDD
>10 uF 0.1 uF >10 uF

PVDD
CPH
470 nF BSTA CBSTA
RGHA
CPL GHA

AVDD SHA
>1uF
AVDD RGLA
GLA
DRV8329
INHA

INLA
PVDD
BSTB CBSTB
INHB
PWM RGHB
INLB GHB
MCU
INHC SHB

INLC RGLB
GLB

DRVOFF
I/O
nSLEEP
ADC

Analog Input PVDD

(0.1 to 2.5V) BSTC
VDSLVL CBSTC

AVDD
RGHC
GHC
RnFAULT

SHC
nFAULT
RGLC
GLC
DT
RDT

LSS

SP
SO
– SN
RSENSE

SO
AVDD SP
+

CSAREF SN

GND

Figure 8-1. DRV8329-Q1 Application Diagram

8.2.1.1 Detailed Design Procedure

Section 8.2.1.1 lists the example input parameters for the system design.
Table 8-1. Design parameters
DESIGN PARAMETERS REFERENCE EXAMPLE VALUE

Supply voltage VPVDD 24 V

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Table 8-1. Design parameters (continued)

DESIGN PARAMETERS REFERENCE EXAMPLE VALUE

Motor peak current IPEAK 20 A

PWM Frequency fPWM 20 kHz

MOSFET VDS Slew Rate SR 120 V/us

MOSFET input gate capacitance QG 54 nC

MOSFET input gate capacitance QGD 14 nC

Dead time tdead 200 ns

Overcurrent protection IOCP 30 A

8.2.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 18-V, 24-V or 36-V). The DRV8329-
Q1 allows for a range of possible operating voltages from 4.5-V to 60-V.
8.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. Equation 4 calculates the maximum allowable voltage drop across the bootstrap capacitor:

¿8$56: = 8)8&& F 8$116& F 8$5678 (4)

=12 V – 0.85 V – 4.45 V = 6.7 V

where
• VGVDD is the supply voltage of the gate drive
• VBOOTD is the forward voltage drop of the bootstrap diode
• VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.7 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.
The total charge needed per switching cycle can be estimated with Equation 5:

ILBS_TRAN
QTOT = QG + fSW (5)

=54 nC + 115 μA/20 kHz = 54 nC + 5.8 nC = 59.8nC

where
• QG is the total MOSFET gate charge
• ILBS_TRAN is the bootstrap pin leakage current
• fSW is the is the PWM frequency
The minimum bootstrap capacitor can then be estimated as below assuming 1V of ΔVBSTx:

%$56_/+0 = 3616W¿8
$56: (6)

= 59.8 nC / 1 V = 59.8 nF
The calculated value of minimum bootstrap capacitor is 59.8 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater
than calculated value to allow for situations where the power stage may skip pulse due to various transient

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conditions. It is recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to
include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.

%)8&& R 10 × %$56: (7)

= 10*100 nF= 1 μF
For this example application, choose a 1-µF CGVDD capacitor. Choose a capacitor with a voltage rating at
least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant
capacitance when biased. This value also improves the long-term reliability of the system.

Note
For higher power system requiring 100% duty cycle support for longer duration it is recommended to
use CBSTx of ≥1μF and CGVDD of ≥10 μF.

8.2.1.1.3 Gate Drive Current

Selecting an appropriate gate drive current is essential when turning on or off power MOSFETs gates to
switch motor current. The amount of gate drive current and input capacitance of the MOSFETs determines the
drain-to-source voltage slew rate (VDS). Gate drive current can be sourced from GVDD into the MOSFET gate
(ISOURCE) or sunk from the MOSFET gate into SHx or LSS (ISINK).
Using too high of a gate drive current can turn on MOSFETs too quickly which may cause excessive ringing,
dV/dt coupling, or cross-conduction from switching large amounts of current. If parasitic inductances and
capacitances exist in the system, voltage spiking or ringing may occur which can damage the MOSFETs or
DRV8329-Q1 device.
PVDD

PVDD
VINHx VGHx
GVDD
I
INHx HS GHx
HS VDS

SHx
PHASE
CGD
VGLx
GVDD
INLx LS GLx
LS

LSS

Figure 8-2. Effects of high gate drive current

On the other hand, using too low of a gate drive current causes long VDS slew rates. Turning on the MOSFETs
too slowly may heat up the MOSFETs due to RDS,on switching losses.

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The relationship between gate drive current IGATE, MOSFET gate-to-drain charge QGD, and VDS slew rate
switching time trise,fall are described by the following equations:

V
SRDS = t DS (8)
rise, fall

Qgd
IGATE = t (9)
rise, fall

It is recommend to evaluate at lower gate drive currents and increase gate drive current settings to avoid
damage from unintended operation during initial evaluation.
8.2.1.1.4 Gate Resistor Selection
The slew rate of the SHx connection will be dependent on the rate at which the gate of the external MOSFETs
is controlled. The pull-up/pull-down strength of the DRV8329-Q1 is fixed internally, hence the slew rate of gate
voltage can be controlled with an external series gate resistor. In some applications, the gate charge of the
MOSFET, which is the load on gate driver device, is significantly larger than the gate driver peak output current
capability. In such applications, external gate resistors can limit the peak output current of the gate driver.
External gate resistors are also used to dampen ringing and noise.
The specific parameters of the MOSFET, system voltage, and board parasitics will all affect the final SHx slew
rate, so generally selecting an optimal value or configuration of external gate resistor is an iterative process.
To lower the gate drive current, a series resistor RGATE can be placed on the gate drive outputs to control the
current for the source and sink current paths. A single gate resistor will have the same gate path for source and
sink gate current, so larger RGATE values will yield similar SHx slew rates. Note that gate drive current varies by
PVDD voltage, junction temperature, and process variation of the device. Gate resistor values can be estimated
with +/-30% accuracy using the Gate Resistor Calculator.
PVDD

PVDD

GVDD
RGATE
INHx HS GHx
HS

SHx

GVDD
RGATE
INLx LS GLx
LS

LSS RSINK

Figure 8-3. Gate driver outputs with series resistors

Typically, it is recommended to have the sink current be twice the source current to implement a strong pulldown
from gate to the source to ensure the MOSFET stays off while the opposite FET is switching. This can be
implemented discretely by providing a separate path through a resistor for the source and sink currents by

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placing a diode and sink resistor (RSINK) in parallel to the source resistor (RSOURCE). Using the same value of
source and sink resistors results in half the equivalent resistance for the sink path. This yields twice the gate
drive sink current compared to the source current, and SHx will slew twice as fast when turning off the MOSFET.
PVDD

PVDD

GVDD
RSOURCE
INHx HS GHx
HS

SHx RSINK

GVDD
RSOURCE
INLx LS GLx
LS

LSS RSINK

Figure 8-4. Gate driver outputs with separate source and sink current paths

8.2.1.1.5 System Considerations in High Power Designs

Higher power system designs can require design and application considerations that are not regarded in lower
power system designs. It is important to combat the volatile nature of higher power systems by implementing
troubleshooting guidelines, external components and circuits, driver product features, or layout techniques. For
more information, please visit the System Design Considerations for High-Power Motor Driver Applications
application note.
8.2.1.1.5.1 Capacitor Voltage Ratings
Use capacitors with voltage ratings that are 2x the supply voltage (PVDD, GVDD, AVDD, etc). Capacitors can
experience up to half the rated capacitance due to poor DC voltage rating performance.
For example, since the bootstrap voltage is around 12 to 13-V with respect to SHx (BSTx-SHx) then the
BSTx-SHx capacitor should be rated for 25-V or greater.
8.2.1.1.5.2 External Power Stage Components
External components in the power stage are not required by design but are helpful in suppressing transients,
managing inductor coil energy, mitigating supply pumping, dampening phase ringing, or providing strong gate-to-
source pulldown paths. These components are used for system tuning and debuggability so the BLDC motor
system is robust while avoiding damage to the DRV8329-Q1 device or external MOSFETs.
Figure 8-5 shows examples of power stage components that can be optimally placed in the design.

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PVDD

PVDD

GVDD
RSOURCE RPD CBULK RSNUB
INHx HS GHx
HS

SHx RSINK CSNUB

PHASE
CHSD_LSS

CSNUB
GVDD
RSOURCE RPD
INLx LS GLx
LS
RSNUB
DGS
LSS RSINK

Figure 8-5. Optional external power stage components

Some examples of issues and external components that can resolve those issues are found in Table 8-2:
Table 8-2. Common issues and resolutions for power stage debugging
Issue Resolution Component(s)

Gate drive current required is too large, Series resistors required for gate drive 0-100 Ω series resistors (RGATE/RSOURCE)
resulting in very fast MOSFET VDS slew rate current adjustability at gate driver outputs (GHx/GLx), optional
sink resistor (RSINK) and diode in parallel
with gate resistor for adjustable sink current

Ringing at phase’s switch node (SHx) RC snubbers placed in parallel to each Resistor (RSNUB) and Capacitor (CSNUB)
resulting in high EMI emissions HS/LS MOSFET to dampen oscillations placed parallel to the MOSFET, calculate
RC values based on ringing frequency using
Proper RC Snubber Design for Motor Drivers

Negative transients at low-side source (LSS) HS drain to LS source capacitor to suppress 0.01uF-1uF, VM-rated capacitor from
below minimum specification negative bouncing PVDD-LSS (CHSD_LSS) placed near LS
MOSFET’s source

Negative transient at low-side gate (GLx) Gate-to-ground Zener diode to clamp GVDD voltage rated Zener diode (DGS)
below minimum specification negative voltage with anode connected to GND and cathode
connected to GLx

Extra protection required to ensure MOSFET External gate-to-source pulldown resistors 10 kΩ to 100 kΩ resistor (RPD) connected
is turned off if gate drive signals are Hi-Z (after series gate resistors) from gate to source for each MOSFET

8.2.1.1.5.3 Parallel MOSFET Configuration

If higher MOSFET continuous drain current ratings are required for the motor, parallel MOSFETs can be used for
higher current capability. However, this requires special schematic and layout design requirements to switch both
MOSFETs simultaneously because one MOSFET may turn on faster than the other due to process variation.
It is recommended to place the MOSFETs close together with a common gate signal that splits as close as
possible to the MOSFETs gates. If gate resistance is required, calculate the equivalent resistance required for
the equivalently rated MOSFET, and place the gate resistors as close as possible to the MOSFET’s gate input to
dampen any coupling into the gate driver.

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For more information, please visit the Driving Parallel MOSFETs application brief.
8.2.1.1.6 Dead Time Resistor Selection
Dead time insertion is available in the DRV8329-Q1 via a resistor (RDT) from the DT pin to ground as shown in
Figure 8-6. The ranges of dead time in the DRV8329-Q1 is 100 ns to 2000 ns when RDT is tied to GND from the
DT pin. A linear interpolation of the resistance value is used to set the appropriate dead time.
RDT
DT

Figure 8-6. Dead time resistor

Dead time (in nanoseconds) can be calculated from the dead time resistor calculation in Equation 1.
Dead time can also be implemented from the PWM inputs generated by an MCU. If dead time is inserted at
the PWM inputs and the DRV8329-Q1, then the driver output PWM dead time is the larger of the two dead
times. For instance, if 200 ns dead time is inserted at the MCU inputs and 50 ns dead time is inserted in the
DRV8329-Q1 via the DT pin, then the output driver PWM dead time will be 200 ns.
8.2.1.1.7 VDSLVL Selection
VDSLVL is an analog voltage used to directly set the VDS overcurrent threshold for overcurrent protection. It can
be sourced directly from an analog voltage source (such as a digital-to-analog converter) or divided down from a
voltage rail (such as a resistor divider from AVDD) as shown in Figure 8-7.
Vin

R1

VDSLVL

R2

Figure 8-7. Resistor divider to set VDSLVL from a voltage rail

Equation 10 and Equation 11 can be used to set the required VDSLVL voltage using a resistor divider from a
voltage source to establish an overcurrent limit given the RDS,on of the MOSFETs used:

VVDSLVL = IOC × Rds on (10)

R1 Vin
R2 = VVDSLVL − 1 (11)

where:
• VVDSLVL = VDSLVL voltage
• IOCP = VDS overcurrent limit
• RDS,on = MOSFET on-resistance
• VIN = voltage source for VDSLVL voltage divider
• R1/R2 = resistor ratio for setting VDSLVL

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For example, if a resistor divider from AVDD is used to set an overcurrent trip threshold of 30-A and the
MOSFET RDS(ON) = 10mΩ, then VDSLVL = 0.3V.
In some applications, there will be a difference between battery voltage (VBAT) to directly drive motor power and
PVDD voltage to power the DRV8329-Q1. Because high-side VDS monitoring is referenced from PVDD-SHx,
VDSLVL needs to be selected appropriately to accommodate for the difference in VBAT and PVDD.
Equation 12 helps select an appropriate VDSLVL if there is a difference between PVDD and VDSLVL:

VDSLVL = VBAT − PVDD + IOC*RDS ON (12)

For instance, if VBAT = 24.0 V, PVDD = 23.3 V, Rdson = 10-mΩ, and I_OC = 30-A, then VDSLVL should equal
1.0V to detect a 30-A overcurrent event across the high-side FET and a 100-A overcurrent event across the
low-side FET.
8.2.1.1.8 AVDD Power Losses
An integrated LDO can supply 3.3-V (up to 80-mA) as power rails for external ICs or supply the pullup voltages
for resistors and switches. The power loss from AVDD with respect to PVDD, AVDD voltage, and AVDD current
is PAVDD = (VPVDD - VAVDD) x IAVDD.

Higher power losses occur due larger dropout from PVDD to 3.3 V or increased AVDD load current.
8.2.1.1.9 Current Sensing and Output Filtering
The SO pin is typically sampled by an analog-to-digital converter in the MCU to calculate the total motor
phase current. A phase current calculation is used for closed-loop feedback such as overcurrent protection or
sensorless trapezoidal or Field-oriented control commutation
An example calculation for phase current is shown below for a system using VSO = 1.4 V, VCSAREF = 3.3V,
CSAGAIN = 20 V/V, and RSENSE = 1 mΩ.

V
VSO − CSAREF
I = CSAGAIN × R8 (13)
SENSE

1.4 V − 3.3 V
8
I = 20 V/V × 0.001 (14)

I = 49.375 A (15)

Sometimes high frequency noise can appear at the SO signals based on voltage ripple at VREF, added
inductance at the SO traces, or routing of SO traces near high frequency components. It is recommended to add
a low-pass RC filter close to the MCU with cutoff frequency at least 10 times the PWM switching frequency for
trapezoidal commutation and 100 times the PWM switching frequency for sinusoidal commutation to filter high
frequency noise. A recommended RC filter is 330-ohms, 470-pF to add minimal parallel capacitance to the ADC
and current mirroring circuitry. The cutoff frequency for the low-pass RC filter is in Equation 16.

1
fc = 2πRC (16)

8.2.1.1.10 Power Dissipation and Junction Temperature Losses

To calculate the junction temperature of the DRV8329-Q1 from power losses, use Equation 17. Note that the
thermal resistance θJA depends on PCB configurations such as the ambient temperature, numbers of PCB
layers, copper thickness on top and bottom layers, and the PCB area.

℃
T J ℃ = Ploss W × θ JA W + TA ℃ (17)

The table below shows summary of equations for calculating each loss in the DRV8329-Q1.

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Table 8-3. DRV8329-Q1 Power Losses

Loss type Equation

Standby power Pstandby = VPVDD x IPVDDS

GVDD CP mode (PVDD < 18V) PLDO = 2 x VPVDD x IGVDD - VGVDD x IGVDD

GVDD LDO mode (PVDD > 18V) PLDO = (VPVDD - VGVDD) x IGVDD

AVDD LDO PLDO = (VPVDD - VAVDD) x IAVDD

8.2.2 Application Curves

Figure 8-8. Device Powerup with PVDD

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Figure 8-9. Device Powerup with nSLEEP

Figure 8-10. GVDD voltage threshold (PVDD = 4.5 V)

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Figure 8-11. GVDD voltage threshold (PVDD = 20V)

Figure 8-12. AVDD powerup

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Figure 8-13. DRVOFF operation

Figure 8-14. Driver operation at 100% duty cycle

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Figure 8-15. Driver PWM operation, 20 kHz, 50% duty cycle, zoomed

Figure 8-16. Driver dead time of 100 ns (DT = 10 kΩ to GND)

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Figure 8-17. Driver dead time of 2000 ns (DT = 390 kΩ to GND)

Figure 8-18. Current sense amplifier operation (GAIN = 40 V/V)

8.3 Power Supply Recommendations

The DRV8329-Q1 family of devices is designed to operate from an input voltage supply (PVDD) range from 4.5
V to 60 V. A 10-µF and 0.1-µF ceramic capacitor rated for PVDD must be placed as close to the device as
possible. In addition, a bulk capacitor must be included on the PVDD pin but can be shared with the bulk bypass
capacitance for the external power MOSFETs. Additional bulk capacitance is required to bypass the external
half-bridge MOSFETs and should be sized according to the application requirements.
8.3.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor startup and braking methods

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The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ +
Motor Driver
±

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 8-19. Motor Drive Supply Parasitics Example

8.4 Layout
8.4.1 Layout Guidelines
Bypass the PVDD pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the PVDD pin using a bulk capacitor rated for PVDD. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 470 nF, rated for
PVDD, and be of type X5R or X7R.
The bootstrap capacitors (BSTx-SHx) should be placed closely to device pins to minimize loop inductance for
the gate drive paths.
The dead time resistor (RDT) should be placed as close as possible to the DT pin.
Bypass the AVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or
X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND
pin.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
When designing higher power systems, physics in the PCB layout can cause parasitic inductances,
capacitances, and impedances that deter the performance of the system as shown in Figure 8-20.
Understanding the parasitics that are present in a higher power motor drive system can help designers mitigate

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their effects through good PCB layout. For more information, please visit the System Design Considerations for
High-Power Motor Driver Applications and Best Practices for Board Layout of Motor Drivers application notes.
PVDD

LP
LP RP
PVDD
CP
GVDD CBULK
LP RGATE LP RSNUB
INHx HS GHx
HS

ESL ESR
LP
SHx CSNUB

LP
PHASE
CP

LP
CSNUB
GVDD
LP RGATE LP
INLx LS GLx
LS
RSNUB
LP RPDIFF
LSS LP
CP
LP
SNx LP

Figure 8-20. Parasitics in the PCB of a BLDC motor driver powerstage

Gate drive traces (BSTx, GHx, SHx, GLx, LSS) should be at least 15-20mil wide and as short as possible to the
MOSFET gates to minimize parasitic inductances and impedances. This helps supply large gate drive currents,
turn MOSFETs on efficiently, and improves VGS and VDS monitoring. If a shunt resistor is used to monitor the
low-side current from LSS to GND, ensure the shunt resistor selected is wide to minimize inductance introduced
at the low-side source LSS.
TI recommends connecting all non-power stage circuitry (including the thermal pad) to GND to reduce parasitic
effects and improve power dissipation from the device. Ensure grounds are connected through net-ties or wide
resistors to reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
8.4.2 Thermal Considerations
The DRV8329-Q1 has thermal shutdown (TSD) to protect against overtemperature. A die temperature in excess
of 150°C (minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.

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8.4.2.1 Power Dissipation

The DRV8329-Q1 integrates a variety of circuits that contribute to total power losses. These power losses
include standby power losses, GVDD power losses, and AVDD power losses.
At start-up and fault conditions, this current is much higher than normal running current; remember to take these
peak currents and their duration into consideration.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.

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9 Device and Documentation Support

9.1 Device Support
9.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
9.2 Documentation Support
9.2.1 Related Documentation
• Refer to the application note Power Delivery in Cordless Power Tools Using DRV8329
• Texas Instruments, DRV8329AEVM evaluation module
• Refer to the application note System Design Considerations for High-Power Motor Driver Applications
• Refer to the E2E FAQ How to Conduct a BLDC Schematic Review and Debug
• Refer to the application note Best Practices for Board Layout of Motor Drivers
• Refer to the application note QFN and SON PCB Attachment
• Refer to the application note Cut-Off Switch in High-Current Motor-Drive Applications
• Refer to the application note Hardware design considerations for an efficient vacuum cleaner using a BLDC
motor
• Refer to the application note Hardware Design Considerations for an Electric Bicycle Using a BLDC Motor
• Refer to the application note Sensored 3-Phase BLDC Motor Control Using MSP430
9.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
9.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.5 Community Resources
9.6 Trademarks
All trademarks are the property of their respective owners.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
March 2023 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 47

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PACKAGE OUTLINE
RGF0040E VQFN - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

5.1 A
B 4.9

PIN 1 INDEX AREA

7.1
6.9

1 MAX

SEATING PLANE
0.05 3.7±0.1 0.08 C
0.00
3.5
SYMM

(0.1) TYP
13 20
36X 0.5
12 21

SYMM 41
5.5 5.7±0.1

1
32
40X 0.3
0.2
PIN 1 ID 33
40
(OPTIONAL) 0.1 C A B
40X 0.5
0.3 0.05 C
4224999/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

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EXAMPLE BOARD LAYOUT

RGF0040E VQFN - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

(3.7)
(3.5)
36X (0.5) SYMM

40 33
40X (0.6)
40X (0.25)
1
32
(Ø0.2) VIA
TYP

41 SYMM
(5.7) (5.5)

(1.35)

(1.25)

21
12

13 20
(R0.05) TYP
(0.625) (0.975)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X

0.07 MAX 0.07 MIN

SOLDER MASK
ALL AROUND METAL ALL AROUND OPENING
EXPOSED METAL

EXPOSED METAL SOLDER MASK

METAL UNDER
OPENING
SOLDER MASK
NON- SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224999/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

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EXAMPLE STENCIL DESIGN

RGF0040E VQFN - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

(3.5)
36X (0.5) SYMM

40 33
40X (0.6)
40X (0.25) 41
1
32
(Ø0.2) VIA
TYP

SYMM
(5.5)
(0.675)

(1.35)

21
12 12X (1.15)

13 20
(R0.05) TYP 12X (1.05)
(1.25)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
69% PRINTED COVERAGE BY AREA
SCALE: 12X

4224999/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

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 PACKAGE OPTION ADDENDUM

www.ti.com 30-Mar-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8329AQRGFRQ1 ACTIVE VQFN RGF 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 D8329AQ Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF DRV8329-Q1 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Mar-2024

• Catalog : DRV8329

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 GENERIC PACKAGE VIEW
RGF 40 VQFN - 1 mm max height
5 x 7, 0.5 mm pitch PLASTIC QUAD FLAT PACK- NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225115/A

www.ti.com
 PACKAGE OUTLINE
RGF0040F VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
B 5.1 A
4.9

0.100 MIN

PIN 1 INDEX AREA

7.1
6.9

(0.130)

SECTION A-A
TYPICAL

1 MAX

SEATING PLANE
0.05 3.7±0.1 0.08 C
0.00
3.5 (0.2) TYP
13 20
36X 0.5
12
21
(0.16)

41 SYMM
5.5 5.7±0.1

1 32
40X 0.3
0.2
40 33
0.1 C A B
40X 0.5
SYMM
0.3 0.05 C
4225901/A 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGF0040F VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(4.8)
(3.7)
SYMM
40X (0.6)
40 33
40X (0.25)

1
32

36X (0.5)

SYMM 41
(5.7) (6.8)

2X
(1.35)

2X
(R 0.05) TYP (1.25)

12 21

13 20
(Ø 0.2) VIA
TYP 2X (0.625) 2X (0.975)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X

0.07 MIN
0.07 MAX
ALL AROUND
ALL AROUND
METAL SOLDER MASK
OPENING
SOLDER MASK
EXPOSED
OPENING EXPOSED METAL UNDER
METAL
METAL SOLDER MASK
NON SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
4225901/A 05/2020
SOLDER MASK DETAILS
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGF0040F VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(4.8)

SYMM 12X (1.05)

40X (0.6)
40 33
40X (0.25)

1
41 32

12X (1.15)
36X (0.5)

SYMM 2X
(0.675) (6.8)

2X
(1.35)

(R 0.05) TYP

12 21

METAL TYP
13 20

2X (1.25)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
69% PRINTED COVERAGE BY AREA
SCALE: 12X

4225901/A 05/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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