PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RTL, Cmodel, and testbench for NVDLA

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

An Open-source FPGA IP Generator

3-stage RV32IMACZb* processor with debug

Various HDL (Verilog) IP Cores

RISC-V Formal Verification Framework

Repository for basic (and not so basic) Verilog blocks with high re-use potential

mor1kx - an OpenRISC 1000 processor IP core

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

VRoom! RISC-V CPU

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

OpenXuantie - OpenC906 Core

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

FuseSoC-based SoC for VeeR EH1 and EL2

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Convolutional accelerator kernel, target ASIC & FPGA

Minimax: a Compressed-First, Microcoded RISC-V CPU

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

CoreScore

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

XCrypto: a cryptographic ISE for RISC-V