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ISCAS 2018: Florence, Italy
- IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy. IEEE 2018, ISBN 978-1-5386-4881-0
- Tingtian Li
, Daniel Pak-Kong Lun:
A Novel Reflection Removal Algorithm Using the Light Field Camera. 1-5 - Po-Hsiang Hsu, Yang-Ming Yeh
A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design. 1-5 - Ya Zhou
Visual Comfort Assessment for Stereoscopic Image Retargeting. 1-5 - Zhaohui Che, Guangtao Zhai, Ke Gu, Patrick Le Callet, Xianming Liu, Deming Zhai, Xiao Gu:
Adaptive Screen Content Image Enhancement Strategy using Layer-based Segmentation. 1-5 - Jialu Yang, Ping An, Jian Ma, Kai Li, Liquan Shen:
No-reference stereo image quality assessment by learning gradient dictionary-based color visual characteristics. 1-5 - Prerna Batta, Maninder Singh
Evaluation of Support Vector Machine Kernels for Detecting Network Anomalies. 1-4 - Xiao Fan Liu
Evaluation of the Anonymizability of Complex Networks. 1-4 - Tanuja Shanmukhappa, Ivan Wang Hei Ho
Multi-layer Public Transport Network Analysis. 1-5 - Michael Small
Ordinal Network Measures - Quantifying Determinism in Data. 1-5 - Jennifer Hasler:
Analog Abstraction, Computation, and Numerical Analysis. 1-5 - William Hwang, Weier Wan
Coming Up N3XT, After 2D Scaling of Si CMOS. 1-5 - György Csaba
Computing with Coupled Oscillators: Theory, Devices, and Applications. 1-5 - Fuxi Cai
Feature extraction and analysis using memristor networks. 1-4 - Ali Moin, Andy Zhou, Abbas Rahimi
An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier. 1-5 - Luke R. Everson, Dwaipayan Biswas
BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG. 1-5 - Shang-Ho Lawrence Tsai, Min-Shan Tsai
A Novel System and Statistical Analysis for Predicting Defibrillation Timing During Ventricular Fibrillation. 1-5 - Juzheng Liu, Jing Chen, Hanjun Jiang, Wen Jia, Qingliang Lin, Zhihua Wang:
Activity Recognition in Wearable ECG Monitoring Aided by Accelerometer Data. 1-4 - Tahmid Ahmed, Khalid B. Mirza
Resource Efficient Pre-processor for Drift Removal in Neurochemical Signals. 1-5 - Siyu Liu
Portable photoacoustic system for noninvasive blood temperature measurement. 1-5 - Nicholas S. Coleman, Karen Nan Miu:
Time Window Selection via Online Risk Assessment for Power Distribution System Analysis. 1-5 - Christian Strobl, Maximilian Schäfer
Non-Recursive System Identification and Fault Detection in LVDC and ELVDC Grids. 1-5 - Domingo Biel, Jacquelien M. A. Scherpen:
Voltage regulation with power curtailment in a single-phase grid-connected PV inverter. 1-5 - Christoph Braun, Mahbubur Rahman, Valentina Cecchi:
An evaluation of transmission line models incorporating longitudinal temperature variations. 1-5 - Wenshuo Tang, Merlinda Andoni
Accurately Forecasting the Health of Energy System Assets. 1-5 - Martin Villemur
Neuromorphic Cellular Neural Network Processor for Intelligent Internet-of-Things. 1-4 - Yuxiang Huan, Jiawei Xu, Lirong Zheng, Hannu Tenhunen, Zhuo Zou:
A 3D Tiled Low Power Accelerator for Convolutional Neural Network. 1-5 - Yingyan Lin, Joseph R. Cavallaro
Energy-efficient Convolutional Neural Networks via Statistical Error Compensated Near Threshold Computing. 1-5 - Arash Ardakani, Carlo Condo, Warren J. Gross:
A Convolutional Accelerator for Neural Networks With Binary Weights. 1-5 - Prashant Singh:
A 19nW, near-threshold to I/O voltage level shifter in 28nm FD-SOI using 1.8V/28Å device for IoT Systems. 1-4 - Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet:
Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. 1-5 - Qicong Liao, Weiqiang Liu, Fei Qiao, Chenghua Wang, Fabrizio Lombardi:
Design of Approximate FFT with Bit-width Selection Algorithms. 1-5 - Ke Xu
A Low-power Pyramid Motion Estimation Engine for 4K@30fps Realtime HEVC Video Encoding. 1-4 - Sying-Jyan Wang
Register PUF with No Power-Up Restrictions. 1-5 - Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi
Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference. 1-5 - Yuejiang Wen
PUF Modeling Attack using Active Learning. 1-5 - Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay:
On Finding Suitable Key-Gate Locations In Logic Encryption. 1-5 - Missael Garcia, Kevin Kauffman, Tyler Davis, Radoslav Marinov, Viktor Gruev:
A 1280 by 720 by 3, 250 mW, 24 fps Hexachromatic Imager for Near-Infrared Fluorescence Image-Guided Surgery. 1-5 - Melik Yazici, Omer Ceylan
High Dynamic Range Smart Pixel Architecture for Infrared Focal Plane Arrays. 1-5 - Shahbaz Abbasi
A Novel Approach to Noise Shaping in Digital Pixels for Infrared Imagers using Over-Integration. 1-5 - Roger Figueras
A 128× 128-pix 4-kfps 14-bit Digital-Pixel PbSe-CMOS Uncooled MWIR Imager. 1-5 - Meera Punjiya, Rachel Owyeung, Brian Wee, Sameer Sonkusale:
High Dynamic Range CMOS Imager for Colorimetric Gas Sensors. 1-5 - Mohammed H. M. Abdulwahab, Nicolas Moser
A CMOS Bio-Chip combining pH Sensing, Temperature Regulation and Electric Field Generation for DNA Detection and Manipulation. 1-5 - Junming Zeng, Nicholas Miscourides, Pantelis Georgiou
A 128×128 Current-Mode Ultra-High Frame Rate ISFET Array for Ion Imaging. 1-5 - Axel Hanuschek, Martin Hantschke, Iasonas F. Triantis
Simulation of Temperature Profiles due to Joule Heating in Microfluidic Systems. 1-4 - Nicolas Moser
An ISFET Pixel with Integrated Trapped Charge Compensation using Temperature Feedback. 1-5 - Karan Gumber, Meenakshi Rawat:
Modified RFin-RFout broadband predistorter for 5G communication system. 1-5 - Walter D. Leon-Salas, Xiaozhe Fan
Exploiting Luminescence Emissions of Solar Cells for Optical Frequency Identification (OFID). 1-5 - Yang Xie, Dan Li, Yiqun Liu, Ming Liu, Yihua Zhang, Xiaoli Wang, Li Geng:
Low-Noise High-Linearity 56Gb/s PAM-4 Optical Receiver in 45nm SOI CMOS. 1-4 - Katharina Hausmair, Ulf Gustavsson
Modeling and Linearization of Multi-Antenna Transmitters Using Over-the-Air Measurements. 1-4 - Najath Akram
Multiport ADCs for Microwave Focal Plane Array Dish Receivers. 1-5 - Behzad Razavi:
An Alternative Analysis of Noise Folding in Fractional-N Synthesizers. 1-4 - Harry Weber, Wolfgang Mathis
Steady State Analysis of Crystal Oscillator Circuits Using a Self-consistent Carleman Linearization. 1-5 - Amandeep Kaur, Deepak Mishra
A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors. 1-5 - Armia Salib, Mark F. Flanagan
A Generic Foreground Calibration Algorithm For ADCs with Nonlinear Impairments. 1-4 - Bohui Xiao, Spencer Leuenberger, Praveen Kumar Venkatachala, Ahmed ElShater, Calvin Lee, Michael Oatman, Un-Ku Moon:
Power Optimized Comparator Selecting Method For Stochastic ADC. 1-4 - Omer Can Akgun
An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction. 1-5 - Insani Abdi Bangsa, Dieuwert P. N. Mul, Wouter A. Serdijn:
Stochastic Resonance Mixed-Signal Processing: Analog-to-Digital Conversion and Signal Processing Employing Noise. 1-5 - Takao Marukame, Yutaka Tamura, Koji Takahashi, Toshimitsu Kitamura, Takashi Takebayashi, Yoshifumi Nishi:
Live Demonstration: A prototype of Analog/Digital-mixed Neural Networks for reconfigurable learning. 1- - Ricardo Madeira
Live Demonstration: An Automated Test Bench for an 130nm SC DC-DC Converter. 1- - Corey Lammie
Live Demonstration: Unsupervised Character Recognition with a FPGA Neuromorphic System. 1- - Walter D. Leon-Salas, Xiaozhe Fan
Live Demonstration: Modulating Luminescence Emissions of Solar Cells for Sensing and Identification. 1- - Jens Döge
Live Demonstration: Hitting a Table Tennis Ball with a Programmable Vision-System-on-Chip. 1- - Shruti R. Kulkarni, John M. Alexiades, Bipin Rajendran:
Live Demonstration: Image Classification Using Bio-inspired Spiking Neural Networks. 1- - Takashi Tokuda, Wuthibenjaphonchai Nattakarn, Takaaki Ishizu, Makito Haruta, Toshihiko Noda, Kiyotaka Sasagawa
Live Demonstration: IoT micronode with optical ID transmission capability operated by optical energy harvesting. 1- - Spyros Stathopoulos, Ali Khiat, Alexantrou Serb, Themis Prodromakis
Live Demonstration: Benchmarking Analogue Performance of Emerging Random Access Memory Technologies. 1- - Alexander Neckar, Terrence C. Stewart, Ben Varkey Benjamin, Kwabena Boahen:
Live Demonstration: Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation. 1- - Marta Franceschi
Live Demonstration: Electrotactile feedback from an electronic skin through flexible electrode matrix. 1- - Esteban Ferro
Live Demonstration: Light Energy Harvesting System with an On-Chip Solar Cell and Cold Start-Up. 1- - Fernando Perez-Peña, Elena Cerezuela-Escudero, Angel Jiménez-Fernandez, Arturo Morgado Estévez:
Live Demonstration: Real-time neuro-inspired sound source localization and tracking architecture applied to a robotic platform. 1- - Yutaro Ishida, Takashi Morie, Hakaru Tamukoh:
Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots. 1- - Takumi Ito, Changhoon Choi, Takahiro Yamamoto, Takashi Nakajima, Takayuki Kawahara
Live Demonstration of IoT and AI System for Recognition of States of Buildings subjected to Seismic Vibration Motion. 1- - Chiara Bartolozzi, Paolo Motto Ros
Live Demonstration: Tactile Events from Off-The-Shelf Sensors in a Robotic Skin. 1- - Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. 1- - A. García-Rodríguez, R. Rodríguez-Sakamoto, Jorge Fernández-Berni, Rocío del Río, Jesús Marín
Live Demonstration: Low-Power Low-Cost Cyber-Physical System for Bird Monitoring. 1- - Francesca Stradolini, Nadia Tamburrano, Thiébaud Modoux, Abuduwaili Tuoheti, Danilo Demarchi, Sandro Carrara:
Live Demonstration: An IoT Cloud-Based Architecture for Anesthesia Monitoring. 1- - Xin Shi, Yongpan Liu, Yinan Sun, Yixiong Yang, Keni Qiu:
Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor. 1- - David Slayback, Syed Abdali, Justin Brooks, W. David Hairston, Paul Groves:
Live Demonstration: Novel Methods for EEG Visualization and Virtualization. 1 - Zhimin Xu, Xinggong Zhang, Kai Zhang, Zongming Guo:
Probabilistic Viewport Adaptive Streaming for 360-degree Videos. 1-5 - Tongyu Dai, Xinggong Zhang, Zongming Guo:
Learning-based Congestion Control for Internet Video Communication over Wireless Networks. 1-5 - Yu-Jui Chiang, Hsu-Feng Hsiao:
Expectation Model and Scheduling for Video Streaming. 1-5 - Hualong Yu, Lu Yu
Improved DASH for Cross-Random-Access Prediction Structure in Video Coding. 1-5 - Yuta Ukon, Koji Yamazaki, Koyo Nitta
Video Service Function Chaining with a Real-time Packet Reordering Circuit. 1-5 - Jing Li, Cong Li, Xiang Li
Quantifying the contact memory in temporal human interactions. 1-5 - Francesco Alderisio, Maria Lombardi
Emergence of leadership in complex networks and human groups. 1-5 - Isaac S. Klickstein, Ishan Kafle, Sudarshan Bartaula, Francesco Sorrentino:
Energy Scaling with Control Distance in Complex Networks. 1-5 - Guanxue Yang, Lin Wang, Xiaofan Wang:
Time-delayed Network Reconstruction based on Nonlinear Continuous Dynamical Systems. 1-5 - Alon Ascoli, Dominik Baumann
Mem-adaptive computing - Part I: Theory. 1-5 - Alon Ascoli, Dominik Baumann
Mem-adaptive computing - Part II: Circuit design. 1-6 - Can Li, Yunning Li, Hao Jiang, Wenhao Song, Peng Lin
Large Memristor Crossbars for Analog Computing. 1-4 - Zhongrui Wang
Unconventional computing with diffusive memristors. 1-5 - Alexander Serb
Processing big-data with Memristive Technologies: Splitting the Hyperplane Efficiently. 1-5 - Waziha Kabir, M. Omair Ahmad, M. N. S. Swamy:
Weighted Hybrid Fusion for Multimodal Biometric Recognition System. 1-4 - Jan Müller, Jens Müller, Benjamin Koch, Ronald Tetzlaff
Architectures for Intraoperative Image Fusion in Brain Surgery. 1-5 - Zheng Li, Scott E. Kerick, Ryan W. Robucci, Justin Brooks, Javier O. Garcia, Nilanjan Banerjee:
Implementation of Structural Synchrony and Linear Measures of Brain Network Connectivity for Real-Time State Estimation. 1-5 - Lahir Marni, Morteza Hosseini, Jennifer Hopp, Pedram Mohseni, Tinoosh Mohsenin:
A Real-Time Wearable FPGA-based Seizure Detection Processor Using MCMC. 1-4 - Jongpal Kim, Hyungho Ko:
Reconfigurable Voltage/Current Readout Instrumentation Amplifier for Cardiovascular Health Monitoring. 1-4 - Y. S. Geng, Dongsheng Yu, H. Cheng, Herbert H. C. Iu, Tyrone Fernando
Modified Pulse Train Control Based Parallel Connected Buck Converters. 1-5 - Humam Al-Baidhani
Nonlinear Modeling and Voltage-Mode Control of DC-DC Boost Converter for CCM. 1-5 - Ahmed H. Shaltout, Mark Lipski, Stefano Gregori
Efficiency Model of Fully-Integrated Boost DC-DC Converters. 1-5 - Tomonori Isono, Ning Li, Yasuhiro Sugimoto:
Continuous-Time Modeling of Hysteretic DC-DC Converters in CCM. 1-4 - Dalvir K. Saini, Ankit Chadha, Agasthya Ayachit, Alberto Reatti, Marian K. Kazimierczuk:
Duty Cycle and Input-to-Output Voltage Transfer Functions of Tapped-Inductor Buck DC-DC Converter. 1-5 - Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda:
Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop. 1-5 - Donghyeon Han, Jinsu Lee, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices. 1-5 - Chengbo Xue, Shan Cao, Rongkun Jiang, Hao Yang:
A Reconfigurable Pipelined Architecture for Convolutional Neural Network Acceleration. 1-5 - Yecheng Lyu, Lin Bai
Real-Time Road Segmentation Using LiDAR Data Processing on an FPGA. 1-5 - Yunhui Zhu, Yaohua Zuo, Tong Zhou, Guoping Fan:
A Multi-Mode Visual Recognition Hardware Accelerator for AR/MR Glasses. 1-5 - Chen Liu, Yuanqing Cheng, Ying Wang, Youguang Zhang, Weisheng Zhao:
NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. 1-5 - Ziji Zhang
Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning. 1-4 - Semih Ramazanoglu
Switched Capacitor Variable Delay Line. 1-5 - Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman
A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. 1-5 - Dongjun Park
A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs. 1-4 - Qianqian Wang, Degang Chen, Randall L. Geiger:
Transparent side channel trigger mechanism on analog circuits with PAAST hardware Trojans. 1-4 - Sumedh Somnath Dhabu, Yue Zheng, Wenye Liu, Chip-Hong Chang
Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test. 1-5 - Tutu Wan, Emre Salman:
Ultra Low Power SIMON Core for Lightweight Encryption. 1-5 - Darshit Vaghani, Satyadev Ahlawat
On Securing Scan Design Through Test Vector Encryption. 1-5 - Kyle Juretus, Ioannis Savidis:
Time Domain Sequential Locking for Increased Security. 1-5 - Jing Huang, Menghan Guo, Shizheng Wang, Shoushun Chen:
A Motion Sensor with On-Chip Pixel Rendering Module for Optical Flow Gradient Extraction. 1-5 - Massimo Gottardi, Michela Lecca:
A 35μW 64 × 64 Pixels Vision Sensor Embedding Local Binary Pattern Code Computation. 1-4 - Masahide Goto
Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration. 1-4 - Julien N. P. Martel, Jonathan Müller, Jörg Conradt, Yulia Sandamirskaya:
An Active Approach to Solving the Stereo Matching Problem using Event-Based Sensors. 1-5 - Pin-Wen Chen, Chi-Wei Huang, Chung-Yu Wu:
An 1.97μ, W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring. 1-5 - Daniele Allegri, Achille Donida, Piero Malcovati, Diego Barrettino
CMOS-Based Multifrequency Impedance Analyzer for Biomedical Applications. 1-5 - Achraf Lamlih, Philippe Freitas, Stephane David-Grignot, Jérémie Salles, Vincent Kerzèrho, Fabien Soulier
Wideband Fully Differential Current Driver with Optimized Output Impedance for Bioimpedance Measurements. 1-5 - Junchao Wang, Kaining Han, Anastasios Alexandridis
An ASIC Implementation of Security Scheme for Body Area Networks. 1-5 - Leila Montazeri, Nizar El Zarif
Active Control of μLED Arrays for Optogenetic Stimulation. 1-5 - Oscar Castañeda
VLSI Design of a 3-bit Constant-Modulus Precoder for Massive MU-MIMO. 1-5 - Harsh Aurora, Carlo Condo, Warren J. Gross:
Low-Complexity Software Stack Decoding of Polar Codes. 1-5 - Chao Yang, Weihong Xu, Zaichen Zhang, Xiaohu You, Chuan Zhang:
A Channel-Blind Detection for SCMA Based on Image Processing Techniques. 1-5 - Mathieu Léonardon, Camille Leroux, David Binet, J. M. Pierre Langlois, Christophe Jégo, Yvon Savaria:
Custom Low Power Processor for Polar Decoding. 1-5 - Hao Li, Jie Guo, Yongshi Wang, Li Li, Zhigang Wang, Houjun Wang, Jian Gao:
Energy Efficient Antenna Selection Scheme for Downlink Massive MIMO Systems. 1-4 - Wei Zhou, Wang Ling Goh, Jia Hao Cheong, Yuan Gao
A 16.6 μW 3.12 MHz RC Relaxation Oscillator with 160.3 dBc/Hz FOM. 1-5 - Josip Mikulic, Gregor Schatzberger, Adrijan Baric:
A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair. 1-4 - Yucheng Tong, Fa Foster Dai, Hossein Noori
A Low Phase Noise Ring Oscillator with Miller Capacitance Cancellation. 1-4 - István Kovács, Marius Neag
New dual-loop topology for ring VCOs based on latched delay cells. 1-5 - Takeshi Shima, Shun Kozuki, Nicodimus Retdian:
Multiphase TDC inspired by the Early Vision Model. 1-4 - Jian Sen Teh
A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. 1-5 - Siddharth R. K.
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. 1-5 - Meng-Shuan Wu, Hao-Chiao Hong
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation. 1-5 - Kayode Sanni, Tomas Figliolia, Gaspar Tognetti, Philippe O. Pouliquen, Andreas G. Andreou
A Charge-Based Architecture for Energy-Efficient Vector-Vector Multiplication in 65nm CMOS. 1-5 - Minqiang Jiang, Shanxi Li, Nam Ling, Jianhua Zheng, Philipp Zhang:
On Derivation of Most Probable Modes for Intra Prediction in Video Coding. 1-4 - Esraa M. Hamed, Mohammed E. Fouda, Ahmed G. Radwan
Conditions and Emulation of Double Pinch-off Points in Fractional-order Memristor. 1-5 - Todd J. Freeborn
Changes of Fractional-Order Model Parameters in Biceps Tissue from Fatiguing Exercise. 1-5 - Dina A. John, Karabi Biswas
Analysis of disturbance rejection by PIλ controller using solid state fractional capacitor. 1-5 - Costas Vastarouchas, Costas Psychalinos
Fractional-Order Model of a Commercial Ear Simulator. 1-4 - Mohamad Moner Al Chawa
Design and implementation of passive memristor emulators using a charge-flux approach. 1-5 - Julius Georgiou, Kypros M. Kossifos
Chua Mem-Components for Adaptive RF Metamaterials. 1-5 - Stephan Menzel, Anne Siemon, Alon Ascoli, Ronald Tetzlaff
Requirements and Challenges for Modelling Redox-based Memristive Devices. 1-5 - Mohammed E. Elbtity, Ahmed G. Radwan
Small Area and Low Power Hybrid CMOS-Memristor Based FIFO for NoC. 1-5 - Christian Bongiorno, Alessandro Rizzo, Maurizio Porfiri:
An information-theoretic approach to study activity driven networks. 1-5 - He Wang, Wenwu Yu, Lingling Yao, Guanrong Chen:
Fully-distributed finite-time consensus of second-order multi-agent systems on a directed network. 1-4 - Raffaele Iervolino
A Consensus Policy for Heterogeneous Opinion Dynamics. 1-5 - Ricardo Cardona Rivera, Pietro De Lellis
Enhancing pinning controllability of complex networks of coupled maps. 1-5 - Yin Sun, Victor Adrian, Joseph S. Chang:
Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters. 1-4 - Yong Qu
An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters. 1-4 - Adel Ali Abosnina, Gerry Moschopoulos:
A Study of Three-Phase DC-DC Boost Converters. 1-5 - Jilong Guo, Qiming Guo, Xinghui Liu, Jiahao Kang, Bihua Yang, Jun Xie, Ximeng Guan, Jiasong Sun, Ze Yuan, Xiang Zou, Peng Wei, Xiaojun Yu, Zihong Liu:
A Fast Charging System based on Charging Current Dynamic Adjustment Method. 1-5 - Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting. 1-5 - Jiyong Woo, Xiaochen Peng, Shimeng Yu
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. 1-4 - Shin-ichi O'Uchi, Hiroshi Fuketa, Tsutomu Ikegami, Wakana Nogami, Takashi Matsukawa, Tomohiro Kudoh, Ryousei Takano:
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. 1-5 - Lita Yang, Daniel Bankman, Bert Moons, Marian Verhelst
Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor. 1-5 - Antonello Rosato, Rosa Altilio, Massimo Panella
On-line Learning of RVFL Neural Networks on Finite Precision Hardware. 1-5 - Giulia Santoro, Mario R. Casu
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. 1-5 - Yuan Cao, Chip-Hong Chang
A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References. 1-5 - Davide Bellizia
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach. 1-5 - Qianying Tang, Won Ho Choi, Luke R. Everson, Keshab K. Parhi
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC. 1-5 - Milos Grujic
A Closer Look at the Delay-Chain based TRNG. 1-5 - Sandeep Goyal, Ron Joseph, Virendra Singh, Shalabh Gupta:
A PAM-4 10S/12S line coding scheme with equi-probable levels. 1-5 - Davide Fabbri
Micropower Design of an Energy Autonomous RF Tag for UWB Localization Applications. 1-5 - Julien Dupeyroux
M2APix: A Bio-Inspired Auto-Adaptive Visual Sensor for Robust Ground Height Estimation. 1-4 - Joseph A. Schmitz, Daniel Rogge, Mahir Kabeer Gharzai, Sina Balkir, Michael W. Hoffman, Mark Bauer:
A Low-Power Radiation Detection System for Portable, Long-Duration Monitoring. 1-4 - Rui Zhang, Shiquan Fan, Li Geng:
A Near-Zero-Power Temperature Sensor with ±0.24 °C Inaccuracy Using Only Standard CMOS Transistors for IoT Applications. 1-4 - Yan Zhang, Yanghyo Kim, Adrian Tang, Jon Kawamura, Theodore Reck, M.-C. Frank Chang:
A 2.6GS/s Spectrometer System in 65nm CMOS for Spaceborne Telescopic Sensing. 1-4 - Yeseul Jeon, Hyuntak Jeon, Song-I Cheon, Chongsoo Jung, Minkyu Je:
A 650-uW 30-Mbps Galvanic Coupling Communication Receiver for Bionic Arms. 1-5 - Seok-Ju Yun, Jaechun Lee, Joonseong Kang, Chisung Bae, Junyeub Suh, Sang Joon Kim:
A Low Power Fully Intergrated RF Transceiver for Medical Implant Communication. 1-4 - Ehsan Ashoori
Compact and Low Power Analog Front End with in-situ Data Decimator for High-Channel-Count ECoG Recording. 1-5 - Bibin John, Clemens Spink, Markus Braunschweig, Rajeev Ranjan, Dietmar Schroeder, Andreas Koops, Gregor Woldt, Ilka Rauh, Andreas Leuzinger, Gerhard Adam, Wolfgang H. Krautschneider:
A Stent Graft Occlusion Detection : Pressure Sensing Implant Device with Inductive Power and Data Telemetry. 1-4 - Seyed Hadi Mirfarshbafan, Mahdi Shabany, Arash Amini, Seyed Alireza Nezamalhosseini
Near-ML Detection in Massive MIMO Systems with One-Bit ADCs: Algorithm and VLSI Design. 1-5 - Marco Crepaldi
A 1 Gbps UWB OOK Receiver with Double PLL All-Digital CDR and Data Packet Re-Synchronizer. 1-5 - Chih-Hsuan Chiang, Shuo-An Huang, Chiao-En Chen
A 2×2-16×16 Reconfigurable GGMD Processor for MIMO Communication Systems. 1-5 - Ulrich L. Rohde, Ajay K. Poddar, Alexandru M. Silaghi:
Monitoring Radios: Dynamics And Emerging Trends. 1-5 - Piyush Kaul
An UWB, Low-Noise, Low-Power Quadrature VCO using Delay-Locked Loop in 40-nm CMOS for Image-Rejection Receivers. 1-5 - Arpan Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan:
A 27.2GHz bipolar LC-VCO using class-C biasing to maximize achievable Fosc in 130nm BiCMOS. 1-5 - Alessandro Garghetti, Andrea L. Lacaita
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. 1-4 - Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub:
A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator. 1-5 - Vincent Rieß
Analysis and Design of a 60 GHz Fully-Differential Frequency Doubler in 130 nm SiGe BiCMOS. 1-5 - Baozhen Chen, Frank M. Yaul
An Adaptive SAR ADC for DC to Nyquist Rate Signals. 1-5 - Hongshuai Zhang
A 10-bit 200-kS/s 1.76-μW SAR ADC with Hybrid CAP-MOS DAC for Energy-Limited Applications. 1-5 - Hua Fan, Jingxuan Yang, Franco Maloberti, Quanyuan Feng, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari
High Linearity SAR ADC for High Performance Sensor System. 1-4 - Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang:
A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window. 1-4 - Sohail Asghar, Sohaib Saadat Afridi, Anu Pillai, Anita Schuler, José M. de la Rosa, Ivan John O'Connell
A 2MS/s, 11.22 ENOB, 3.2 Vpp-d SAR ADC with improved DNL and offset calculation. 4- - Gemma Taverni, Diederik Paul Moeys, Cheng-Han Li, Tobi Delbrück, Celso Cavaco, Vasyl Motsnyi, David San Segundo Bello:
Live Demonstration: Front and Back Illuminated Dynamic and Active Pixel Vision Sensors Comparison. 1- - Mehdi Noormohammadi Khiarak, Kiyotaka Sasagawa
Live Demonstration: An Energy-Efficient CMOS Biophotometry Sensor Interface. 1- - Anselm Au
Live Demonstration: A Mobile Diagnostic System for Rapid Detection and Tracking of Infectious Diseases. 1- - Julien N. P. Martel, Jonathan Müller, Jörg Conradt, Yulia Sandamirskaya:
Live Demonstration: An Active System for Depth Reconstruction using Event-Based Sensors. 1- - Krzysztof Wildner, Nishanth Kulasekeram, Khalid B. Mirza
Live Demo: Reconfigurable Low-noise Multichannel Amplifier for Neurochemical Recording. 1- - Thomas Abbey, Alexander Serb, Nikolaos Vasilakis, Loukas Michalas, Ali Khiat, Spyros Stathopoulos, Themis Prodromakis
Live Demonstration: An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation. 1- - Naty Ould Sidaty, Marko Viitanen
Live Demonstration: End-to-End Real-Time ROI-based Encryption in HEVC Videos. 1- - Yu Zou, Massimo Gottardi, Matteo Perenzoni:
Live Demostration: Low Power Vision Sensor with Robust Dynamic Background Rejection. 1- - Francesco Galluppi
Live Demonstration: A Wearable Device for Optogenetic Vision Restoration. 1- - Pei-Yin Chen
Live Demonstration: Hardware Design of Video Defogging Method for Real-Time Applications. 1- - Fabio Rossi
Live Demonstration: Low Power System for Event-Driven Control of Functional Electrical Stimulation. 1- - Vili Viitamäki, Panu Sjövall
Live Demonstration: 4K100p HEVC Intra Encoder. 1- - Missael Garcia, Kevin Kauffman, Tyler Davis, Radoslav Marinov, Viktor Gruev:
Live Demonstration: A 1280 by 720 by 3, 250 mW, 24 fps Hexachromatic Imager for Near-Infrared Fluorescence Image-Guided Surgery. 1- - Khandaker A. Al Mamun, Nicole McFarlane:
Live Demonstration: Portable Bowel Sound Idenfication System. 1- - Robert Giterman, Roman Golman, Amir Shalom, Or Maltabashi, Alexander Fish
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. 1- - Jian Zhang, Shuming Chen, Zhi Wang, Lei Wang, Linghui Lv, Yaohua Wang:
Live Demonstration: Image Segmentation on the FPGA-based Pre-calculating Ising Memory. 1- - Johannes Wagner, Maurits Ortmanns:
Live Demonstration: Designing CT BP ΣΔ Modulators with www.sigma-delta.de. 1- - Yu Wu, Dai Jiang, Richard H. Bayford, Andreas Demosthenous
Live Demonstration: A Wearable EIT System for Hand Prosthesis Motion Controls. 1- - Lukasz Farian
Live Demonstration: A Miniaturized Two-Axis Low Latency and Low-Power Sun Sensor for Attitude Determination of Sounding Rockets. 1 - Amit Mahesh Joshi, Mohammad Samar Ansari, Chitrakant Sahu
VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder. 1-4 - Douglas Corrêa, Guilherme Corrêa, Daniel Palomino
OTED: Encoding Optimization Technique Targeting Energy-Efficient HEVC Decoding. 1-5 - Christian Herglotz, André Kaup
Decoding Energy Estimation of an HEVC Hardware Decoder. 1-5 - Amir Ahmad Mohammadi, Mohammad Sadegh Alizadeh, Mohammad Sharifkhani:
JVET Encoder Complexity Analysis. 1-5 - Selman Ergünay, Yusuf Leblebici:
Hardware Implementation of a Smart Camera with Keypoint Detection and Description. 1-4 - Nancy S. Soliman, Mohamed F. Tolba, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan:
FPGA Implementation of X- and Heart-shapes Controllable Multi-Scroll Attractors. 1-5 - Todd J. Freeborn
Supercapacitor Fractional-Order Model Discharging from Polynomial Time-Varying Currents. 1-5 - Panagiotis Bertsias
Fractional-Order Differentiators and Integrators with Reduced Circuit Complexity. 1-4 - Arturo Buscarino, Riccardo Caponetto, Carlo Famoso, Luigi Fortuna:
Jump resonance in fractional order circuits. 1-5 - Arturo Buscarino, Claudia Corradino
Role of diversity in taming chaos in driven memristive arrays. 1-5 - Valerio Milo
Resistive switching synapses for unsupervised learning in feed-forward and recurrent neural networks. 1-5 - S. R. Nandakumar, Manuel Le Gallo
Mixed-precision architecture based on computational memory for training deep neural networks. 1-5 - Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Shahar Kvatinsky:
Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC. 1-5 - Ioulia Tzouvadaki, Abuduwaili Tuoheti
Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics. 1-5 - Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas
Memristive Cellular Automata for Modeling of Epileptic Brain Activity. 1-5 - Ernesto Estrada
Synchronization in networks of Rössler oscillators with long-range interactions. 1-4 - Pengxiang Ren, Ali Abur:
Obtaining Partial Solutions for Divergent State Estimation Problems in Large Power Systems. 1-5 - Rassul Bairamkulov
Versatile Framework for Power Delivery Exploration. 1-5 - Costas D. Vournas, Panagiotis Mandoulidis:
On-Line Voltage Stability Monitoring. 1-5 - Wei-Ting Lin, Zong-Yi Lin, Chia-Hao Liu, Ke-Horng Chen
A 20MHz Low Dropout Controlled Current Sensor for Constant On-Time Based Envelop Tacking Supply Modulator for Radio Frequency Power Amplifier. 1-4 - Seyed Mohammad Noghabaei, Rafael L. Radin, Yvon Savaria, Mohamad Sawan:
A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications. 1-4 - Long D. Nguyen, Dongyun Lin, Zhiping Lin, Jiuwen Cao:
Deep CNNs for microscopic image classification by exploiting transfer learning and feature concatenation. 1-5 - Vasileios Lioutas, Nikolaos Passalis, Anastasios Tefas
Visual Question Answering using Explicit Visual Attention. 1-5 - David Slayback, Syed Abdali, Justin Brooks, W. David Hairston, Paul Groves:
Novel Methods for EEG Visualization and Visualization. 1-5 - Ayesha Khalid, James Howe
Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography. 1-5 - Zhen Gu
An Implementation of Karatsuba-based Montgomery Modular Multiplication with Only Half-size Additions. 1-5 - Benjamin Lac, Anne Canteaut, Jacques J. A. Fournier, Renaud Sirdey
Thwarting Fault Attacks against Lightweight Cryptography using SIMD Instructions. 1-5 - Tuy Nguyen Tan
High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting. 1-4 - Jithendar Anumula, Enea Ceolini
An event-driven probabilistic model of sound source localization using cochlea spikes. 1-5 - Ying Xu, Saeed Afshar, Ram Kuber Singh, Tara Julia Hamilton
A Machine Hearing System for Binaural Sound Localization based on Instantaneous Correlation. 1-5 - Ram Kuber Singh, Ying Xu, Runchun Wang, Tara Julia Hamilton
CAR-Lite: A Multi-Rate Cochlea Model on FPGA. 1-5 - Qian Yu, Farid Boussaïd
Room-Temperature Dual-mode CMOS Gas-FET Sensor for Diabetes Detection. 1-4 - Virgilio Valente, Matthew Schormans, Andreas Demosthenous
An Energy-Efficient 1.2V 4-Channel Wireless CMOS Potentiostat for Amperometric Biosensors. 1-4 - Guijie Zhu, Songping Mai, Xian Tang, Chun Zhang, Zhihua Wang, Hong Chen:
An Energy-Efficient High-Frequency Neuro-Stimulator with Parallel Pulse Generators, Staggered Output and Extended Average Current Range. 1-4 - Hyungwoo Lee, Sang Joon Kim:
Energy Efficient Bio-Feedback Stimulation System with Adaptive Parameters Optimization Closed Loop. 1-4 - Edward K. F. Lee:
A Power Efficient LDO-Type Wireless Battery Charger for Biomedical Implants Based on Direct Charging from Regulated Rectifier Current. 1-4 - Henry Lancashire
A MicroChannel Neural Interface ASIC. 1-4 - Esmaeel Maghsoudloo, Gabriel Gagnon-Turcotte, Z. Rezaei, Benoit Gosselin
A Smart Neuroscience Platform with Wireless Power Transmission for Simultaneous Optogenetics and Electrophysiological Recording. 1-5 - Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. 1-5 - Yuan-Sheng Lee, Wei-Zen Chen:
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery. 1-4 - Linqi Shi, Weixin Gai, Xiaoting Zhi, Liangxiao Tang, Xiao Xiang:
An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. 1-4 - Chee-Kit Ng, Yu-Chun Lin, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou:
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems. 1-4 - Linqi Shi, Weixin Gai, Jichao Huang, Liangxiao Tang, Xiao Xiang:
A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. 1-4 - Razieh Abedi, Rouzbeh Kananizadeh, Amir Esmaili, Omeed Momeni, Payam Heydari:
A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS. 1-5 - Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng:
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. 1-4 - Tuan Minh Vo
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs. 1-4 - Arzu Ergintav, Frank Herzel, Dietmar Kissinger, Herman Jalli Ng:
An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation. 1-4 - Shahaboddin Ghajari, Mohammad Sharifkhani:
A Time-Interleaved 2b/Cycle SAR ADC with Background Offset Calibration. 1-4 - Antonio J. Ginés, Antonio Lopez-Angulo
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. 1-5 - Donald M. Johnson, Thomas P. Weldon:
A Clock-Tuned Discrete-Time Negative Capacitor Implemented Using Analog Samplers. 1-5 - Mahdi M. Khafaji, Corrado Carta
Analysis of a Modified Current Switching Cell for High-Speed Digital-to-Analog Converters. 1-5 - Bao Li, Long Zhao, Jiangfeng Wu, Yuhua Cheng:
Duty Cycle Distortion in Half-rate Nyquist DACs with Limited Output Bandwidth. 1-4 - Huiyu Duan, Guangtao Zhai, Xiongkuo Min
Perceptual Quality Assessment of Omnidirectional Images. 1-5 - Shaowei Xie, Yiling Xu, Qiaojian Qian, Qiu Shen, Zhan Ma, Wenjun Zhang:
Modeling the Perceptual Impact of Viewport Adaptation for Immersive Video. 1-5 - Ruidi Zheng, Xuchang Huangfu, Yule Sun, Lu Yu
Projection Deformation Based Motion Compensation for Panoramic Video. 1-5 - Tae-Ho Lee, Hyuk-Jae Lee:
Ambidextrous Virtual Keyboard Design with Finger Gesture Recognition. 1-4 - Gustavo Sanchez
High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos. 1-5 - Tejaswini Keragodu, Bhawna Tiwari, Nishtha, Pydi Bahubalindruni, João Goes
A Voltage Controlled Oscillator Using IGZO Thin-Film Transistors. 1-5 - Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps. 1-5 - Ramy N. Tadros, Peter A. Beerel:
A Robust and Self-Adaptive Clocking Technique for RSFQ Circuits - The Architecture. 1-5 - Shaofeng Guo, Zhenghan Lin, Runsheng Wang, Dongyuan Mao, Yangyuan Wang, Ru Huang:
Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method. 1-4 - Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. 1-5 - Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing. 1-5 - Heiner Giefers
Extending the POWER Architecture with Transprecision Co-Processors. 1-5 - Anil Kanduri, Mohammad Hashem Haghbayan, Amir M. Rahmani
Approximation for Run-time Power Management. 1-4 - Yan Xing, Ziji Zhang, Yiduan Qian, Qiang Li, Yajuan He:
An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application. 1-4 - Alberto Girolami, Federica Zonzini
Modal Analysis of Structures with Low-cost Embedded Systems. 1-4 - Tommaso Addabbo, Mauro Di Marco
Turbomachinery Clearance Monitoring Based on Passive Variable Reluctance Magnetic Sensors. 1-5 - Christian Kexel, Moritz Mälzer, Jochen Moll:
Guided Wave Based Acoustic Communications in Structural Health Monitoring Systems in the Presence of Structural Defects. 1-4 - Frederic Cegla
Coded excitation, motion and signal-to-noise ratio. 1-4 - Shohei Mita, Hiroo Sekiya
Analysis and Design of Wireless Power Transfer System with Asymmetrical Duty-Cycle Controlled Class-D ZVS Inverter. 1-5 - Long Wang, Dongsheng Yu, Ruidong Xu, Zongbin Ye, Herbert H. C. Iu, Tyrone Fernando
A Pulse Train Controlled Single-Input Dual-Output Buck Converter. 1-5 - Arunkumar Salimath, Giovanni Gonano, Edoardo Bonizzoni, Davide Luigi Brambilla, Edoardo Botti, Franco Maloberti:
Design Considerations for Integrated, High-Voltage DC-DC Converters. 1-5 - Abdullah M. Zyarah
On-Device Learning in Memristor Spiking Neural Networks. 1-5 - Nicholas D. Skuda
High-Level Simulation for Spiking Neuromorphic Computing Systems. 1-5 - Md. Munir Hasan, Jeremy Holleman:
Implementation of Linear Discriminant Classifier in 130nm Silicon Process. 1-5 - Vishal Saxena, Xinyu Wu, Kehan Zhu:
Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip. 1-5 - Arya Alex Rahimi, Huan Hu, Krishnamoorthy Sivakumar, Subhanshu Gupta:
Energy-Efficient Serialized Walsh-Hadamard Transform Based Feature-Extraction for Information-Aware Compressive Sensing. 1-5 - Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. 1-5 - Stefania Perri
Design of Real-Time FPGA-based Embedded System for Stereo Vision. 1-5 - Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. 1-5 - Jiayan Gan, Jun Zhou, Ning Wang:
A FPGA-based RO PUF with LUT-Based Self-Compare Structure and Adaptive Counter Time Period Tuning. 1-5 - Jiakun Li, Zhe Li, Chengbo Xue, Jingqi Zhang
A Fast Modular Inversion FPGA Implementation over GF(2m) using Modified x2n Unit. 1-5 - Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Massimo Poncino:
A Compact PV Panel Model for Cyber-Physical Systems in Smart Cities. 1-5 - Stefano Aldegheri, Nicola Bombieri, Nicola Dall'Ora
A Framework for the Design and Simulation of Embedded Vision Applications Based on OpenVX and ROS. 1-5 - Debayan Roy, Michael Balszun, Thomas Heurung, Samarjit Chakraborty
Multi-Domain Coupling for Automated Synthesis of Distributed Cyber-Physical Systems. 1-5 - Georges G. E. Gielen, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Nektar Xama
Methodology Towards Sub-ppm Testing of Analog and Mixed-Signal ICs for Cyber-Physical Systems. 1-4 - Stefano Buccelli, Jacopo Tessadori
Closed-loop electrophysiology: Past, present and future perspectives and applications. 1-5 - M. Frega, B. Mossink, K. Linda, J. Keller, Dirk Schubert
Brain-on-a chip technologies for investigating neuronal diseases: Toward precision medicine applications. 1-3 - Maxwell D. Murphy
Assessing Perturbations to Neural Spiking Response Dynamics Caused By Electrical Microstimulation. 1-5 - Gianluca Traversi, Francesco De Canio, Valentino Liberali
Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition. 1-4 - Milad Haghi Kashani, Reza Molavi, Shahriar Mirabbasi:
A Wide-Tunning-Range Low-Phase-Noise Colpitts Oscillator with Variable Capacitive Feedback. 1-5 - Milad Haghi Kashani, Reza Molavi, Hormoz Djahanshahi, Shahriar Mirabbasi:
On the Design of Vertical-Turn Solenoids for Magnetically Isolated Densely Integrated LC Oscillators. 1-5 - Faizan Ul Haq, Mikko Englund, Yury Antonov
Full-Duplex Wireless Transceiver Self-Interference Cancellation Through FD-SOI Buried-Gate Signaling. 1-5 - Anna C. Tasolamprou
Intercell Wireless Communication in Software-defined Metasurfaces. 1-5 - Tianye He, Runxi Zhang, Hui Yang, Jiefu Wang, Chunqi Shi:
A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications. 1-4 - Liheng Lou, Kai Tang, Zhongyuan Fang
A DDS-Driven ADPLL Chirp Synthesizer with Ramp-Interpolating Linearization for FMCW Radar Application in 65nm CMOS. 1-4 - Jinghang Liang, Duncan G. Elliott
Frequency Synthesis Based on A Novel Differential Locking Mechanism. 1-5 - Zhenwu Wang, Sijia Jiang, Hanjun Jiang, Baoyong Chi:
A K-Band Fractional-N Frequency Synthesizer With a Low Phase Noise LC VCO in 90nm CMOS. 1-4 - Mohammad Honarparvar, José M. de la Rosa, Frederic Nabki, Mohamad Sawan:
Design Considerations of MASH ΔΣ Modulators with GRO-based Quantization. 1-5 - Ankesh Jain
Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC. 1-5 - Marcel Runge, Friedel Gerfers:
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. 1-5 - Deng Luo, Milin Zhang, Zhihua Wang:
Design of A Low Noise Neural Recording Amplifier for Closed-loop Neuromodulation Applications. 1-4 - Lieuwe B. Leene, Michal Maslik, Peilong Feng, Katarzyna M. Szostak, Federico Mazza
Autonomous SoC for Neural Local Field Potential Recording in mm-Scale Wireless Implants. 1-5 - Natalie Butz, Utpal Kalita, Matthias Kuhl, Yiannos Manoli:
Active Charge Balancer with 6.6 to 40 V Quad-Rail Power Supply Compliance for Neural Stimulators. 1-4 - Jhao-Cheng Wu, Chia-Wei Wang, Yuan-Hao Huang, Hau-Tieng Wu, Po-Chiun Huang, Yu-Lun Lo:
A Portable Monitoring System with Automatic Event Detection for Sleep Apnea Level-IV Evaluation. 1-4 - Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang:
A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. 1-4 - Amirhossein Shahshahani, Sharmistha Bhadra, Zeljko Zilic:
A Continuous Respiratory Monitoring System Using Ultrasound Piezo Transducer. 1-4 - Karim Elmantawi, Nicholas Miscourides, Ermis Koutsos, Pantelis Georgiou
A 96-channel ASIC for sEMG Fatigue Monitoring with Compressed Sensing for Data Reduction. 1-5 - Palagani Yellappa, Ye Rim Lee, Jun Rim Choi:
Analysis of Coil Misalignment Issue in Resonance-based Wireless Power Transmission System for Implantable Biomedical Applications. 1-5 - Yu-Jin Lin, Chen-Wei Chuang, Chun-Yueh Yen, Sheng-Hsin Huang, Shuenn-Yuh Lee:
Smart Pet Clothing for Monitoring of Health and Mood. 1-4 - Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi
Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. 1-5 - Mengye Cai, Robert Sobot, Shahriar Mirabbasi:
A 32-μW Programmable Crystal-less Event-driven Receiver for Miniaturized Biomedical Implants. 1-4 - Jian Zhao, Jingna Mao, Tong Zhou, Longqiang Lai, Huazhong Yang, Bo Zhao:
An Auto Loss Compensation System for Non-contact Capacitive Coupled Body Channel Communication. 1-5 - Devdip Sen, John A. McNeill
Time-Domain-Based Measurement Technique for Pressure Measurement in a Wearable Wireless Sensor Patch. 1-5 - Harsh Durga Tiwari, Jae-Hyung Kim, Woon Hyun Cho:
Design and Implementation of complete wearable Low-Intensity Pulsed Ultrasound Therapeutic Device. 1-5 - Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu:
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. 1-4 - Elisa Donati
Deriving optimal silicon neuron circuit specifications using Data Assimilation. 1-5 - Omer Ceylan
Development of Hand-Held Point-of-Care Diagnostic Device for Detection of Multiple Cancer and Cardiac Disease Biomarkers. 1-5 - Sheung Lu
System Integration of IC chips for Lab-on-CMOS Applications. 1-5 - Reza Ranjandish
Current Overshoots and Undershoots in Electrical Stimulation: A Circuit-level Perspective of the Origin and Solutions. 1-4 - Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao, Peter G. M. Baltus:
Analysis of the Effect of PFD Sampling on Charge-Pump PLL Stability. 1-5 - Sebastian Bader, Maurits Ortmanns, Jens Anders
Nonlinear Energy-Efficient Noise-Aware Design of CMOS LC Tank Oscillators. 1-5 - Eugene Koskin, Dimitri Galayko, Elena Blokhina
Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs. 1-5 - Zherui Zhang, Heyi Li, Fan Yang, Haoyun Jiang, Junhua Liu, Huailin Liao:
A Digital Phase Noise Cancelling Scheme for Ring Oscillator-based Fractional-N ADPLL. 1-5 - Elena Blokhina
Reconstructing the Model of a Nonlinear MEMS Structure by the Example of a Piezoelectric Resonant Energy Harvester. 1-5 - Thomas P. Weldon, Patrick J. Kehoe, Killian K. Steer:
A Clock-Tuned Digital Memristor Emulator. 1-5 - Alberto Oliveri
Modeling and compensation of hysteresis and creep: The HysTool toolbox. 1-5 - Riccardo Trinchero
F-Domain Analysis of Linear Circuits with Time-Varying Parameters via Integral Equations. 1-5 - Shuo Wang, Hsiao-Dong Chiang:
Multi-Objective Look-Ahead Power Dispatch with Renewables: The User Preference Enabling Method and Theory. 1-5 - Di He, Xin Chen, Danping Zou, Ling Pei
An Improved Kernel Clustering Algorithm Used in Computer Network Intrusion Detection. 1-5 - Wanmai Yuan, Nuwan Ganganath, Chi-Tsun Cheng
Path Planning for Semi-Flocking-Controlled Mobile Sensor Networks on Mobility Maps. 1-5 - Kai-Yin Fok, Chi-Tsun Cheng
Accelerating 3D Printing Process Using an Extended Ant Colony Optimization Algorithm. 1-5 - Hong Xia, Wei Xing Zheng, Guanghui Wen:
Event-Based Containment Control of Multi-Agent Systems Without Velocity Measurements. 1-4 - Shidong Zhai, Wei Xing Zheng:
Survival of All Agents Through Cooperative Interactions in Generalized Verhulst-Lotka-Volterra Systems. 1-4 - Shuhei Hashimoto, Yoko Uwate, Yoshifumi Nishio
Synchronization Phenomena of Chaotic Circuit Networks with Distributed Hub Including Positive and Negative Coupling. 1-5 - Jiali Dong, Fanghua Ye
Identifying Influential Nodes in Complex Networks via Semi-Local Centrality. 1-5 - Bandhit Suksiri, Masahiro Fukumoto:
A Computationally Efficient Wideband Direction-of-Arrival Estimation Method for L-Shaped Microphone Arrays. 1-5 - Sheng Zhang, Wei Xing Zheng:
Joint adaptive step-size and zero-attractor parameters for l0-NLMS algorithm. 1-4 - Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
Efficient and Lightweight Quantized Compressive Sensing using μ-Law. 1-5 - Saman S. Abeysekera:
Least-Squares Multiple Frequency Estimation using Recursive Regression Sum of Squares. 1-5 - Achanna Anil Kumar, Dongye Zhang, Zhiping Lin, Sirajudeen Gulam Razul
Direction finding and multipath mitigation using single antenna. 1-5 - Jeffrey O. Coleman:
Equiripple-Stopband Multiplierless FIR Filters by Chebyshev Sharpening of Two-Sample Averaging. 1-4 - Takao Hinamoto, Akimitsu Doi, Wu-Sheng Lu:
Generalized Direct-Form II Realization of 2-D Separable-Denominator Digital Filters. 1-5 - Shun-Min Chang, Chia-Chi Tsai
A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow for E-mirror Applications. 1-5 - Manuel Eggimann, Christelle Gloor, Florian Scheidegger
Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS. 1-5 - Tiecheng Sun, Shuaicheng Liu
A 3D Descriptor based on Local Height Image. 1-5 - Mitsuru Kawamoto, Ken Okayama, Takashi Okuma
Work Analysis Using Human Operating Data Based on a State Transition Model. 1-5 - Matteo Testa, Tiziano Bianchi, Enrico Magli:
On the secrecy of compressive cryptosystems under finite-precision representation of sensing matrices. 1-4 - Trong-Thuc Hoang
High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC. 1-5 - Alex Marchioni
Disturbance Rejection With Rakeness-based Compressed Sensing: Method and Application to Baseline/Powerline Mitigation in ECGs. 1-5 - Gian Domenico Licciardo
Design Criteria for Real-time Processing of HW Gabor Filters in Visual Search. 1-5 - Juan Yepez
An FPGA-based Closed-loop Approach of Angular Displacement for a Resolver-to-Digital-Converter. 1-4 - Aditya Galada, Jianmin Zhang, Yong Kiang Yeo, Wee Ser, Zhiping Lin, Doris Tan, Yvonne Chow, Swapna Tony, Jaclyn Chow, David Chee-Guan Foo:
ECG Signal Processing and Analysis for Data Arising from Rehab Patients Doing Exercises. 1-5 - Mao-Jan Lin, Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen
A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor. 1-5 - Kevin Gilboy, Khaled Sayed, Niteesh Sundaram, Kara Bocan, Natasa Miskov-Zivanov:
A Faster DiSH: Hardware Implementation of a Discrete Cell Signaling Network Simulator. 1-5 - Zhe Su, Hong Chen, Zhihua Wang:
A Trajectory Measurement System and Algorithms for Unicondylar Knee Replacement Surgery. 1-5 - Sameh Sherif
Electroporation Improvement of Leukemic Cells Using Dielectrophoresis Technique. 1-4 - Dwaipayan Biswas
CORDIC Framework for Quaternion-based Joint Angle Computation to Classify Arm Movements. 1-5 - Ruochong Zhang
Noninvasive Glucose Measurement by Microwave Biosensor with Accuracy Enhancement. 1-4 - Abdulwadood A. Al-Ali
Design and Implementation of a Bio-Impedance Analyzer Based on the Kramers-Kronig Transform. 1-5 - Salim Lahmiri, Mounir Boukadoum:
Improved Electromyography Signal Modeling for Myopathy Detection. 1-4 - Alessandro Bevilacqua
A novel algorithm to detect the baseline value of a time signal in Dynamic Contrast Enhanced-Computed Tomography. 1-4 - Alessandro Bevilacqua
Analysis of the effects of fitting errors of DCE-CT signals on perfusion parameters. 1-5 - Jun Ogata, Koichi Ichige:
Fast Intra Mode Decision Method Based on Outliers of DCT Coefficients and Neighboring Block Information for H.265/HEVC. 1-5 - Yi Zhang, Yucheng Sun
Adaptive Weighted Averaged Template Matching Prediction for Intra Coding. 1-4 - Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC. 1-5 - Yan Huang, Li Song, Rong Xie, Zhengyi Luo, Xiangwen Wang:
An MCMC based Efficient Parameter Selection Model for x265 Encoder. 1-5 - Yushan Zheng, Peng Xu, Jun Sun, Zongming Guo:
Gradient Based Interpolation for Intra Angular Prediction in HEVC. 1-5 - Haibing Yin, Dong Li, Yu Lu, Yang Zhou:
Frame Level Quantization Control with Temporal Distortion Propagation Model for Video Coding. 1-5 - Ji Hun Jang, Chae-Eun Rhee:
Encoder-friendly Global-view-depth for Free Viewpoint Video. 1-5 - Vladimir Afonso, Altamiro Amadeu Susin, Murilo R. Perleberg
Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC. 1-5 - Daniel García-Lesta
Shannon Entropy as Background Dynamics Estimator In Foreground Detector Algorithms. 1-4 - Yucheng Zhu, Guangtao Zhai, Wenhan Zhu, Jiantao Zhou:
An Image Augmentation Method for Quality Assessment Database. 1-5 - Ismael Seidel, Vanio Rodrigues Filho, Luciano Volcan Agostini, José Luís Güntzel:
Coding- and Energy-Efficient FME Hardware Design. 1-5 - Jahanzeb Ahmad, Alexander Warren:
FPGA based Deterministic Latency Image Acquisition and Processing System for Automated Driving Systems. 1-5 - Chung-Yan Chih, Sih-Sian Wu, Jan P. Klopp, Liang-Gee Chen:
Accurate and Bandwidth Efficient Architecture for CNN-based Full-HD Super-Resolution. 1-5 - Panu Sjövall
FPGA-Powered 4K120p HEVC Intra Encoder. 1-5 - Zhi-Yi Lin, Jia-Lin Chen, Liang-Gee Chen:
A 65 fps Full-HD Hardware Implementation of HOG, HOF, MBHx, and MBHy for Real-Time Action Recognition. 1-5 - Juhyoung Lee, Changhyeon Kim, Sungpill Choi, Dongjoo Shin, Sanghoon Kang, Hoi-Jun Yoo:
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices. 1-5 - Chih-Ting Liu, Yi-Heng Wu, Yu-Sheng Lin, Shao-Yi Chien:
Computation-Performance Optimization of Convolutional Neural Networks with Redundant Kernel Removal. 1-5 - Ioannis Galanis, Priyaa Gurunathan, Dona Burkard, Iraklis Anagnostopoulos
Weather-based road condition estimation in the era of Internet-of-Vehicles (IoV). 1-5 - Sai Saketh Nandan Perala, Ioannis Galanis, Iraklis Anagnostopoulos
Fog Computing and Efficient Resource Management in the era of Internet-of-Video Things (IoVT). 1-5 - Kien Trinh Quang
Novel Time-Based Sensing Scheme for STT-MRAMs. 1-5 - Artur Antonyan
Embedded MRAM Macro for eFlash Replacement. 1-4 - Runze Han, Peng Huang, Yachen Xiang, Chen Liu, Zhekang Dong, Zhiqiang Su, Yongbo Liu, L. Liu, Xiaoyan Liu, Jinfeng Kang:
A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient. 1-4 - Hao-Chiao Hong
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications. 1-4 - Hao Jiang, Kevin Yamada, Zizhe Ren, Thomas Kwok, Fu Luo, Qing Yang, Xiaorong Zhang, J. Joshua Yang
Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array. 1-4 - Melika Payvand, Lorenz K. Müller, Giacomo Indiveri:
Event-based circuits for controlling stochastic learning with memristive devices in neuromorphic architectures. 1-5 - Denys R. B. Ly
Role of synaptic variability in spike-based neuromorphic circuits with unsupervised learning. 1-5 - Olga Krestinskaya
Analog Backpropagation Learning Circuits for Memristive Crossbar Neural Networks. 1-5 - Valerio Milo
Brain-inspired recurrent neural network with plastic RRAM synapses. 1-5 - Pietro Burrascano, Stefano Laureti
Range Sidelobes Reduction for Pulse-Compression NDT based on Reactance Transformation. 1-5 - Jorge R. Salas Avila
A multi-frequency NDT system for imaging and detection of cracks. 1-4 - Luca De Marchi
Piezo-transducer's shape design as a pre-processing tool in guided wave inspections. 1-5 - Thomas Abbey, Alexandru Serb, Nikolaos Vasilakis, Loukas Michalas
An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation. 1-4 - Mi Zhou, Zhuochao Sun
A Fast Transient Response DC-DC Converter with an Active Compensation Capacitor Module. 1-5 - Saad Bin Nasir
A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. 1-5 - Yongjie Jiang, Muhammad Swilam, Sita Asar, Ayman A. Fayed
An Accurate Sense-FET-based Inductor Current Sensor with Wide Sensing Range for Buck Converters. 1-4 - Dedong Ding, Hesheng Lin, Binjie Liu, Min Zhang
A Step-Up Charge Pump with High Integration and Full-Coverage Voltage Conversion Ratio. 1-4 - Younis Allasasmeh, Stefano Gregori
Fast-Startup High-Efficiency Tripler Charge Pump in Standard 0.18-μm CMOS Technology. 1-5 - Peter A. Beerel, Massoud Pedram:
Opportunities for Machine Learning in Electronic Design Automation. 1-5 - Arman Iranfar, William Andrew Simon, Marina Zapater
A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs. 1-5 - Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frédéric Kaplan
Deep Learning for Logic Optimization Algorithms. 1-4 - Manuele Rusci, Lukas Cavigelli, Luca Benini
Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity? 1-5 - Jinhang Choi
Stochastic Functional Verification of DNN Design through Progressive Virtual Dataset Generation. 1-5 - Mário Lopes Ferreira
Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator. 1-5 - Muluken Hailesellasie, Syed Rafay Hasan, Faiq Khalid, Falah Awwad, Muhammad Shafique
FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements. 1-5 - Vatistas Kostalampros, Konstantinos Maragos, George Lentaris, Dimitrios Soudris
Carrier Phase Recovery of 64 GBd Optical 16-QAM Using Extensive Parallelization on an FPGA. 1-5 - Guilherme F. Weidle, Felipe Viel
A Hardware Accelerator for Anisotropic Diffusion Filtering in FPGA. 1-5 - Ludovica Bozzoli, Luca Sterpone
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs. 1-5 - Tae Woo Oh, Seong-Ook Jung:
SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. 1-4 - Ling Qiu, Yingjie Lao:
A Systematic Method for Approximate Circuit Design Using Feature Selection. 1-5 - Yonghwi Kwon
Transient Clock Power Estimation of Pre-CTS Netlist. 1-4 - Suganthi Venkatachalam, Hyuk Jae Lee, Seok-Bum Ko
Power Efficient Approximate Booth Multiplier. 1-4 - Sheng Ma, Hongyi Lu, Libo Huang, Li Shen, Yang Guo, Zhiying Wang, Wenliang Xue:
Adaptive VC Partitioning for NoCs in GPGPUs. 1-5 - Paul Bogdan, Massoud Pedram:
Toward Enabling Automated Cognition and Decision-Making in Complex Cyber-Physical Systems. 1-4 - Victor Javier Kartsch, Simone Benatti
Smart Wearable Wristband for EMG based Gesture Recognition Powered by Solar Energy Harvester. 1-5 - Charis Basetas, Nikos Temenos, Paul P. Sotiriadis
Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance. 1-5 - Yann Donnelly
High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller. 1-5 - Dmytro Cherniak, Luigi Grimaldi, Carlo Samori
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. 1-5 - Ioannis L. Syllaios:
Hybrid ΔΣ Programmable Phase/Frequency Detector for IoT Chipsets. 1-4 - Stefano Capra
A Digitally-Controlled Ring Oscillator in 28 nm CMOS technology. 1-5 - Bing Li, Chuang Li, Wei Wang, Jia Liu, Wen-Jun Liu, Qian Yang, Wen Bin Ye:
An Energy-Efficient 13-bit Zero-Crossing ΔΣ Capacitance-to-Digital Converter with 1 pF-to-10 nF Sensing Range. 1-5 - Yanquan Luo, Liang Qi, Ankesh Jain
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch. 1-5 - Xi Yang, Hae-Seung Lee:
Design of a 6th-order Continuous-time Bandpass Delta-Sigma Modulator with 250 MHz IF, 25 MHz Bandwidth, and over 75 dB SNDR. 1-5 - Debajit Basak, Sarthak Kalani
An On-Chip Static and Dynamic DAC Error Correction Technique for High Speed Multibit Delta-Sigma Modulators. 1-5 - Jiazuo Chi, Ankesh Jain
Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications. 1-4 - José R. de Oliveira-Neto
Hardware Architectures for Computing 8-Point Cosine Number Transform. 1-5 - Freddy A. Pinto-Benel, Manuel Blanco-Velasco
Comparing the Wavelet OFDM and Windowed OFDM data rate for in-home PLC. 1-5 - Ruijie Zhao, Xiaoping Lai, Zhiping Lin:
An Iterative Reweighted Minimax Algorithm for the Design of FRM-based Two-channel QMF Banks. 1-5 - Gordana Jovanovic-Dolecek
Improving Comb Alias Rejection Using Modified Cosine Filters. 1-4 - Xiaoming Chen, Michael T. Niemier, Xiaobo Sharon Hu
Nonvolatile Lookup Table Design Based on Ferroelectric Field-Effect Transistors. 1-5 - Evelyn T. Breyer
Demonstration of versatile nonvolatile logic gates in 28nm HKMG FeFET technology. 1-5 - Bi Wang, Zhaohao Wang, Kaihua Cao, Youguang Zhang, Yuanfu Zhao, Weisheng Zhao:
Radiation hardening design for spin-orbit torque magnetic random access memory. 1-4 - Chihiro Matsui, Ken Takeuchi:
3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage. 1-5 - Ning Qiao, Giacomo Indiveri:
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems. 1-5 - Amirreza Yousefzadeh, Garrick Orchard, Evangelos Stromatias, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network. 1-5 - Nan Zheng, Pinaki Mazumder:
A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks. 1-5 - Jennifer Hasler, Sahil Shah:
Enabling Embedded Learning and Classification implemented on SoC FPAA devices. 1-5 - Benoit Larras, Paul Chollet, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel
A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS. 1-4 - Dong Liu, Xi Zhang, Chi K. Tse
Effect of Malware Spreading on Propagation of Cascading Failure in Cyber-Coupled Power Systems. 1-4 - Jie Zhang, Jiajing Wu, Yongxiang Xia, Fanghua Ye
Measuring Cohesion of Software Systems Using Weighted Directed Complex Networks. 1-5 - Ashleigh Ballantyne, Nicholas Lawrance, Michael Small
Fault prediction and modelling in transport networks. 1-5 - Yoko Uwate, Thomas Ott, Yoshifumi Nishio
Producing Complex Networks Using Coupled Oscillatory Circuits with Evolutionary Connections. 1-5 - Xiongrui Xu, Zhihai Rong, Chi Kong Tse
Bounded Rationality Optimizes the Performance of Networked Systems in Prisoner's Dilemma Game. 1-5 - Hengwei Yu, Mingyi Chen, Chundong Wu, Kea-Tiong Tang, Guoxing Wang:
A Batteryless and Single-Inductor DC-DC Boost Converter for Thermoelectric Energy Harvesting Application with 190mV Cold-Start Voltage. 1-4 - Nanqi Liu
A Transient-Enhanced Fully-Integrated LDO Regulator for SoC Application. 1-5 - Yuanqing Huang, Yan Lu, Franco Maloberti, Rui Paulo Martins:
A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning. 1-5 - Xin Ming, Jia-Hao Zhang, Chun-qi Zhang, Li Hu, Yao Qin, Shaowei Zhen, Bo Zhang
A Capacitor-less LDO With Fast-transient Error Amplifier and Push-pull Differentiator. 1-5 - Mahmoud A. Khalil
Low-ripple PFM Buck Converter Employing Background Calibration. 1-4 - Shuai Huo, Dong Liu, Feng Wu, Houqiang Li:
Convolutional Neural Network-Based Motion Compensation Refinement for Video Coding. 1-4 - Zhenghui Zhao, Shiqi Wang
CNN-Based Bi-Directional Motion Compensation for High Efficiency Video Coding. 1-4 - Jun-Hao Hu, Wen-Hsiao Peng
Reinforcement Learning for HEVC/H.265 Intra-Frame Rate Control. 1-5 - Hao Wang, Li Song, Rong Xie, Zhengyi Luo, Xiangwen Wang:
Masking Effects Based Rate Control Scheme for High Efficiency Video Coding. 1-5 - Shanshe Wang, Junru Li, Shiqi Wang
A Frame Level Rate Control Algorithm For Screen Content Coding. 1-4 - Basak Sakcak
Using motion primitives to enforce vehicle motion constraints in sampling-based optimal planners. 1-5 - Ray Lattarulo
A Speed Planner Approach Based On Bézier Curves Using Vehicle Dynamic Constrains and Passengers Comfort. 1-5 - Gábor Rödönyi:
Extensions of ACC Technology Toward Ad Hoc Platooning with Guaranteed String Stability and Improved Tracking Performance. 1-5 - Ernest Benedito, Arnau Dòria-Cerezo
Traffic flow-oriented design and analysis of an adaptive cruise control system. 1-5 - Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang:
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. 1-5 - Mauro Olivieri
Characterizing noise pulse effects on the power consumption of idle digital cells. 1-5 - Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski:
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. 1-5 - Daijoon Hyun, Jaewoo Seo, Youngsoo Shin:
Library Optimization for Near-Threshold Voltage Design. 1-4 - Daniele Jahier Pagliari
Application-Driven Synthesis of Energy-Efficient Reconfigurable-Precision Operators. 1-5 - Alex Marchioni
Resource Redistribution in Internet of Things applications by Compressed Sensing: A Survey. 1-5 - Valerio Cambareri
Correlation-Aware Recovery of Compressible and Localized Signals. 1-5 - Xiao Wang, Jie Zhang, Tao Xiong, Trac Duy Tran, Sang Peter Chin, Ralph Etienne-Cummings:
Using Deep Learning to Extract Scenery Information in Real Time Spatiotemporal Compressed Sensing. 1-4 - Bathiya Senevirathna, Pamela Abshire:
Spatio-temporal compressed sensing for real-time wireless EEG monitoring. 1-5 - Andrea Massa
Compressive Sensing as Applied to Antenna Arrays: Synthesis, Diagnosis, and Processing. 1-5 - Hoda Fares
Screen Printed Tactile Sensing Arrays for Prosthetic Applications. 1-4 - Reza Kamali-Sarvestani, Brandon Wright, Kawin Triyasakorn:
A Flexible Printed Radio Frequency Direction Finder Using Carbon Nanotube Field Effect Transistors. 1-4 - Philippe Descent, Ricardo Izquierdo, Christian Fayomi:
Printing of temperature and humidity sensors on flexible substrates for biomedical applications. 1-4 - Boyang Lyu, Meera Punjiya, Zimple Matharu, Sameer Sonkusale:
An improved pH mapping bandage with thread-based sensors for chronic wound monitoring. 1-4 - Tong Ge, Zhou Jia, Joseph S. Chang:
Flexible Hybrid Electronics: Review and Challenges. 1-5 - Yaqi Wang, Jun Lin, Zhongfeng Wang:
A New Soft-input Hard-output decoding algorithm for Turbo Product Codes. 1-5 - Xinmiao Zhang, Michael O'Sullivan
Ultra-Compressed Three-Error-Correcting BCH Decoder. 1-5 - Arul K. Subbiah
Area-effcient re-encoding scheme for NAND Flash Memory with multimode BCH Error correction. 1-5 - Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin
Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. 1-5 - Ningyuan Yang, Shusen Jing, Anlan Yu, Xiao Liang, Zaichen Zhang, Xiaohu You
Reconfigurable Decoder for LDPC and Polar Codes. 1-5 - Johannes Wagner, Maurits Ortmanns, José M. de la Rosa:
Man or Machine - Design Automation of Delta-Sigma Modulators. 1-5 - Shanthi Pavan, Siddharth Baskaran:
What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator? 5- - Hajime Shibata:
Thermal noise limits - ΔΣ vs. pipeline ADCs. 1 - Arindam Sanyal, Shaolan Li, Nan Sun:
Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC. 1-5 - Changsok Han, Beomsoo Park, Nima Maghari:
Can SMASH Smash MASH? 1-5 - Gagan Deep Singh
A CMOS Inverter-Like Class-D/E Power Amplifier with No RF-Choke and No Dead-Time Requirement. 1-4 - Imon Mondal, Nagendra Krishnapura:
Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load. 1-5 - Praveen Kumar Venkatachala, Spencer Leuenberger, Ahmed ElShater, Calvin Lee, Yang Xu, Bohui Xiao, Michael Oatman, Un-Ku Moon:
Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit. 1-5 - Soheil Ziabakhsh, Ghyslain Gagnon
An All-Digital High-Resolution Programmable Time-Difference Amplifier Based on Time Latch. 1-5 - Guido Magazzù, Gabriele Ciarpi
Design of a radiation-tolerant high-speed driver for Mach Zender Modulators in High Energy Physics. 1-5 - Nilan Udayanga, Arjuna Madanayake
Continuous-time Analog Computing Circuits for Solving The Electromagnetic Wave Equation. 1-5 - Alessandro Truppi, Carlo Samori
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. 1-4 - Leo Filippini
A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion. 1-5 - Jose Cisneros-Fernández
A Compact Switched-Capacitor Multi-Bit Quantizer for Low-Power High-Resolution Delta-Sigma ADCs. 1-5 - Spencer Leuenberger, Praveen Kumar Venkatachala, Ahmed ElShater, Michael Oatman, Calvin Lee, Bohui Xiao, Un-Ku Moon:
An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs. 1-5 - Ali Rezapour, Hossein Shamsi, Hamed Abbasizadeh, Kang-Yoon Lee:
Low Power High Speed Dynamic Comparator. 1-5 - Francesco De Canio, Gianluca Traversi:
Temperature Sensor with Process and Mismatch Auto-Compensation Technique in 28 nm CMOS. 1-5 - Qiwu Luo, Yigang He, Yichuang Sun, Lifen Yuan:
Time-effective Fault Diagnosis Algorithms for Analog and Mixed-signal Circuits Using Sparsity-aware Multi-class Relevance Vector Machine. 1-4 - Meng Zhao, Qiancheng Zhao, Zhongjian Chen, Wengao Lu, Yacong Zhang, Guizhen Yan:
A Low-Noise High-G Closed-Loop Capacitive Accelerometer Using DC-Blocking Technique for Reduction of Power Dissipation. 1-5 - Natalie S. Killeen
Design of a Wideband Bandpass Stacked HBT Distributed Amplifier in InP. 1-5 - Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Mismatch Compensation Technique for Inverter-Based CMOS Circuits. 1-5 - Lukas Langhammer, Roman Sotner
Fully-Differential Universal Frequency Filter with Dual-Parameter Control of the Pole Frequency and Quality Factor. 1-5 - Saina Asefi, Alireza Saberkari, Herminio Martínez-Garcia, Eduard Alarcón:
Low-Quiescent Current Class-AB CMOS LDO Voltage Regulator. 1-4 - Qian Ding, Benjamin J. Fletcher, Terrence S. T. Mak:
Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems. 1-5 - Stefano Perticaroli, Danilo Ruscio, Filippo Neri, Thomas Brauner, Eric De Mey:
Mitigation technique for non-linear DC-shift induced by power supply noise in a 28 nm BGR reference. 1-4 - Jan Dvorak, Zuzana Polesakova, Jan Jerabek
Non-Integer-Order Low-Pass Filter with Electronically Controllable Parameters. 1-5 - Alexander Serb
High-sensitivity memristor-based threshold detection. 1-4 - Laude Fernandez, Andres Amaya, Elkim Roa
A 0.007mm2 50mA Three-Stage Fully-Integrated Capacitor-Less Low-Dropout Regulator. 1-4 - Qadeer A. Khan, Saurabh Saxena, Abirmoya Santra:
Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier. 1-5 - Norbert Herencsar
A Novel Pseudo-Differential Integer/ Fractional-Order Voltage-Mode All-Pass Filter. 1-5 - Youngmin Kim, Pilsung Jang, Joongseok Lim, Won Ko, Seungchan Heo, Jongwoo Lee, Thomas Byunghak Cho:
A Ka-band Phase Shifting Low Noise Amplifier with Gain Error Compensation for 5G RF beam forming array using 14nm FinFET CMOS. 1-4 - Peeyoosh Mirajkar, Jagdish Chand, Sankaran Aniruddhan, Srinivas Theertham:
Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature. 1-5 - Nusrat Jahan
A K-Band VCO Employing High Active Q-factor Defected Ground Structure Resonator in 0.18pm CMOS Technology. 1-5 - Paula C. Pereira
Generic Model for Multi-Phase Ring Oscillators. 1-4 - Matthew Schormans, Virgilio Valente, Andreas Demosthenous
Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation. 1-4 - João Santos, Diogo Brito
Radio Pulsar Signal Generator. 1-4 - Luis Irio, Rodolfo Oliveira
Characterization of the residual self-interference power in full-duplex wireless systems. 1-5 - Andrea De Marcellis, Marco Faccio
A 0.35μm CMOS 200kHz-2GHz Fully-Analogue Closed-Loop Circuit for Continuous-Time Clock Duty-Cycle Correction in Integrated Digital Systems. 1-5 - Wei-Wei Chen, Shang-De Yang, Kuang-Wei Cheng:
A 1.2 V 490 μW Sub-GHz UWB CMOS LNA with Current Reuse Negative Feedback. 1-4 - Hossein Noori
A 1.8 GHz-2.4 GHz SAW-Less Reconfigurable Receiver Frontend RFIC in 65nm CMOS RF SOI. 1-4 - Mohammad Hassan Montaseri, Janne Aikio
Optimum Number of Transistors in Stacked CMOS Millimeter-Wave Power Amplifiers. 1-4 - Zhe Liu, Liheng Lou, Zhongyuan Fang
A DLL-based Configurable Multi-Phase Clock Generator for True-Time-Delay Wideband FMCW Phased-Array in 40nm CMOS. 1-4 - M. V. Praveen, Nagendra Krishnapura:
An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters. 1-5 - Nevena Rakuljic, Carroll Speir, Eric Otte, Jeff Bray, Corey Petersen, Gabriele Manganaro:
In-situ nonlinear calibration of a RF signal chain. 1-5 - Luis Hernández, Enrique Prefasi
VCO-ADC Resolution Enhancement Using Maximum Length Sequences. 1-4 - Mahmoud A. Khalil
Design Trade-offs in Buck Converters for Low-Energy Wireless Transceivers. 1-4 - Osamu Watanabe, Hiroyuki Kobayashi, Hitoshi Kiya:
Lossless Two-Layer Coding using Histogram Packing Technique for HDR Images. 1-5 - Luciano Almeida Braatz, Bruno Zatt, Daniel Palomino
High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design. 1-5 - Anderson Martins, Wagner Penny
Configurable Cache Memory Architecture for Low-Energy Motion Estimation. 1-5 - Nikolaos Passalis, Anastasios Tefas
Efficient Camera Control using 2D Visual Information for Unmanned Aerial Vehicle-based Cinematography. 1-5 - Hyunmin Jung, Hyuk-Jae Lee, Chae-Eun Rhee:
Ray-space360: An extension of ray-space for omnidirectional free viewpoint. 1-5 - Whan Choi, Kyung-Rae Kim, Chang-Su Kim
Reliable Depth-of-Field Rendering Using Estimated Depth Maps. 1-4 - Chun-Wei Chen, Wen-Yuan Hsiao, Ting-Yu Lin, Jonas Wang, Ming-Der Shieh:
Fast Keyframe Selection and Switching for ICP-based Camera Pose Estimation. 1-4 - Anahita Shojaei-Hashemi, Panos Nasiopoulos, James J. Little, Mahsa T. Pourazad:
Video-based Human Fall Detection in Smart Homes Using Deep Learning. 1-5 - Damir Hamidovic
Modeling of an IQ RF-DAC with error-free LO-switching. 1-5 - Saqib Mohamad, Moaaz Ahmed
Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique. 1-4 - Manuela La Rosa, Giovanni Sicurella, Donata Nicolosi, Roberto Giorgio Bardelli:
Time to Digital Converter Based on a Ring Oscillator with Even Number of Non-Inverting Elements. 1-4 - Amir Babaie-Fishani, Dries Vercaemer, Johan Raman, Pieter Rombouts
Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping. 1-5 - Seyed Alireza Zahrai, Marina Zlochisti, Nicolas Le Dortz, Marvin Onabajo:
Design Considerations and Experimental Verification of a 10.5mW 1GS/s Hybrid ADC for Portable Wireless Devices. 1-5 - Bao Li, Long Zhao, Jiangfeng Wu, Yuhua Cheng:
A 12GS/s 6-bit DAC with 4-2 Segmentation in 40nm CMOS. 1-5 - Meiyi Zhou
A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator. 1-5 - Wei Tung, Shu-Chuan Huang:
An Energy-Efficient 11-bit 10-MS/s SAR ADC with Monotonie Switching Split Capacitor Array. 1-5 - Tianli Zhang, Yuefeng Cao
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. 1-5 - Marios Neofytou, Meiyi Zhou
A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. 1-5 - Zhaoming Ding, Xiong Zhou, Qiang Li:
Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching. 1-4 - Charis Basetas, Nikos Temenos, Paul P. Sotiriadis
An Efficient Hardware Architecture for the Implementation of Multi-Step Look-Ahead Sigma-Delta Modulators. 1-5 - Hao Meng, Randall L. Geiger, Degang Chen:
A High Constancy Rail-to-rail Level Shift Generator for SEIR-based BIST circuit for ADCs. 1-5 - Saihua Xu, Jun Wei Lee:
A Digital Technique for Calibrating and Correcting Nonlinearities in Current-Steering DACs. 1-5 - Harneet Singh Khurana, Anantha P. Chandrakasan, Hae-Seung Lee:
Recode then LSB-first SAR ADC for Reducing Energy and Bit-cycles. 1-5 - Jui-Hsiang Tsai, Yi-Chia Chen, Yu-Te Liao
A Power-efficient Bidirectional Potentiostat-based Readout IC for Wide-range Electrochemical Sensing. 1-5 - Gerardo Molina Salgado
Behavioral Modeling of SAR ADCs in Simulink. 1-5 - Yang Zhang, Daxiang Li, Kong-Pang Pun:
Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator. 1-4 - Han Le Duc, Van-Phuc Hoang
Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands. 1-4 - Calvin Lee, Spencer Leuenberger, Praveen Kumar Venkatachala, Ahmed ElShater, Michael Oatman, Bohui Xiao, Un-Ku Moon:
A Power Efficient SAR Algorithm for High Resolution ADCs. 1-5 - Shravan K. Chaganti
A low-cost jitter separation and ADC spectral testing method without requiring coherent sampling. 1-5 - Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu:
A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. 1-5 - Mehdi Nasrollahpour, Sotoudeh Hamedi-Hagh:
Extra Bit Generation for High-Speed Time-Based Flash ADCs in 65nm CMOS. 1-5 - Boyu Shui, Matthias Keller, Matthias Kuhl, Yiannos Manoli:
A 70.8 dB 0.0045 mm2 Low-power Continuous-Time Incremental Delta-Sigma Modulator for Multi-Site Neural Recording Interfaces. 1-4 - Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang:
A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. 1-5 - Manxin Li, Yongzhen Chen, Fan Ye
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. 1-4 - Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti:
A Timing Skew Calibration Method for Time-Interleaved FATI ADCs. 1-5 - Jovan Mitrovic, Yiqiao Zhang, Zeljko Ignjatovic:
Predictive Successive Approximation ADC. 1-5 - Mohammed A. Eldeeb, Yehya H. Ghallab, Yehea Ismail, Hassan El-Ghitani:
Fully Integrated Mixed Mode Interface Circuit in 65 nm CMOS for Leukemia Detection and Classification. 1-5 - Bing Li, Ji-Ping Na, Wei Wang, Jia Liu, Wen-Jun Liu, Qian Yang, Wen Bin Ye:
A 480 fJ/conversion-step 13-bit Resistive Sensor Readout IC with a 1%/V Power Supply Sensitivity. 1-5 - Rafel Perelló-Roig
Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit. 1-5 - Nuwan Ganganath, Wanmai Yuan, Chi-Tsun Cheng
Territorial Marking for Improved Area Coverage in Anti-Flocking-Controlled Mobile Sensor Networks. 1-4 - Martin Gantier, Melpomeni Kalofonou, Chris Toumazou:
A trapped charge compensation scheme for ISFET based translinear circuits. 1-5 - Mingzheng Duan, Wei Xu, Xiaopeng Zhong, Moaaz Ahmed
A Dual-mode Flow Measurement System for Large Sensing Range with High Accuracy. 1-5 - Mansour Taghadosi
Integrated Stretch Processed S-Band Digital Radar System. 1-5 - Foad Arvani, Tony Chan Carusone
Direct Time-of-Flight TCSPC Analytical Modeling Including Dead-Time Effects. 1-4 - Claudio Accarino, Mohammed Al-Rawhani, Yash Diptesh Shah, Dzmitry Maneuski, Srinjoy Mitra, Craig Buttar, David R. S. Cumming:
Low Noise and High Photodetection Probability SPAD in 180 nm Standard CMOS Technology. 1-4 - Maximilian P. R. Löhr, Heiko Neumann:
Contrast Detection in Event-Streams from Dynamic Vision Sensors with Fixational Eye Movements. 1-5 - Zhaofeng Huang, Yuze Niu, Wengao Lu, Guangyi Chen, Yi Li, Shengdong Zhang
A 16-bit Single-Slope based Pixel-level ADC for 15μm-pitch 640×512 MWIR FPAs. 1-5 - Daniel García-Lesta
Impact of Analog Memories Non-Idealities on the Performance of Foreground Detection Algorithms. 1-5 - Gustavo M. S. Nunes
Color Tone-Mapping Circuit for a Focal-Plane Implementation. 1-5 - Shiting Li, Wenbin Ye, Huawei Liang, Xiaofang Pan
K-SVD Based Denoising Algorithm for DoFP Polarization Image Sensors. 1-5 - Deval Samirbhai Mehta, Shoushun Chen:
A Star Pattern Recognition Technique Based on the Binary Pattern Formed from the FFT Coefficients. 1-5 - Xutong Ren, Mading Li, Wen-Huang Cheng, Jiaying Liu
Joint Enhancement and Denoising Method via Sequential Decomposition. 1-5 - Nikolaos Papandreou, Abu Sebastian
Exploiting the non-linear current-voltage characteristics for resistive memory readout. 1-5 - Georgios Papandroulidakis
Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates. 1-5 - Nicola Lupo, Edoardo Bonizzoni, Eduardo Pérez, Christian Wenger, Franco Maloberti:
An Approximated Verilog-A Model for Memristive Devices. 1-5 - Ashwani Kumar, Mukul Sarkar, Manan Suri:
OxRAM Resistive Switching for DR Improvement. 1-5 - Thanasin Bunnam
An Excitation Time Model for General-purpose Memristance Tuning Circuit. 1-5 - Bodo Rueckauer
Conversion of analog to spiking neural networks using sparse temporal coding. 1-5 - Raphaela Kreiser, Matteo Cartiglia, Julien N. P. Martel, Jörg Conradt, Yulia Sandamirskaya:
A Neuromorphic Approach to Path Integration: A Head-Direction Spiking Neural Network with Vision-driven Reset. 1-5 - Myo Tun Aung, Rodney Teo, Garrick Orchard:
Event-based Plane-fitting Optical Flow for Dynamic Vision Sensors in FPGA. 1-5 - Stefano Sapienza
On-Line Event-Driven Hand Gesture Recognition Based on Surface Electromyographic Signals. 1-5 - Miguel Soto, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
An Intrinsic Method for Fast Parameter Update on the SpiNNaker Platform. 1-5 - Federico Bizzarri, Angelo Brambilla
On the Benefit of Adopting Saturable Inductors in Switching-Mode Power-Supplies: A Case Study. 1-5 - Devon Janke, Gabriel A. Rincón-Mora:
Ripple Suppression of On-Chip Switched-Inductor Power Supplies. 1-5 - Igor N. Aizenberg, Fabio Corti
A multi-step approach to the single fault diagnosis of DC-DC switched power converters. 1-5 - Christian Oeder, Markus Barwig, Julian Dobusch, Thomas Duerbaum:
Accurate Prediction of Resonant Converters' ZVS Behavior in the Time Domain. 1-4 - Abdelali El Aroudi:
Prediction of Subharmonic Oscillation in a PV-fed Quadratic Boost Converter with Nonlinear Inductors. 1-5 - Pablo López Díez, Iosu Gabilondo
A Comprehensive Method to Taxonomize Mechanical Energy Harvesting Technologies. 1-5 - Gustavo C. Martins, Wouter A. Serdijn:
An RF Energy Harvester with MPPT Operating Across a Wide Range of Available Input Power. 1-5 - Xiaodong Meng, Xing Li, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki
An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector. 1-5 - Arish Shareef, Wang Ling Goh, Srikanth Narasimalu
A Rectifier-less Energy Harvesting Interface Circuit for Low-Voltage Piezoelectric Transducers. 1-5 - Nyong-Bassey Bassey Etim, Damian Giaouris, Athanasios I. Papadopoulos
Adaptive Power Pinch Analysis for Energy management of Hybrid Energy Storage Systems. 1-5 - Duy Thanh Nguyen, Hyun Kim, Hyuk-Jae Lee, Ik Joon Chang:
An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications. 1-5 - Hao Zhang
Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors. 1-5 - Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu
Bit-width Adaptive Accelerator Design for Convolution Neural Network. 1-5 - Roberto Giorgio Rizzo, Valerio Tenace
Multiplication by Inference using Classification Trees: A Case-Study Analysis. 1-5 - Xuan-Thuan Nguyen, Trong-Thuc Hoang
A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS. 1-4 - Matthias Wagner
Threshold-Free Interference Cancellation Method for Automotive FMCW Radar Systems. 1-4 - Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri:
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. 1-5 - Kris Rohrmann, Marvin Sandner, Phil Meier, Marcus Prochaska
A novel readout technique for magnetoresistive sensors in automotive anti-lock braking systems. 1-5 - Chunhong Chen, Jinchen Cai, Suoyue Zhan:
A Triple-Point Model for Circuit-Level Reliability Analysis. 1-4 - Chih-Wei Jen, Hung-Wei Yang, Hsun-Wei Chan, Hung-Chih Liu, Henry Lopez Davila
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band. 1-4 - Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes
An LSSD Compliant Scan Cell for Flip-Flops. 1-5 - Pavan Kumar Javvaji, Spyros Tragoudas, Ganesh Kondapuram:
Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection. 1-5 - Yi Jin, Yuxiang Huan, Haoming Chu, Zhuo Zou, Lirong Zheng:
TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design. 1-5 - Yunyun Ji, Wei-Ping Zhu
Improved Lorentzian Greedy Iterative Algorithm Based on Bi-directional Support Estimation for Compressed Sensing. 1-5 - Siyuan Peng, Wee Ser, Zhiping Lin, Badong Chen
Robust sparse nonnegative matrix factorization based on maximum correntropy criterion. 1-5 - Heiner Lange, Sebastian Schmale, Dagmar Peters-Drolshagen, Steffen Paul:
Comparison of Implementation and Recovery for Multi Channel Compressed Sensing. 1-5 - Jeevan K. Pant, Sridhar Krishnan:
Sparse Signal Reconstruction Using Multi-Sequential Lp Optimization. 1-5 - Yu Wu, Dai Jiang, Jifang Duan, Xiao Liu, Richard H. Bayford, Andreas Demosthenous
Towards a High Accuracy Wearable Hand Gesture Recognition System Using EIT. 1-4 - Lijuan Xia, Ahmed Soltan
A Flash-FPGA based Rodent Control System for Closed-loop Optogenetic Control of Epilepsy. 1-5 - Fanpeng Kong, Muhammad Zada
Triple-Band Transmitter with a Shared Dual-Band Antenna and Adaptive Matching for an Intraoral Tongue Drive System. 1-5 - Robert Wilkes, Gang Wang, Carol Huang, Orly Yadid-Pecht, Martin P. Mintchev
Minimally Invasive Pseudo-continuous Blood Glucose Monitoring: Results from In-Vitro and In-Vivo Testing of the eTac. 1-4 - José Luis Merino, Onur Kazanc, Nicolas Brunner, Vincent Schlageter, Michel Demierre, Catherine Dehollain:
Pediatric Size Swallowable Glass Pill for Digestive Motility Analysis. 1-5 - Xinmiao Zhang, Alexander Bazarsky:
Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures. 1-5 - Fakhreddine Ghaffari, Bane Vasic:
Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels. 1-5 - Marco Ferrari
Ultra-Fast Error Correction and Detection for Low-Latency Storage Applications with Emerging Memories. 1-5 - Jing Tian, Jun Lin, Zhongfeng Wang:
An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. 1-5 - Milos Stanisavljevic, Thomas Mittelholzer, Nikolaos Papandreou, Thomas P. Parnell, Haralampos Pozidis:
Drift-Invariant Detection for Multilevel Phase-Change Memory. 1-5 - Zexue Liu, Heyi Li, Haoyun Jiang, Xiucheng Hao
A Low Power SAW-less 2.4-GHz Receiver with an LC Matched Series N-path Filter. 1-5 - Aram Baharmast
A Low Noise, Wide Dynamic Range TOF Laser Radar Receiver Based on Pulse Shaping Techniques. 1-5 - Abhishek Kumar
A Same-Channel Full-Duplex Receiver Using Direct RF Sampling. 1-4 - Sarthak Kalani
Using VCO-OTA TIAs to Break the Gain, Linearity and Power Consumption Trade-offs in Passive Mixer based Direct-Conversion Receivers. 1-5 - Peter Prevedello, André Luiz Aita:
Virtual Collaborative Environment for Support of Teamwork-based Education of Analog IC Design. 1-4 - Ming Zhang, Arnaud Bournel
Educational project on the design of interface circuit for a Pirani pressure sensor. 1-5 - Jennifer Hasler:
Circuit Implementations Teaching a Junior Level Circuits Course Utilizing the SoC FPAA. 1-5 - David C. Burnett
Tapeout class: Taking students from schematic to silicon in one semester. 1-5 - Sifeng Xia, Wenhan Yang, Jiaying Liu
Dual Recovery Network with Online Compensation for Image Super-Resolution. 1-5 - Li Guo, Dajiang Zhou, Jinjia Zhou
Embedded Frame Compression for Energy-Efficient Computer Vision Systems. 1-5 - David Northcote, Louise H. Crockett, Paul Murray:
FPGA Implementation of a Memory-Efficient Hough Parameter Space for the Detection of Lines. 1-5 - Jiwon Lee, Kyoung-Rog Lee, Hoi-Jun Yoo:
A 0.78 mW Low-Power 4.02 High-Compression Ratio Less than 10-6 BER Error-Tolerant Lossless Image Compression Hardware for Wireless Capsule Endoscopy System. 1-4 - Roman Palenychka, Ahmed Lakhssassi, M. Palenychka:
Verification of Medication Dispensing Using the Attentive Computer Vision Approach. 1-4 - Alexander Neckar, Terrence C. Stewart, Ben Varkey Benjamin, Kwabena Boahen:
Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation. 1-5 - Qing Yang, Hai Li, Qing Wu:
A Quantized Training Method to Enhance Accuracy of ReRAM-based Neuromorphic Systems. 1-5 - Chika Tanaka, Keiji Ikeda
Charge-based Neuromorphic Cell by InGaZnO Transistor and Implementation of Simple Scheme Spike-Timing-Dependent Plasticity. 1-5 - Wayne Arter, Ana Osojnik, Coralia Cartis, Godwin Madho, Chris A. Jones
Data assimilation approach to analysing systems of ordinary differential equations. 1-5 - Gabriele Manduchi, Adriano Luchetta, C. Taliercio, Andrea Rigoni:
Big data requirements in current and next fusion research experiments. 1-5 - Teddy Craciunescu
A New Approach to Bolometric Tomography in Tokamaks. 1-4 - Arturo Buscarino, Claudia Corradino
Modeling and control of System of Systems: The Tokamak scenario. 1-5 - Giuseppe Mazzitelli:
The Italian proposal for a new Divertor Test Tokamak (DTT). 1-3 - Xukun Liu, Xinjie Yu:
A New Pulse-Compression Circuit With Residual Energy Recovered. 1-4 - Hung-Yu Chen, Le-Ren Chang-Chien:
Charge Balance Control for Improving the Load Transient Response on Dynamic Voltage Scaling(DVS) Buck Converter. 1-5 - Hur Jedi
A Current-Source Sinusoidal Gate Driver for High-Frequency Applications. 1-5 - Adel Alganidi, Gerry Moschopoulos:
A Comparative Study of Two Passive Regenerative Snubbers for Flyback Converters. 1-4 - Fumiya Ebihara, Xiuqin Wei, Hiroo Sekiya
A Novel Analysis Procedure for Class E Oscillator. 1-5 - Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. 1-5 - Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui, Ken Takeuchi:
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD. 1-5 - Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines. 1-5 - Woong Choi, Kyeongho Lee, Jongsun Park
Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. 1-4 - Soumya Basu, Loris Duch, Miguel Peón Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi:
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. 1-5 - Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi:
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. 1-5 - Michaël Pelissier, Gilles Masson, Laurent Ouvry, Luis Felipe Fonseca Dias, Marguerite Marnat:
Hardware platform of Analog-to-Information converter using Non Uniform Wavelet Bandpass Sampling for RF signal activity detection. 1-5 - Johan Laurent, Pascal Benoit, Loic Dalmasso, Thierry Gil:
Computing in the Fog with Reconfigurable Gateways. 1-4 - Jens Döge
Low-Latency Image Acquisition and Processing with a Programmable Vision-System-on-Chip. 1-5 - Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
A Sub-1V, 220 μW Receiver Frontend for Wearable Wireless Sensor Network Applications. 1-5 - Ka-Meng Lei, Pui-In Mak
A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °C for Wearable and Sensing Applications. 1-5 - Kaung Oo Htet, Hua Fan, Hadi Heidari
Switched Capacitor DC-DC Converter for Miniaturised Wearable Systems. 1-5 - Nishanth Kulasekeram, Krzysztof Wildner, Khalid B. Mirza
Reconfigurable Low-noise Multichannel Amplifier for Neurochemical Recording. 1-5 - Ziyu Wang, Shahriar Mirabbasi:
CMOS Rectifier with on-chip Transformer-Coupled Tunable Matching Network for Biomedical Implants. 1-5 - Surachoke Thanapitak, Chutham Sawigun
A 1.5 V 5.2 nW 60 dB-DR Lowpass Filter With Self-Compansated Gain in 0.35 μm CMOS Suitable for Biomedical Applications. 1-4 - Jorge Pérez-Bailón
A 0.18μm CMOS Widely Tunable Low Pass Filter with sub-Hz Cutoff Frequencies. 1-4 - Gaurav Jha, Mahmoud A. A. Ibrahim
A Low-Power Complex Bandpass Gm-C Filter with Dynamic Range Expansion through Adaptive Biasing. 1-5 - Jiawen Hu, Chen Liu:
An Anti-Aliasing Filter with a Programmable Bandwidth of 10-500MHz for Supply Modulator. 1-5 - Nikita Mirchandani, Aatmesh Shrivastava:
High Stability Gain Structure and Filter Realization with less than 50 ppm/° C Temperature Variation with Ultra-low Power Consumption using Switched-capacitor and Sub-threshold Biasing. 1-5 - Tuomas Haapala, Kari Halonen:
A Fully Integrated Digitally Programmable Pulse Shaping 6.0-8.5 GHz UWB IR Transmitter Front-End for Energy Harvesting Applications. 1-5 - Mika Pulkkinen, Jarno Salomaa, Kari Halonen:
Low-Power Single-Stage Narrowband Transmitter Front-End for 433-MHz Band. 1-4 - Haixiang Zhao, Soumyajit Mandal, Viduneth Ariyarathna, Arjuna Madanayake
An Offset-Canceling Approximate-DFT Beamforming Architecture for Wireless Transceivers. 1-5 - Venkata Narasimha Manyam
A Wideband Mixed-Signal Predistorter for Small-Cell Base Station Power Amplifiers. 1-5 - Muh-Dey Wei, Renato Negra:
High-isolation Stacked RF Switch using dc-lift and Feedforward Cancellation Techniques in Standard 65 nm CMOS. 1-4 - Haoyun Jiang, Zexue Liu, Xiucheng Hao
A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator. 1-5 - Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang:
A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. 1-5 - Yongzhen Chen, Zhekan Ni, Yuefeng Cao
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. 1-4 - Shen-Fu Hsiao, Kun-Chih Chen
Optimization of Lookup Table Size in Table-Bound Design of Function Computation. 1-4 - Erwan Libessart, Matthieu Arzel
40 Gop/s/mm2 fixed-point operators for Brain Computer Interface in 65 nm CMOS. 1-4 - Mohd. Tasleem Khan, Rafi Ahamed Shaik:
Analysis and Implementation of Block Least Mean Square Adaptive Filter using Offset Binary Coding. 1-5 - Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing. 1-5 - Marouf Khan, Masud H. Chowdhury:
Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate. 1-5 - Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu
An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. 1-5 - Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu:
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. 1-4 - Yufeng Li, Yan Li, Deqiang Cheng, Jie Chen:
Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic. 1-4 - Christopher J. Lukas
An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches. 1-4 - Jian Zhang, Shuming Chen, Zhi Wang, Lei Wang, Linghui Lv, Yaohua Wang:
Pre-Calculating Ising Memory: Low Cost Method to Enhance Traditional Memory with Ising Ability. 1-5 - Jian Gao, Wuhuang Huang, Wentao Wei, Lianping Guo, Hao Li, Peng Ye:
Trade-off between Sampling Rate and Resolution: A Time-synchronized Based Multi-resolution Structure for Ultra-fast Acquisition. 1-5 - Md Farhadur Reza
Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era. 1-5 - Dinh Van Luan, Xuan Truong Nguyen, Hyuk-Jae Lee:
A New FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation of Operating Condition Variation. 1-4 - Ke Chen, Jie Han, Paolo Montuschi, Weiqiang Liu, Fabrizio Lombardi:
Design and Application of an Approximate 2-D Convolver with Error Compensation. 1-5 - Nahid M. Hossain, Ritesh Kumar Reddy Kuchukulla, Masud H. Chowdhury:
Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC). 1-4 - Libo Qian, Xitao He, Kefang Qian, Yinshui Xia:
Study of silicon core coaxial through silicon via for three dimensional integration. 1-4 - Sachin Kumar, Jawad Haj-Yahya, Anupam Chattopadhyay:
Efficient Hardware Accelerator for NORX Authenticated Encryption. 1-5 - Ghasem Pasandi, Alireza Shafaei, Massoud Pedram:
SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits. 1-5 - Donatus Silva Richard, Rashid Rashidzadeh, Majid Ahmadi:
Secure Scan Architecture Using Clock and Data Recovery Technique. 1-5 - Jingon Lee, Jinwook Jung, Youngsoo Shin:
Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits. 1-4 - Justine Bonnot, Karol Desnos, Daniel Ménard:
Stochastic Modeling to Accelerate Approximate Operators Simulation. 1-5 - Seongkwan Lee, Taehwan Kim:
Low-cost Technique for Measuring Clock Duty Cycle on FPGAs. 1-5 - Nihar Hage, Satyadev Ahlawat
In-situ Monitoring for Slack Time Violation Without Performance Penalty. 1-5 - Jody Maick Matos, André Inácio Reis, Jordi Carrabina:
Technology Mapping for Circuits with Simple Cells. 1-5 - Scott Lerner, Vasil Pano, Baris Taskin:
NoC Router Lifetime Improvement using Per-Port Router Utilization. 1-5 - Sheng-Hui Wang, Huai-Ting Li, An-Yeu Andy Wu:
Error-Resilient Reconfigurable Boosting Extreme Learning Machine for ECG Telemonitoring Systems. 1-5 - Minyoung Jeong, Jaeheum Lee, Eungu Jung, Young Hwan Kim, Kyoung-Rok Cho:
Extract LUT Logics from a Downloaded Bitstream Data in FPGA. 1-5 - Mikko Martelius, Kari Stadius, Jerry Lemberg, Enrico Roverato, Marko Kosunen
Spectral Effects of Discrete-Time Amplitude Levels in Digital-Intensive Wideband Radio Transmitters. 1-5 - Jerry Lemberg, Marko Kosunen
Design and Implementation of a Wideband Digital Interpolating Phase Modulator RF Front-End. 1-5 - Sheng-Kai Chang, Kuan-Wei Chen, Shang-De Yang, Chin-Lung Yang, Kuang-Wei Cheng:
An Autonomous Wireless Transmitter with Piezoelectric Energy Harvester from Short-Duration Vibrations. 1-4 - Mohamed Shehata, Mohamed Sameh Said, Hassan Mostafa
Photodetected Power Maximization of Photonically Generated Impulse Radio Ultrawide Band Signals. 1-4 - Xiucheng Hao
A 43.2 μW 2.4 GHz 64-QAM Pseudo-Backscatter Modulator Based on Integrated Directional Coupler. 1-5 - Younes Aimer, Boubakar Seddik Bouazza
PAPR Reduction Performance in WIMAX OFDM Systems using Interleavers with Downward-Compatibility. 1-5 - Pascal Seidel, Benjamin Knoop, Sebastian Schmale, Daniel Gregorek, Steffen Paul, Jochen Rust
Random Subsampling based Signal Detection for Spatial Correlated Massive MIMO Channels. 1-5 - Wen-Ching Hu, Nai-Hsuan Huang, Tzi-Dar Chiueh:
Software Defined Radio Implementation of an LTE Downlink Transceiver for Ultra Dense Networks. 1-5 - Filipe Vinci dos Santos, Emanuel Dogaru:
Flexible Wideband Radio Transceiver Testing using Non-Uniform Subsampling Demodulation. 1-5 - Hanchun Tang, Li Ding, Jing Jin, Jianjun Zhou:
A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI. 1-4 - Jacob Pike, Mahdi Parvizi, Naim Ben-Hamida, Sadok Aouini, Calvin Plett:
New Charge-Steering Latches in 28nm CMOS for Use in High-Speed Wireline Transceivers. 1-5 - Andres Amaya, Elkim Roa
On-Fly Offset-Correction Method for High-Speed Comparators using All-Digital Phase Measurement. 1-4 - Ailing Piao, Aili Wang, Chuanjin Richard Shi:
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. 1-4 - Sheng-Sian Wang, Ying-Ren Chien
Compensation of SNR Degradation Caused by Nonlinearity of the Phase Interpolator in a Frequency-Domain Echo Canceller. 1-5 - H. Zhang, Enrico Monaco, Matteo Bassi, Andrea Mazzanti:
Flexible Transversal Continuous-Time Linear Equalizer Operating up to 25Gb/s in 28nm CMOS. 1-4 - Samuel Presa Toledo, Alexandra L. Zimpeck, Ricardo Reis
Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders. 1-5 - Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. 1-5 - Valentino Peluso
Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. 1-5 - Gyuseong Kang, Yunho Jang, Jongsun Park
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM. 1-4 - David A. Basford, Mohsen Judy, Peixing Liu, Jeremy Holleman:
A Sub-1V-Read Flash Memory in a Standard 130nm CMOS Process. 1-4 - Cheol Kim, Rak-Joo Sung, Sung-Gi Ahn, Jisu Min, Kee-Won Kwon:
Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line. 1-4 - Adewale Adetomi, Godwin Enemali
Characterization of Clock Buffers for On-Chip Inter-Circuit Communication in Xilinx FPGAs. 1-5 - Faiq Khalid, Sunil Nanjiani, Syed Rafay Hasan, Osman Hasan
Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices. 1-5 - Chikun Yuan, Letian Huang, Junshi Wang, Qiang Li:
Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip. 1-5 - Sen-Chih Tsai, Yu-Xiang Su, Yu-Han Chin, Wei-Zhong Ceng, Chung-Ho Chen:
Kernel Aware Warp Scheduler. 1-5 - Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu:
An Automatic Task Partition Method for Multi-core System. 1-5 - Mohamed Shehata, Mohamed Sameh Said, Hassan Mostafa
A Single-Wavelength Photonic Network on Chip Design Based on Optical Orthogonal Codes. 1-4 - Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado:
Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs. 1-5 - Chun-Jen Tsai, Yan-Hung Lin:
A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC. 1-4 - Bahar Youssefi, Alexander J. Leigh
Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays. 1-5 - Ming Ming Wong, Jawad Haj-Yahya, Suman Sau, Anupam Chattopadhyay:
A New High Throughput and Area Efficient SHA-3 Implementation. 1-5 - Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. 1-4 - Felipe T. Bortolon, Geancarlo Abich
Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems. 1-5 - Andreas Herkle, Joachim Becker, Maurits Ortmanns:
An Arbiter PUF employing eye-opening oscillation for improved noise suppression. 1-5 - Gaurav Sharma
Automated Coverage Register Access Technology on UVM Framework for Advanced Verification. 1-4 - Ragh Kuttappa, Baris Taskin:
Low Frequency Rotary Traveling Wave Oscillators. 1-5 - Mahmood J. Azhar, Selçuk Köse
Process, Voltage, and Temperature-stable Adaptive Duty Cycle based PUF. 1-5 - Mallika Rathore, Emre Salman:
Error Probability Models to Facilitate Approximate Computing in TFET based Circuits. 1-5 - Guido Di Patrizio Stanchieri
An FPGA-Based Architecture of True Random Number Generator for Network Security Applications. 1-4 - Md Shazzad Hossain
Noise Constrained Optimum Selection of Supply Voltage for IoT Applications. 1-5 - Li Ding, Wenbo Yin, Lingli Wang:
Ultra-Low Latency and High Throughput Key-Value Store Systems Over Ethernet. 1-5 - Yutaro Ishida, Takashi Morie, Hakaru Tamukoh:
A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots. 1-5 - Heng Liu, Li Ding, Jing Jin, Jianjun Zhou:
A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. 1-5 - Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang:
A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A. 1-4 - ChenYang Xia
On Path Memory in List Successive Cancellation Decoder of Polar Codes. 1-5 - Manuel Potéreau, Yoan Veyrac, Guillaume Ferré:
Leveraging LoRa Spreading Factor Detection to Enhance Transmission Efficiency. 1-5 - Imad Benacer
Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. 1-5 - Fanfan Meng, Ke Li, Dave J. Thomson, Cosimo Lacava
Ultra Wide-Band Inductive Peaking VCO with Cascode Noise Reduction. 1-5 - Di He, Xin Chen, Danping Zou, Ling Pei
Uplink Power Control Approach Based on Adaptive Chaotic Simulated Annealing. 1-5 - Chia-Yu Yao, Wei-Chun Hsia
Controlling a switched beam array antenna using PLL frequency synthesizers based on the congruence modulo. 1-4 - Eunho Choi, SeongMoon Kim
Improved SNR, On-Chip Differentially Modulated TISM Signaling in HV DMOS Process for Mutual Capacitance Fingerprint Sensor. 1-4 - Antoine Courtay, Mickaël Le Gentil, Olivier Berder, Arnaud Carer, Pascal Scalart, Olivier Sentieys:
Zyggie: A Wireless Body Area Network platform for indoor positioning and motion tracking. 1-5 - Bachir Fradj, Benjamin Wolff, Normand Bélanger, Yvon Savaria:
Implementation of a Cache-Based IPv6 Lookup System with Hashing. 1-4 - Omer Tanovic, Rui Ma
Compact Analytical Description of Digital Radio-Frequency Pulse-Width Modulated Signals. 1-5 - Pengfei Ji, Jing Gao, Wenyi Xu, Yanan Sun, Weifeng He, Hui Wu:
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array. 1-5 - Chunyang Liu, Jian Ni, Weiqiang Liu, Zhe Liu, Máire O'Neill:
Design and Optimization of Modular Multiplication for SIDH. 1-5 - Adrián Pérez-Resa
Using a Chaotic Cipher to Encrypt Ethernet Traffic. 1-5 - Miguel Garcia-Bosque
A New Technique For Improving the Security of Chaos Based Cryptosystems. 1-5 - Jheng-Hao Ye, Si-Quan Chen, Ming-Der Shieh:
Minimizing ESOP Expressions for Fully Homomorphic Encryption. 1-4 - Vasileios G. Ntinas
Coupled Physarum-Inspired Memristor Oscillators for Neuron-like Operations. 1-5 - Guanghui Wen, Wei Xing Zheng:
Consensus Tracking of Multi-Agent Systems With Directed Switching Topology: A Multiple Lyapunov Functions Method. 1-4 - Jyoti Prakash Mishra, Mahdi Jalili
Robust Pinning Synchronization of Complex Network with Non-linear Coupling using Switching Control. 1-5 - Ali Moradi Amani
A New Metric to Find the Most Vulnerable Node in Complex Networks. 1-5 - Peng Liu
Analysis of Incremental Exponential Stability for Switched Nonlinear Systems. 1-4 - Miroslav Mirchev, Igor Mishkovski, Ljupco Kocarev:
Epidemic spreading in multiplex networks with Markov and memory based inter-layer dynamics. 1-5 - Jun-Hyuk Choi, Joon Sung Park, Byong Jo Hyon, Jin-Hong Kim, Bon-Gwan Gu:
Experimental Performance Evaluation of Bi-directional Converter for High Power Application. 1-4 - Francesco Musolino, Paolo Stefano Crovetti:
Interference of Spread-Spectrum Switching-Mode Power Converters and Low-Frequency Digital Lines. 1-5 - Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. 1-4 - Chayapas Sritongon, Paweewatch Wisestherrakul, Nattawut Hansupho, Supapong Nutwong
Novel IPT Multi-Transmitter Coils with Increase Misalignment Tolerance and System Efficiency. 1-5 - Yiwei Tan, Chi-Seng Lam
Design and Control of An Integrated 3-Level Boost Converter under DCM Operation. 1-5 - Satya K. Vendra
Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile. 1-5 - Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son:
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling. 1-5 - Nico Angeli, Klaus Hofmann:
A Scalable Fully Synthesized Phase-to-Digital Converter for Phase and Duty-Cycle Measurement of High-Speed Clocks. 1-5 - Orazio Aiello
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V. 1-5 - Takumi Fujimori, Minoru Watanabe:
High total-ionizing-dose tolerance field programmable gate array. 1-4 - Bing Li, Fan Chen, Wang Kang, Weisheng Zhao, Yiran Chen, Hai Li:
Design and Data Management for Magnetic Racetrack Memory. 1-4 - Stephen K. Heinrich-Barna, Jean-Pierre Leburton, Joseph S. Friedman:
All-Carbon Spin Logic Sensor for RRAM Arrays. 1-5 - Zhaohao Wang, Zuwei Li, Yang Liu, Simin Li, Liang Chang
Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited). 1-5 - Damir Vodenicarevic, Nicolas Locatelli, Alice Mizrahi, Tifenn Hirtzlin, Joseph S. Friedman, Julie Grollier, Damien Querlioz:
Circuit-Level Evaluation of the Generation of Truly Random Bits with Superparamagnetic Tunnel Junctions. 1-4 - Naohiko Shimizu, Junichi Akita, Marie-Minerve Louërat, Haralampos-G. D. Stratigopoulos, Jean-Paul Chaput, Dimitri Galayko:
Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping. 1-5 - Gildas Léger
Mixed-signal test automation: Are we there yet? 1-5 - Mona Safar, Keroles K. Khalil, Magdy A. El-Moursy, Mohamed Abdelsalam:
Virtual Electronic Control Unit as a Functional Mockup Unit for Heterogeneous Systems. 1-5 - Joan Asselot, Arnaud Krust, Arnaud Parent, Chris Welham:
High order MEMS models for system design. 1-5 - François Pêcheux, Christoph Grimm, Torsten Maehne, Martin Barnasconi, Karsten Einwich:
SystemC AMS Based Frameworks for Virtual Prototyping of Heterogeneous Systems. 1-4 - Kai-Ren Cheng, Hsin-Shu Chen, Mickaël Lallart
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting. 1-4 - Lidan Wang, Chenchang Zhan, Linjun He
A Low-Power High-PSRR CMOS Voltage Reference with Active-Feedback Frequency Compensation for IoT Applications. 1-4 - Jianping Guo, Weimin Li, Yicheng Li, Siji Huang, Zhao Wang, Bing Mo, Dihu Chen:
A 70-nA 13-ppm/°C All-MOSFET Voltage Reference for Low-Power IoT Systems. 1-4 - Fangyu Mao, Yan Lu, Jie Lin, Chenchang Zhan, Seng-Pan U, Rui Paulo Martins:
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT. 1-4 - Ya Wen, Andreas Demosthenous
A Capacitance-to-Digits Readout Circuit for Integrated Humidity Sensors for Monitoring the In-Package Humidity of Ultra-Small Medical Implants. 1-4 - Soon-Jae Kweon, Sung-Hun Jo, Ji-Hoon Suh, Minkyu Je, Hyung-Joun Yoo:
A Sinusoidal Signal Generator Using a Constant Gain Finite Impulse Response (FIR) Filter for Electrical Bioimpedance Spectroscopy. 1-5 - Matthieu Sylvain, Francis Lehoux, Steeve Morency, Felix Faucher, Eric Bharucha
The EcoChip: A Wireless Multi-Sensor Platform for Comprehensive Environmental Monitoring. 1-5 - Mahdi Rajabzadeh, Denis Djekic, Matthias Haeberle, Joachim Becker, Jens Anders
Comparison Study of Integrated Potentiostats: Resistive-TIA, Capacitive-TIA, CT ΣΔ Modulator. 1-5 - Rahul Kumar Yadav, Jan Wessel, Mohamed Hussein Eissa, Farabi Ibne Jamal, Maciej Kucharski, Dietmar Kissinger:
A 30 GHz Power Detector based Reflectometer in 130nm SiGe BiCMOS for Dielectric Spectroscopy. 1-4 - W. Kenneth Jenkins, Michael A. Soderstrand, Chandrasekhar Radhakrishnan:
Historical Patterns of Emerging Residue Number System Technologies During the Evolution of Computer Engineering and Digital Signal Processing. 1-5 - Eric B. Olsen:
RNS Hardware Matrix Multiplier for High Precision Neural Network Acceleration: "RNS TPU". 1-5 - Amir Sabbagh Molahosseini
Towards Efficient Modular Adders based on Reversible Circuits. 1-5 - Hiroki Nakahara
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. 1-5 - Mehdi Noormohammadi Khiarak, Kiyotaka Sasagawa
An Energy-Efficient CMOS Biophotometry Sensor With Incremental DT-∑Δ ADC Conversion. 1-4 - Ramy Tantawy
A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS. 1-4 - Yuefeng Cao
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. 1-5 - Nikola Ivanisevic, Saul Rodriguez
Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation. 1-4 - Shirin Pourashraf
Continuous and Discrete Time Low Voltage Analog Circuits in 16 nm CMOS Technology. 1-5 - Shunsuke Koshita, Masahide Abe, Masayuki Kawamata:
Minimum Roundoff Noise Realization for Variable IIR Digital Filters Based on M-D Polynomial Approximation. 1-5 - Wu-Sheng Lu, Takao Hinamoto:
Enhanced Steiglitz-McBride Procedure for Minimax IIR Digital Filters. 1-5 - Gyan Deep, Sumit Jagdish Darak
Spectral Parameter Approximation Based Tunable Digital Filters on Zynq SoC. 1-5 - Namalka Liyanage, Chamith Wijenayake
Low-Complexity 4-D IIR Filters for Multi-Depth Filtering and Occlusion Suppression in Light Fields. 1-5 - Lech Kolonko
Word Length Optimization of 2-D Wave Digital Filters with Weighted Quantization Error Variances. 1-5 - Darya Mikhailenko, Chamika M. Liyanagedera, Alex Pappachen James
M2CA: Modular Memristive Crossbar Arrays. 1-5 - Albert Ciprut, Eby G. Friedman:
Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays. 1-5 - Matteo Lodi, Andrey Shilnikov
Design of Minimal Synthetic Circuits with Sensory Feedback for Quadruped Locomotion. 1-5 - Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi:
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. 1-5 - Maria-Teresa Atienza, Lukasz Kowalski
Model identification of Time-Varying Diffusive Systems. 1-5 - Graziano Chesi:
Determinant-Based Hurwitz Test For Complex Matrices Over The Complex Unit Circumference And Applications in 2D Systems. 1-4 - Tat Kei Chau
An Adaptive Optimization Method for LFOD Enhancement in DFIG Integrated Smart Grids. 1-5 - Wuyang Su, Bin Liu
Dynamic State Estimation for DFIG Wind Turbine with Stochastic Wind Speed in Power System. 1-5 - Suli Zou, Zhongjing Ma, Guorong Zhu, Xiangdong Liu:
Demand Side Management in Direct Current Distribution Networks: Convergence and Optimality. 1-5 - Zongbin Ye, Xianming Deng, Anni Chen, Zhiguo Zhang, Linlin Jiang, Dongsheng Yu:
Design of a novel three-level voltage source converter for AC-DC-AC conversion. 1-5 - Guangyi Liu, Xi Chen
Evolving Graph Based Power System EMS Real Time Analysis Framework. 1-5 - Yixiong Yang, Zhibo Wang, Pei Yang, Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu:
A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation. 1-5 - Richard Afoakwa, Lejie Lu, Yong Wang
High Swing Pulse-Amplitude Modulation of Transmission Line Links for On-Chip Communication. 1-5 - Xin Li, Xingtao Ou, Henglu Wei, Wei Zhou:
Synergistic Calibration of Noisy Thermal Sensors Using Smoothing Filter-Based Kalman Predictor. 1-5 - Kasem Khalil
A Cost-Effective Self-Healing Approach for Reliable Hardware Systems. 1-5 - Alberto Annovi, Giovanni Calderini, Stefano Capra
Characterization of an Associative Memory Chip in 28 nm CMOS Technology. 1-5 - Alberto Annovi, Luca Frontini
Design and Characterization of New Content Addressable Memory Cells. 1-5 - Spyros Stathopoulos, Ali Khiat, Alexantrou Serb
Benchmarking Analogue Performance of Emerging Random Access Memory Technologies. 1-4 - Christian Weis, Matthias Jung, Éder F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn
The Role of Memories in Transprecision Computing. 1-5 - Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu, Lih-Yih Chiou:
Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme. 1-4 - Zhenxin Zhao, Tuotian Liao, Lihong Zhang:
Fast Performance Evaluation for Analog Circuit Synthesis Frameworks. 1-5 - Mohammad Torabi, Lihong Zhang:
Electromigration and Parasitic-Aware ILP Router for Analog and RF Circuits. 1-5 - Igor M. Filanovsky, Luís B. Oliveira
Using Modified Bessel Functions For Calculations of Drain Current Harmonics In a MOS Transistor Operating in Moderate Inversion. 1-4 - Yifei Li, Nathan M. Neihart:
Time-Domain Analysis of Optimum Bias Point in Inverse Class-F Power Amplifiers. 1-4 - Ji Hoon Hyun, Long Huang, Dong Sam Ha:
Vibration and Thermal Energy Harvesting System for Automobiles with Impedance Matching and Wake-up. 1-5 - Keisuke Kimura, Keita Taeda, Shohei Niikawa, Hirotaka Koizumi:
A Wireless Sensor Node Driving System with Bridgeless Bipolar Boost Rectifier Using Thermoelectric Energy Harvesting. 1-5 - Adrien Morel, Pierre Gasnier, Yohan Wanderoild, Gaël Pillonnet, Adrien Badel:
Short Circuit Synchronous Electric Charge Extraction (SC-SECE) Strategy for Wideband Vibration Energy Harvesting. 1-5 - Bao Zhao, Junrui Liang, Kang Zhao:
Phase-Variable Control of Parallel Synchronized Triple Bias-Flips Interface Circuit towards Broadband Piezoelectric Energy Harvesting. 1-5 - Mohamed Fayez El-Sharkawy, John Daniels
A Portable Low-Power Platform for Ambulatory Closed Loop Control of Blood Glucose in Type 1 Diabetes. 1-5 - Shih-Kai Lin, Isti Qomah, Yu-Shan Lin, Herming Chiueh, Chin-Yew Lin:
Design and Implementation of a Smart Headband for Epileptic Seizure Detection and Its Verification Using Clinical Database. 1-5 - Dionisije Sopic, Amir Aminifar, David Atienza:
e-Glass: A Wearable System for Real-Time Detection of Epileptic Seizures. 1-5 - Edoardo Bonizzoni, Alessandro Puiatti
UWB Tracking for Home Care Systems with Off-the-Shelf Components. 1-5 - Francesca Stradolini, Nadia Tamburrano, Thiébaud Modoux, Abuduwaili Tuoheti
IoT for Telemedicine Practices enabled by an Android™ Application with Cloud System Integration. 1-5 - Eduardo C. Culau, Grégory C. Marchesan, Nelson R. Weirich
An Efficient Single Core Flexible Processor Architecture for 4096-bit Montgomery Modular Multiplication and Exponentiation. 1-5 - Darjn Esposito, Gennaro Di Meo
On the Use of Approximate Multipliers in LMS Adaptive Filters. 1-5 - Avishek Sinha Roy, Anindya Sundar Dhar:
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. 1-5 - Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. 1-5 - Takayuki Moto, Mineo Kaneko:
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing. 1-5 - Gianluca Giustolisi
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads. 1-4 - M. Pilar Garde
Folded Cascode OTA with 5540 MHzpF/mA FoM. 1-5 - Meysam Akbari
A High Slew Rate CMOS OTA with Dynamic Current Boosting Paths. 1-5 - Gianluca Giustolisi
Settling-time oriented OTA design through the approximation of the ideal delay. 1-4 - Amr Ahmed
A Ring Amplifier Architecture for Continuous-Time Applications. 1-5 - Praveen Kumar Venkatachala, Spencer Leuenberger, Ahmed ElShater, Calvin Lee, Jason Muhlestein, Bohui Xiao, Michael Oatman, Un-Ku Moon:
Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers. 1-5 - Alessandro Urso, Wouter A. Serdijn:
A Switched Capacitor DC-DC Buck Converter for a Wide Input Voltage Range. 1-5 - Jen-Chien Hsieh, Tsung-Heng Tsai
An AC-DC Wind Energy Harvesting Circuit with Extended Input-Voltage Range and 95% Tracking Efficiency. 1-4 - Antônio Carlos M. de Queiroz:
Steady-State Analysis of Electronic Electrostatic Generators. 1-5 - Soumya Bose, Matthew L. Johnston:
A Stacked-Inverter Ring Oscillator for 50 mV Fully-Integrated Cold-Start of Energy Harvesters. 1-5 - Mark Lipski, Yin Li, Manjusri Misra, Stefano Gregori
A Low Forward Bias Active Diode Circuit for Electrostatic Energy Harvesters. 1-5 - Parvaneh Saffari, Ali Basaligheh, Kambiz Moez:
A Wide-Range Highly Power Efficient RF-to-DC Rectifier for RF Energy Harvesting Systems. 1-4 - Shohei Mita, Hiroo Sekiya
Analysis of class-D ZVS inverter with asymmetrical duty-cycle control for wireless power transfer applications. 1-5 - Alberto Bernardini
Wave Digital-Based Variability Analysis of Electrical Mismatch in Photovoltaic Arrays. 1-5 - Yvan Debizet, Guénolé Lallement, Fady Abouzeid
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States. 1-5 - Hesam Fathi Moghadam, Jieun Jang, Michael Dayringer, Thipok Rak-amnouykit, Guanghua Shu, Anatoly Yakovlev, Yue Zhang, David Hopkins:
Design Considerations of Monolithically Integrated Voltage Regulators for Multicore Processors. 1-5 - Sung-Hao Wang
The Design of CMOS 13.56-MHz High Efficiency 1×/3× 1.99V/6.29V Active Rectifier for Implantable Neuromodulation Systems. 1-4 - Abdulqader Nael Mahmoud
A Charge Pump Based Power Management Unit With 66%-Efficiency in 65 nm CMOS. 1-4 - Dima Kilani
An Efficient and Small Area Multioutput Switched Capacitor Buck Converter for IoTs. 1-4 - Boyu Shen
Zero Reversion Loss, High-Efficiency Charge Pump for Wide Output Current Load Range. 1-5 - Juan C. Castellanos
Dynamic Output Resistance Optimization for Duty-cycle Control in Hybrid Capacitive LED Drivers. 1-5 - Mahmoud A. A. Ibrahim
Study of Performance Impact from Powering RF Receiver Front-End Circuits with a DC-DC Converter. 1-5 - Alberto Bocca, Yukai Chen
Fundamental Feature Extraction of the Battery Charge Phase from Product Data. 1-4 - Sraddhanjoli Bhadra, Hirak Patangia:
A Unified Analytical Solution for Bipolar, Unipolar, and Multistep SHE Converters. 1-5 - Yohan Wanderoild, Adrien Morel
Maximizing Wireless Power Transfer with Single-Turn Coreless Coupled Coils. 1-5 - Yoshikazu Sakai, Hirotaka Koizumi:
Half-Wave Class DE Low dv/dt Rectifier Using Common-Grounded Controlled Shunt Capacitor and Its Design Approach. 1-4 - Rudolf Rabenstein, Maximilian Schäfer
A Wave Digital Kalman Filter Approach for Fault Detection in DC Grids: A Case Study. 1-5 - Hengdao Guo, Herbert Ho-Ching Iu, Tyrone Fernando
Cascading Failure Model Considering Multi-Step Attack Strategy. 1-5 - Blanca Areli Martínez-Treviño, Abdelali El Aroudi, Luis Martínez-Salamero:
Synthesis of constant power loads using switching converters under sliding mode control. 1-5 - Pierluigi Guerriero, Pasquale Cennamo, Santolo Daliento:
A Two Legs Darlington Based Circuit for on Site Tracing of Solar Panels I-V Curve. 1-5 - Francesco Grasso, Antonio Luchetta, Stefano Manetti
Improvement of Power Flow Analysis based on Currents' Physical Component (CPC) Theory. 1-5 - Peter McCallum
The Use of Demand Modelling for Community Energy Analysis. 1-5 - Seyed Hamid Reza Hosseini, Adib Allahham
Techno-Economic-Environmental Analysis of Integrated Operation of Gas and Electricity Networks. 1-5 - Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. 1-5 - Pedro Arthur R. L. Silva, Juliana Rezende S. B. Alves, Ricardo S. Ferreira, Omar P. Vilela Neto
A Novel Five-input Multiple-function QCA Threshold Gate. 1-5 - Valeri M. Mladenov
A Memristor Model with a Modified Window Function and Activation Thresholds. 1-5 - Gleb Krylov, Eby G. Friedman:
Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor. 1-5 - Tingfeng Yang, Jianping Hu, Wenjing Bai:
Analysis and Simulation of Negative Capacitance Independent Multi-Gate FinFETs. 1-5 - Zhicheng Wang, Yu Yu, Xi Xiao
A Time-Division-Multiplexing Scheme for Simultaneous Wavelength Locking of Multiple Silicon Micro-Rings. 1-4 - Geraldo Fontes, Pedro Arthur R. L. Silva, José Augusto Miranda Nacif, Omar P. Vilela Neto
Placement and Routing by Overlapping and Merging QCA Gates. 1-5 - Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. 1-5 - Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. 1-5 - Qian He, Aibin Yan, Chaoping Lai, Yinlei Zhang, Chunming Liu, Zhile Chen, Zhen Wu, Jie Cui, Huaguo Liang:
Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS. 1-5 - Stefano Lai, Giulia Casula, Piero Cosseddu, Annalisa Bonfiglio, Massimo Barbaro
All-Polymer Integrated Circuit for Monitoring the X-Ray Checking History of Luggages. 1-4 - Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi
A Novel Sensing Circuit with Large Sensing Margin for Embedded Spin-Transfer Torque MRAMs. 1-5 - Ahmed Abubakr
High-Temperature Modeling of the I-V Characteristics of GaN150 HEMT Using Machine Learning Techniques. 1-5 - Mostafa Amer
High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT. 1-5 - Tingting Zhang
Design of Majority Logic (ML) Based Approximate Full Adders. 1-5 - Jeferson F. Chaves
Enhancing Fundamental Energy Limits of Field-Coupled Nanocomputing Circuits. 1-5 - Md Musabbir Adnan, Sherif Amer, Garrett S. Rose
A Novel Scan-In Scheme for CMOS/ReRAM Programmable Logic Circuits. 1-5 - Emre Göncü, Abdulkadir Koçdogan, Müstak E. Yalçin
A High Speed True Random Number Generator with Cellular Automata with Random Memory. 1-5 - Robert D'Angelo, Brent Hollosi, Wes Uy, Haiyao Huang, Dorothy C. Poppe, Sameer Sonkusale:
An Analog Visual Saliency Processor using Time-mode Computation. 1-5 - Shvan Karim, Jim Harkin, Liam McDaid, Bryan Gardiner
FPGA-based Fault-injection and Data Acquisition of Self-repairing Spiking Neural Network Hardware. 1-5 - Lu Zhang, Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang:
A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. 1-4 - Yizhi Wang, Jun Lin, Zhongfeng Wang:
An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning. 1-5 - Zhao Heng, Dipu Manandhar, Kim-Hui Yap
Hybrid Supervised Deep Learning for Ethnicity Classification using Face Images. 1-5 - Ali Shayei, Mehryar Abbasi, Ali Habiban, Mahdi Shabany, Zahra Kavehvash:
A Machine Learning Approach for Material Classification in MMW Imaging Systems based on Frequency Spectra. 1-5 - Xiaoping Lai, Jiuwen Cao, Zhiping Lin:
A Novel Relaxed ADMM with Highly Parallel Implementation for Extreme Learning Machine. 1-5 - Dusan M. Stipanovic
Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model. 1-5 - Duncan J. M. Moss, David Boland
Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. 1-5 - Li Guo, Dajiang Zhou, Jinjia Zhou
Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression. 1-5 - Hedyeh A. Kholerdi, Nima Taherinejad, Axel Jantsch
Enhancement of Classification of Small Data Sets Using Self-awareness - An Iris Flower Case-Study. 1-5 - Deepak Mishra
Segmentation of Vascular Regions in Ultrasound Images: A Deep Learning Approach. 1-5 - Muhammet Bastan, Kim-Hui Yap
Idling Car Detection with ConvNets in Infrared Image Sequences. 1-5 - Dipu Manandhar, Kim-Hui Yap
Brand-Aware Fashion Clothing Search using CNN Feature Encoding and Re-ranking. 1-5 - Suhwan Lim, Jong-Ho Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim
Hardware-based Neural Networks using a Gated Schottky Diode as a Synapse Device. 1-5 - Rajeev Ranjan, Mirko Hansen, Pablo Mendoza Ponce
Integration of Double Barrier Memristor Die with Neuron ASIC for Neuromorphic Hardware Learning. 1-5 - Narasinga Rao Miniskar
Optimal SDRAM Buffer Allocator for Efficient Reuse of Layer IO in CNNs Inference Framework. 1-5 - Chandrajit Pal
Modified Huffman based compression methodology for Deep Neural Network Implementation on Resource Constrained Mobile Platforms. 1-5 - Luis A. Camuñas-Mesa, Y. Domínguez-Cordero, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA. 1-5 - Amirreza Yousefzadeh, Mikel Soto, Teresa Serrano-Gotarredona, Francesco Galluppi
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker. 1-4 - Corey Lammie
Unsupervised Character Recognition with a Simplified FPGA Neuromorphic System. 1-5 - Aishwarya Natarajan
Dynamics of Hodgkin Huxley Neuron across chips implemented on a reconfigurable platform. 1-5 - Kevin Corder, John V. Monaco
Solving Vertex Cover via Ising Model on a Neuromorphic Processor. 1-5 - Sheng Zhang, Wei Xing Zheng:
Normalized Least Mean-Square Algorithm with Variable Step Size Based on Diffusion Strategy. 1-4 - B. K. Das, Sudipta Mukhopadhyay, Mrityunjoy Chakraborty:
Robust adaptive filtering via convex combination of l0-RLS adaptive filters. 1-5 - Jian-Qiang Lin, Shing-Chow Chan:
A Robust Variable Forgetting Factor QS-decomposition Algorithm for Subspace Tracking. 1-5 - Danilo Comminiello, Michele Scarpiniti, Simone Scardapane, Aurelio Uncini:
Sparse functional link adaptive filter using an ℓ1-norm regularization. 1-5 - Keisuke Okano, Takaki Itatsu, Naoto Sasaoka, Yoshio Itoh:
Auxiliary Noise Power Scheduling Based on Gradient of Error Power for Pre-inverse Active Noise Control. 1-5 - Kypros M. Kossifos
An Optically-Programmable Absorbing Metasurface. 1-5 - Carlota Ruiz de Galarreta
Phase-Change Metasurfaces for Dyamic Beam Steering and Beam Shaping in the Infrared. 1-5 - Xavier Timoneda, Sergi Abadal
Millimeter-Wave Propagation within a Computer Chip Package. 1-5 - Fu Liu
Programmable Metasurfaces: State of the Art and Prospects. 1-5 - Loukas Petrou
Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces. 1-5 - Federico Bizzarri, Angelo Brambilla
The Urbanek Black Box Arc Model in Passive Resonance Circuit Breakers for HVDC Applications. 1-5 - Jian Sen Teh
Novel Edge Comparator with Input Time Hysteresis for Improved Edges Arbitration. 1-5 - Zbigniew Galias
On the Existence of the Double Scroll Attractor for the Chua's Circuit with a Smooth Nonlinearity. 1-5 - Tommaso Addabbo, Ada Fort, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque
Digital Nonlinear Oscillators in PLDs: Pitfalls and Open Perspectives for a Novel Class of True Random Number Generators. 1-5 - Graziano Chesi, Tiantian Shen:
Computing Parametric LQRs For Polytopic Discrete-Time Systems. 1-4 - Ebrahim Rezaei, Vaithianathan Venkatasubramanian:
Quantitative Indicators for Quality of Fit Assessment in Power System Model Validation Problems. 1-5 - Nicholas S. Coleman, Thomas J. Halpin, Karen Nan Miu:
Online Determination of Time Intervals for Statically Secure Distribution System Control. 1-5 - Sijia Geng, Ian A. Hiskens:
Jump Conditions for Second-Order Trajectory Sensitivities at Events. 1-5 - Alisha Zachariah, Zachary Charles, Nigel Boston, Bernard C. Lesieutre:
Distributions of the Number of Solutions to the Network Power Flow Equations. 1-5 - Marcelo Ruaro
Software-Defined Networking Architecture for NoC-based Many-Cores. 1-5 - Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. 1-4 - Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin:
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. 1-5 - Sri Harsha Gade, Sidhartha Sankar Rout
A Utilization Aware Robust Channel Access Mechanism for Wireless NoCs. 1-5 - Rongdi Sun, Peilin Liu, Cecil Accetti, Abid A. Naqvi, Haroon Ahmed, Jiuchao Qian:
A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration. 1-4 - Sujan K. Gonugondla
Energy-Efficient Deep In-memory Architecture for NAND Flash Memories. 1-5 - Vivek Nautiyal, Gaurav Singla, Sagar Dwivedi, Satinderjit Singh, Ingming Chang, Jitendra Dasani, Fakhruddin Ali Bohra:
Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies. 1-5 - Libo Yang, Jiadi Zhu
Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications. 1-5 - Minho Kwon, Boris Murmann:
A New Figure of Merit Equation for Analog-to-Digital Converters in CMOS Image Sensors. 1-5 - Nanqi Liu
Concurrent Sampling with Local Digitization - An Alternative to Analog Test Bus. 1-5 - Tuotian Liao, Lihong Zhang:
Layout-dependent effects aware gm/iD-based many-objective sizing optimization for analog integrated circuits. 1-5 - Antonio D. Martínez-Pérez
Analysis of the Influence of Component Mismatch on Integrated Passive Polyphase Filters. 1-4 - Johan J. Estrada-López, Amr Abuellil, Alfredo Costilla-Reyes
Technology Enabling Circuits and Systems for the Internet-of-Things: An Overview. 1-5 - Yue Zheng, Sumedh Somnath Dhabu, Chip-Hong Chang
Securing IoT Monitoring Device using PUF and Physical Layer Authentication. 1-5 - Marco Carminati, Lorenzo Mezzera, Giorgio Ferrari
A Smart Sensing Node for Pervasive Water Quality Monitoring with Anti-Fouling Self-Diagnostics. 1-5 - Martino Dazzi, Pierpaolo Palestri, Davide Rossi, Andrea Bandiziol, Igor Loi, David E. Bellasi, Luca Benini
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. 1-5 - Mario Osta, Ali Ibrahim
Inexact Arithmetic Circuits for Energy Efficient IoT Sensors Data Processing. 1-4 - Zhongyuan Fang
A Ku-band FMCW Radar on Chip for Wireless Micro Physiological Signal Monitoring by Interferometry Phase Analysis. 1-4 - Mohammad Mehdi Moayer
Ultra-Low Power Wide-Dynamic-Range Universal Interface for Capacitive and Resistive Sensors. 1-5 - Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator. 1-5 - Shirin Pourashraf, Jaime Ramírez-Angulo, Alejandro Díaz-Sánchez:
Ultra Low Voltage Gate Driven Bandpass PGA with Constant Bandwidth. 1-5 - Weiping Wu, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu:
An Accurate dB-Linear Programmable-Gain Amplifier with Temperature-Robust Characteristic. 1-4 - Florian Glaser, Stefan Mach, Abbas Rahimi
An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. 1-5 - Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture Generator for Type-3 Unum Posit Adder/Subtractor. 1-5 - D. Celia, Vinita Vasudevan
Probabilistic Error Modeling for Two-part Segmented Approximate Adders. 1-5 - Joydeep Basu
Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators. 1-5 - Sri Navaneeth Easwaran
1.3A, -2V Tolerant Solenoid Drivers for Pedestrian Protection in Active Hood Lift Systems. 1-4 - Adeboye Stephen Oyeniran
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. 1-5 - Aniruddha Roy, Nitin Agarwal, Pavan K. Kulkarni, Poornima J. Boosi:
MCU-integrated PGA in 65nm CMOS with sub-1% gain error, 180ns acquisition window, and programmable output filter for motor control. 1-5 - Kuangyuan Ying, Hao Gao, Xiaowen Min, Dusan M. Milosevic, Peter G. M. Baltus:
A Wideband Envelope Detector with Low Ripple and High Detection Speed. 1-5 - Sagar Ray, Asif Chowdhury
Enhancing the Stability of Broadband Amplifiers Using Third Order Nested Feedback. 1-4 - Guillermo Royo, Antonio D. Martínez-Pérez
Low-EVM CMOS Transimpedance Amplifier for Intermediate Frequency over Fiber. 1-4 - Antonio J. López-Martín
On the Optimal Current Followers for Wide-Swing Current-Efficient Amplifiers. 1-5 - Ahmed S. Sayed, Hesham N. Ahmed
A 10-W, High Efficiency, Broadband Harmonically Tuned GaN-HEMT Power Amplifier. 1-4 - Zaiming Fu, Jun Liu, Zhixiang Zhang:
Research on A Novel Synthesizing Technology of Fast-edge Pulse with variable Amplitude. 1-5
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