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axi

Here are 91 public repositories matching this topic...

VLSI-Design-Verification-Projects

SACHINUR17 / VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Updated Sep 13, 2025
SystemVerilog

hdl-registers

hdl-registers / hdl-registers

An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

Updated Sep 11, 2025
Python

hdl-modules

hdl-modules / hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Updated Sep 9, 2025
VHDL

pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Sep 9, 2025
SystemVerilog

MicroTCA-Tech-Lab / libudmaio

Userspace I/O library for Xilinx AXI S2MM DMA

fpga soc uio dma pcie userspace-driver axi xdma

Updated Sep 9, 2025
C++

aignacio / jtag_axi

JTAG to AXI master

jtag axi jtag-adapter

Updated Sep 8, 2025
Python

Karan-nevage / AXI-UVC

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

systemverilog axi uvm-verification axi-uvc axi-verification-using-uvm axi-protocol axi-protocol-verification-using-uvm axi-uvm-project

Updated Sep 7, 2025
SystemVerilog

Functional-Bus-Description-Language / afbd

Functional Bus Description Language compiler backend for Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications.

asic fpga eda vlsi axi amba apb ahb

Updated Sep 6, 2025
Go

rggen / rggen-sv-rtl

Common SystemVerilog RTL modules for RgGen

rtl systemverilog axi apb axi4

Updated Sep 5, 2025
SystemVerilog

SystemRDL / PeakRDL

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Aug 27, 2025
Python

Manoj10211021 / book-world

Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.

nodejs express mongodb react-router reactjs mongoose bcrypt cloudinary multer-storage axi

Updated Aug 22, 2025
JavaScript

rggen / rggen

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Sep 13, 2025
Ruby

IPCore-Tests / AXI

performance simulation verification xilinx osvvm axi ipcore

Updated Jul 27, 2025

cong2738 / May_team_project_I2C_SPI

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs

Updated Jul 24, 2025
VHDL

Ajao-Victor / Fol

Fol app is a hands-on full-stack learning app built with React, Node, Express & PostgreSQL. Sign up to explore real-time examples, live code demos, and practical tutorials—all freely accessible and deployed on GitHub to help you learn by doing. Perfect for beginners and curious devs!

nodejs gitignore cors react-router reactjs expressjs body-parser postgresql-database react-router-dom axi react-hooks

Updated Jul 9, 2025
JavaScript

Functional-Bus-Description-Language / go-fbdl

Functional Bus Description Language compiler front-end written in Go.

asic fpga eda vlsi axi amba apb wishbone-bus ahb

Updated Jul 9, 2025
Go

wyvernSemi / mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Jul 8, 2025
VHDL

atfox272 / DVP-RX-Controller

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

camera axi axi4 dvp

Updated May 5, 2025
Verilog

ZipCPU / sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

Updated Apr 24, 2025
Verilog

RadioactiveScandium / Digital-Interfaces

Knowledge hub for digital interfaces

axi amba apb valid-ready-handshake

Updated Apr 23, 2025
SystemVerilog

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