AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Dec 9, 2025 - SystemVerilog
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axi
Here are 92 public repositories matching this topic...
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Dec 3, 2025 - Python
Code generation tool for control and status registers
asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents
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Dec 2, 2025 - Ruby
Knowledge hub for digital interfaces
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Nov 13, 2025 - SystemVerilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
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Oct 18, 2025 - Verilog
Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.
systemverilog axi uvm-verification axi-uvc axi-verification-using-uvm axi-protocol axi-protocol-verification-using-uvm axi-uvm-project
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Sep 24, 2025 - SystemVerilog
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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Sep 13, 2025 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
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Sep 5, 2025 - SystemVerilog
Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.
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Aug 22, 2025 - JavaScript
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Jul 27, 2025
UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol
c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs
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Jul 24, 2025 - VHDL
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